From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 12661 invoked by alias); 24 Nov 2015 00:04:39 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 12641 invoked by uid 89); 24 Nov 2015 00:04:38 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.9 required=5.0 tests=AWL,BAYES_50,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-lf0-f42.google.com Received: from mail-lf0-f42.google.com (HELO mail-lf0-f42.google.com) (209.85.215.42) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Tue, 24 Nov 2015 00:04:37 +0000 Received: by lfs39 with SMTP id 39so767860lfs.3 for ; Mon, 23 Nov 2015 16:04:33 -0800 (PST) MIME-Version: 1.0 X-Received: by 10.112.151.37 with SMTP id un5mr9941799lbb.53.1448323473568; Mon, 23 Nov 2015 16:04:33 -0800 (PST) Received: by 10.114.62.230 with HTTP; Mon, 23 Nov 2015 16:04:33 -0800 (PST) In-Reply-To: <20151123215623.GA21427@ibm-tiger.the-meissners.org> References: <20151123215623.GA21427@ibm-tiger.the-meissners.org> Date: Tue, 24 Nov 2015 00:06:00 -0000 Message-ID: Subject: Re: [PATCH] lround for PowerPC From: David Edelsohn To: Michael Meissner , Richard Biener , Segher Boessenkool , "William J. Schmidt" , GCC Patches Content-Type: text/plain; charset=UTF-8 X-SW-Source: 2015-11/txt/msg02811.txt.bz2 On Mon, Nov 23, 2015 at 4:56 PM, Michael Meissner wrote: > David ping'ed me on internal IRC, and I had a thinko in terms of the use of the > mode attribute. In some of the uses (such as abs, smax, etc.) we want to > use ISA 2.06 instructions on SFmode, while in other uses (add, mul, etc.) we > want to use it only if we have the ISA 2.07 instrucitons. > > I have split these mode attributes into Fv and Fv2 and gone through all of the > uses in the compiler to use the appropriate attribute. I have built a cross > compiler on x86, but it blew up on a big endian power7 with a segmentation > violation that I need to look into. I'm also building on a little endian > power8 right now, and it has gotten further. > > 2015-11-23 David Edelsohn > Michael Meissner > > * config/rs6000/rs6000.md (UNSPEC_XSRDPI): New unspec. > (Fv2): New mode attribute to be used when ISA 2.06 instructions > are used on SF/DF values. > (abs2_fpr): Use instead of . > (nabs2_fpr): Likewise. > (neg2_fpr): Likewise. > (copysign3_fcpsgn): Likewise. > (smax3_vsx): Likewise. > (smin3_vsx): Likewise. > (floatsi2_lfiwax): Likewise. > (floatunssi2_lfiwz): Likewise. > (fctiwz_): Likewise. > (fctiwuz_): Likewise. > (btrunc2): Likewise. > (ceil2): Likewise. > (floor2): Likewise. > (xsrdpi): Add support for the lround function. > (lround2): Likewise. I would prefer that you reverse the meaning of "Fv" and "Fv2". "Fv" corresponds to VSX2 and "Fv2" corresponds to VSX, which is confusing for anyone trying to make sense of this in the future. Also, the lrounddi2 pattern should use "Fv" not "wa" from my original patch. And the ChangeLog entry should list lrounddi2. Okay with those changes, after the cause of the SEGV is diagnosed and fixed. Thanks, David