From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ua1-x92e.google.com (mail-ua1-x92e.google.com [IPv6:2607:f8b0:4864:20::92e]) by sourceware.org (Postfix) with ESMTPS id 4C4A43858D39 for ; Mon, 13 Dec 2021 22:22:18 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 4C4A43858D39 Received: by mail-ua1-x92e.google.com with SMTP id 30so31738099uag.13 for ; Mon, 13 Dec 2021 14:22:18 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=6hzz42ojqmFSZo15adMaWsa7Vo8Vt24a3UrGdSM0fng=; b=kl+UBvG7yoaCdPxPC+081jTVxVjHaieNNnTylIx2DNkUS2Kz9xVkTz6jnVI5uJJbnO B0eNXQMmFXDo3GSr4Y6ByP/dQrmWoeXCF25w8f9uSeislVwa8735NhupNbGXpR8zXk7r /AtOymoS6ZMF/bwpEQ6V3JtH+9JvdrIdP0zoz9MrLwAI/ZZ5TxaZvVY6dmq/S9ylXNvH 5zvrXetJMrd3AxNqqoXq3azEbtFN5FHfzT/SvND2g0PZZTBEaD0FFnMj8zl7He60ESWt AxcVP8B7iv95Qn/yOJQrsFVxbzQM9GOrC1fjvnXusd2dd3EnXdRimlH3MIzW7JNYBI7J I4dw== X-Gm-Message-State: AOAM530hJSeuSoJ3zScfblL58IZfa1oVkj4XWAOUF3GmNIofGJaCd7uP gAAFPh4BQiik2qkkjTQPRu5EyMncg7QzSNxCF16INZMl X-Google-Smtp-Source: ABdhPJyZFPPYjuetYamu0bAyIacIGDmME/tVO7x1U1iQBA4z1vfVnFwZ9T9E+7xmAeYHjPF0OiYXf7yvLvts0teuOm8= X-Received: by 2002:a05:6102:38c7:: with SMTP id k7mr1708849vst.45.1639434137796; Mon, 13 Dec 2021 14:22:17 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: David Edelsohn Date: Mon, 13 Dec 2021 17:22:06 -0500 Message-ID: Subject: Re: [PATCH, rs6000] new split pattern for TI to V1TI move [PR103124] To: HAO CHEN GUI Cc: gcc-patches , Segher Boessenkool , Bill Schmidt Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 13 Dec 2021 22:22:19 -0000 On Sun, Dec 12, 2021 at 10:00 PM HAO CHEN GUI wrote: > > Hi, > This patch defines a new split pattern for TI to V1TI move. The pattern concatenates two subreg:DI of > a TI to a V2DI, then move the V2DI to V1TI. With the pattern, the subreg pass can do register split for > TI when there is a TI to V1TI move. The patch optimizes one unnecessary "mr" out on P9. The new > test case illustrates it. > > Bootstrapped and tested on powerpc64-linux BE and LE with no regressions. Is this okay for trunk? > Any recommendations? Thanks a lot. > > ChangeLog > 2021-12-13 Haochen Gui > > gcc/ > * config/rs6000/vsx.md (split pattern for TI to V1TI move): Defined. > > gcc/testsuite/ > * gcc.target/powerpc/pr103124.c: New testcase. > > > patch.diff > diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md > index bf033e31c1c..7bca7780735 100644 > --- a/gcc/config/rs6000/vsx.md > +++ b/gcc/config/rs6000/vsx.md > @@ -6589,3 +6589,19 @@ (define_insn "xxeval" > [(set_attr "type" "vecperm") > (set_attr "prefixed" "yes")]) > > +;; split TI to V1TI move > +(define_split > + [(set (match_operand:V1TI 0 "vsx_register_operand") > + (subreg:V1TI > + (match_operand:TI 1 "int_reg_operand") 0 ))] > + "TARGET_P9_VECTOR && !reload_completed" > + [(const_int 0)] > +{ > + rtx tmp1 = simplify_gen_subreg (DImode, operands[1], TImode, 0); > + rtx tmp2 = simplify_gen_subreg (DImode, operands[1], TImode, 8); > + rtx tmp3 = gen_reg_rtx (V2DImode); > + emit_insn (gen_vsx_concat_v2di (tmp3, tmp1, tmp2)); > + rtx tmp4 = simplify_gen_subreg (V1TImode, tmp3, V2DImode, 0); > + emit_move_insn (operands[0], tmp4); > + DONE; > +}) > diff --git a/gcc/testsuite/gcc.target/powerpc/pr103124.c b/gcc/testsuite/gcc.target/powerpc/pr103124.c > new file mode 100644 > index 00000000000..724492dbcd2 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/powerpc/pr103124.c > @@ -0,0 +1,11 @@ > +/* { dg-do compile { target { powerpc*-*-* && lp64 } } */ Please don't include the "powerpc" target selector in the gcc.target/powerpc directory. Just use lp64. > +/* { dg-require-effective-target powerpc_p9vector_ok } */ > +/* { dg-options "-O2 -mdejagnu-cpu=power9" } */ > +/* { dg-final { scan-assembler-not "\mmr\M" } } */ > + > +vector __int128 add (long long a) > +{ > + vector __int128 b; > + b = (vector __int128) {a}; > + return b; > +} Okay with that change. Thanks, David