Re: RISC-V: fix a typo in riscv.h

[Yeting Kuo <fakepaper56@gmail.com>]

Hi Kito,

> > Could you provide a test case for that?
>
I add the test case and update the git message.
    RISC-V: fix a typo in riscv.h

    The missing parentheses would make shorten-memrefs pass give a
    wrong base when the offset of load/store is not multiple of 4.

    2020-09-14 Yeting Kuo <fakepaper56@gmail.com>

    gcc/ChangeLog:
            * config/riscv/riscv.h

    gcc/testsuite/ChangeLog:
            * gcc.target/riscv/shorten-memrefs-8.c: New test.

diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 9f67d82e74e..b7b4a1c88a5 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -941,7 +941,7 @@ extern unsigned riscv_stack_boundary;

 /* This is the maximum value that can be represented in a compressed
load/store
    offset (an unsigned 5-bit value scaled by 4).  */
-#define CSW_MAX_OFFSET ((4LL << C_S_BITS) - 1) & ~3
+#define CSW_MAX_OFFSET (((4LL << C_S_BITS) - 1) & ~3)

 /* Called from RISCV_REORG, this is defined in riscv-sr.c.  */
diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c
b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c
new file mode 100644
index 00000000000..f7428bd86cb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c
@@ -0,0 +1,26 @@
+/* { dg-options "-Os -march=rv32imc -mabi=ilp32" } */
+
+/* shorten_memrefs should use a correct base address*/
+
+void
+store (char *p, int k)
+{
+  *(int *)(p + 17) = k;
+  *(int *)(p + 21) = k;
+  *(int *)(p + 25) = k;
+  *(int *)(p + 29) = k;
+}
+
+int
+load (char *p)
+{
+  int a = 0;
+  a += *(int *)(p + 17);
+  a += *(int *)(p + 21);
+  a += *(int *)(p + 25);
+  a += *(int *)(p + 29);
+  return a;
+}
+
+/* { dg-final { scan-assembler "store:\n\taddi\ta\[0-7\],a\[0-7\],1" } } */
+/* { dg-final { scan-assembler "load:\n\taddi\ta\[0-7\],a\[0-7\],1" } } */

Thanks,
Yeting