From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [IPv6:2a00:1450:4864:20::344]) by sourceware.org (Postfix) with ESMTPS id 41DDF3857C57 for ; Mon, 14 Sep 2020 11:06:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 41DDF3857C57 Received: by mail-wm1-x344.google.com with SMTP id l9so10798552wme.3 for ; Mon, 14 Sep 2020 04:06:38 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=DDgZ/AujJS8RIZQTlPxDVTGvIU5tf/RMO4mtFmu+7U4=; b=QyBT3Gv3up4iJYARyIgxosknmGDnZu8OAIGSoqmDYSqhcroxqFIFWD8zj+s9ON8g52 6gAoR9ObSg4F4VOrKi3Rpj6cRZ6OCypeWQZ5WyjfiWimLI+1B4auKr5MdleIyxBPD529 ovN7FCt0LoYgYKbYQvVau9eDKDP5YvGhDkCk8tijmGrC+TI3rfJkDWLB2uToAHRUkDUK MTbQPgC9UqS8vHP9byuHeFJJPm+ZcG3UkLfkPsyuccwauR14ThMN/t3BrR9o/VzQpMJP CWAaCGDEG4WqSYor07SYKo7WiBDHy3/HKbQZupJD819hF86nD4Ge78ex+BkgFeDZYnh2 MkfQ== X-Gm-Message-State: AOAM530HopWV7yNDtc680w/tPsyWH13OLdkCZAhtd8D0MimUJfwhKw30 9D0LE3TLLj21qK6tI+TzkLb6nTyfhS16l9ckxTg= X-Google-Smtp-Source: ABdhPJyHH4Z29HJP0HCn03gvEU8eZJtz2cxr+NnGatfuWaPlmk4U5ocQHH2y7FebR0O/wIYykAc0lrgs4VdL9ipm1XY= X-Received: by 2002:a1c:7d0c:: with SMTP id y12mr14573977wmc.103.1600081597434; Mon, 14 Sep 2020 04:06:37 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Yeting Kuo Date: Mon, 14 Sep 2020 19:06:26 +0800 Message-ID: Subject: Re: RISC-V: fix a typo in riscv.h To: Kito Cheng Cc: GCC Patches X-Spam-Status: No, score=-6.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, GIT_PATCH_0, HTML_MESSAGE, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org Content-Type: text/plain; charset="UTF-8" X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 14 Sep 2020 11:06:39 -0000 Hi Kito, > > Could you provide a test case for that? > I add the test case and update the git message. RISC-V: fix a typo in riscv.h The missing parentheses would make shorten-memrefs pass give a wrong base when the offset of load/store is not multiple of 4. 2020-09-14 Yeting Kuo gcc/ChangeLog: * config/riscv/riscv.h gcc/testsuite/ChangeLog: * gcc.target/riscv/shorten-memrefs-8.c: New test. diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 9f67d82e74e..b7b4a1c88a5 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -941,7 +941,7 @@ extern unsigned riscv_stack_boundary; /* This is the maximum value that can be represented in a compressed load/store offset (an unsigned 5-bit value scaled by 4). */ -#define CSW_MAX_OFFSET ((4LL << C_S_BITS) - 1) & ~3 +#define CSW_MAX_OFFSET (((4LL << C_S_BITS) - 1) & ~3) /* Called from RISCV_REORG, this is defined in riscv-sr.c. */ diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c new file mode 100644 index 00000000000..f7428bd86cb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c @@ -0,0 +1,26 @@ +/* { dg-options "-Os -march=rv32imc -mabi=ilp32" } */ + +/* shorten_memrefs should use a correct base address*/ + +void +store (char *p, int k) +{ + *(int *)(p + 17) = k; + *(int *)(p + 21) = k; + *(int *)(p + 25) = k; + *(int *)(p + 29) = k; +} + +int +load (char *p) +{ + int a = 0; + a += *(int *)(p + 17); + a += *(int *)(p + 21); + a += *(int *)(p + 25); + a += *(int *)(p + 29); + return a; +} + +/* { dg-final { scan-assembler "store:\n\taddi\ta\[0-7\],a\[0-7\],1" } } */ +/* { dg-final { scan-assembler "load:\n\taddi\ta\[0-7\],a\[0-7\],1" } } */ Thanks, Yeting