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From: Yeting Kuo <fakepaper56@gmail.com>
Date: Mon, 14 Sep 2020 15:15:05 +0800
Message-ID: <CAGhUdNiwPvWG_kBWMZoq5XUGUhiqLVnyzQtshxQAA2J9Ff1ZLw@mail.gmail.com>
Subject: RISC-V: fix a typo in riscv.h
To: gcc-patches@gcc.gnu.org
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Hi all,

The patch fixes a typo that would make some errors in fast-unaligned-access
targets.

    RISC-V: fix a typo in riscv.h

    2020-09-14 Yeting Kuo <fakepaper56@gmail.com>

    gcc/
            * config/riscv/riscv.h

diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 9f67d82e74e..b7b4a1c88a5 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -941,7 +941,7 @@ extern unsigned riscv_stack_boundary;

 /* This is the maximum value that can be represented in a compressed
load/store
    offset (an unsigned 5-bit value scaled by 4).  */
-#define CSW_MAX_OFFSET ((4LL << C_S_BITS) - 1) & ~3
+#define CSW_MAX_OFFSET (((4LL << C_S_BITS) - 1) & ~3)

 /* Called from RISCV_REORG, this is defined in riscv-sr.c.  */

Best Regard,
Yeting