* [wwwdocs] IA-32/x86-64 Changes for upcoming 4.7.0 series
@ 2011-09-22 11:57 Kirill Yukhin
2011-09-22 12:09 ` Kirill Yukhin
0 siblings, 1 reply; 15+ messages in thread
From: Kirill Yukhin @ 2011-09-22 11:57 UTC (permalink / raw)
To: gcc-patches List; +Cc: Kirill Yukhin, H.J. Lu, Uros Bizjak
[-- Attachment #1: Type: text/plain, Size: 157 bytes --]
Hi,
I've perepared a list of IA-32/x86-64 related changes (for changes.html).
Could you please have a look and if there're no objections commit?
Thanks, K
[-- Attachment #2: 4.7.0-x86-changes.html.www.patch --]
[-- Type: application/octet-stream, Size: 1720 bytes --]
Index: htdocs/gcc-4.7/changes.html
===================================================================
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.7/changes.html,v
retrieving revision 1.28
diff -p -r1.28 changes.html
*** htdocs/gcc-4.7/changes.html 12 Sep 2011 07:46:05 -0000 1.28
--- htdocs/gcc-4.7/changes.html 22 Sep 2011 10:20:06 -0000
*************** struct F: E { }; // error: deriving from
*** 270,275 ****
--- 270,291 ----
<h3>IA-32/x86-64</h3>
<ul>
+ <li>Support for Intel AVX2 intrinsics, built-in functions and code generation is
+ available via <code>-mavx2</code>.</li>
+ <li>Support for Intel BMI2 intrinsics, built-in functions and code generation is
+ available via <code>-bmi2</code>.</li>
+ <li>Implementation and automatic generation of <code>__builtin_clz*</code>
+ using <code>lzcnt</code> instruction is available via <code>-mlzcnt</code>.</li>
+ <li>Support for Intel FMA3 intrinsics and code generation is available via
+ <code>-mfma</code>.</li>
+ <li>A new <code>-mfsgsbase</code> option is available to enable GCC
+ to use new segment register read/write instructions through dedicated built-ins.</li>
+ <li>Support for new Intel <code>rdrnd</code> instruction is available via <code>-mrdrnd</code>.</li>
+ <li>Two additional AVX vector conversion instructions are available via <code>-mf16c</code>.</li>
+ <li>Support for new Intel processor codename IvyBridge with RDRND, FSGSBASE and F16C
+ is available through <code>-march=core-avx-i</code>.
+ <li>Support for new Intel processor codename Haswell with AVX2, FMA, BMI,
+ BMI2, LZCNT is available through <code>-march=core-avx2</code>.
<li>...</li>
</ul>
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [wwwdocs] IA-32/x86-64 Changes for upcoming 4.7.0 series
2011-09-22 11:57 [wwwdocs] IA-32/x86-64 Changes for upcoming 4.7.0 series Kirill Yukhin
@ 2011-09-22 12:09 ` Kirill Yukhin
2011-09-24 21:31 ` Gerald Pfeifer
0 siblings, 1 reply; 15+ messages in thread
From: Kirill Yukhin @ 2011-09-22 12:09 UTC (permalink / raw)
To: gcc-patches List; +Cc: Kirill Yukhin, H.J. Lu, Uros Bizjak
[-- Attachment #1: Type: text/plain, Size: 267 bytes --]
a typo fixed.
K
On Thu, Sep 22, 2011 at 2:28 PM, Kirill Yukhin <kirill.yukhin@gmail.com> wrote:
> Hi,
> I've perepared a list of IA-32/x86-64 related changes (for changes.html).
>
> Could you please have a look and if there're no objections commit?
>
> Thanks, K
>
[-- Attachment #2: 4.7.0-x86-changes.html.www.patch --]
[-- Type: application/octet-stream, Size: 1721 bytes --]
Index: htdocs/gcc-4.7/changes.html
===================================================================
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.7/changes.html,v
retrieving revision 1.28
diff -p -r1.28 changes.html
*** htdocs/gcc-4.7/changes.html 12 Sep 2011 07:46:05 -0000 1.28
--- htdocs/gcc-4.7/changes.html 22 Sep 2011 11:19:14 -0000
*************** struct F: E { }; // error: deriving from
*** 270,275 ****
--- 270,291 ----
<h3>IA-32/x86-64</h3>
<ul>
+ <li>Support for Intel AVX2 intrinsics, built-in functions and code generation is
+ available via <code>-mavx2</code>.</li>
+ <li>Support for Intel BMI2 intrinsics, built-in functions and code generation is
+ available via <code>-mbmi2</code>.</li>
+ <li>Implementation and automatic generation of <code>__builtin_clz*</code>
+ using <code>lzcnt</code> instruction is available via <code>-mlzcnt</code>.</li>
+ <li>Support for Intel FMA3 intrinsics and code generation is available via
+ <code>-mfma</code>.</li>
+ <li>A new <code>-mfsgsbase</code> option is available to enable GCC
+ to use new segment register read/write instructions through dedicated built-ins.</li>
+ <li>Support for new Intel <code>rdrnd</code> instruction is available via <code>-mrdrnd</code>.</li>
+ <li>Two additional AVX vector conversion instructions are available via <code>-mf16c</code>.</li>
+ <li>Support for new Intel processor codename IvyBridge with RDRND, FSGSBASE and F16C
+ is available through <code>-march=core-avx-i</code>.
+ <li>Support for new Intel processor codename Haswell with AVX2, FMA, BMI,
+ BMI2, LZCNT is available through <code>-march=core-avx2</code>.
<li>...</li>
</ul>
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [wwwdocs] IA-32/x86-64 Changes for upcoming 4.7.0 series
2011-09-22 12:09 ` Kirill Yukhin
@ 2011-09-24 21:31 ` Gerald Pfeifer
2011-09-27 14:36 ` Kirill Yukhin
0 siblings, 1 reply; 15+ messages in thread
From: Gerald Pfeifer @ 2011-09-24 21:31 UTC (permalink / raw)
To: Kirill Yukhin; +Cc: gcc-patches List, H.J. Lu, Uros Bizjak
On Thu, 22 Sep 2011, Kirill Yukhin wrote:
> a typo fixed.
Thanks, Kirill. Note you were attaching the patch as
Application/OCTET-STREAM which does not generally view nicely for
others; perhaps just include the patch in the body of the mail to
avoid that?
Index: htdocs/gcc-4.7/changes.html
===================================================================
+ <li>Implementation and automatic generation of <code>__builtin_clz*</code>
+ using <code>lzcnt</code> instruction is available via <code>-mlzcnt</code>.</li>
...using the ... instruction.... (Add "the").
+ <li>A new <code>-mfsgsbase</code> option is available to enable GCC
+ to use new segment register read/write instructions through dedicated built-ins.</li>
Perhaps say "command-line option" instead of just option? Though we
don't have that in the earlier cases either.
And "available that makes GCC I'm a bit use"?
How does this happen via built-ins? From a user perspective, isn't this
just emitting the respective assember instructions? If so, perhaps just
say "that makes GCC generate...."
+ <li>Support for new Intel <code>rdrnd</code> instruction is available via <code>-mrdrnd</code>.</li>
"the new Intel"
Fine from my perspective with these changes, though please give an
x86 maintainer time to chime in, too, before you commit.
Gerald
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [wwwdocs] IA-32/x86-64 Changes for upcoming 4.7.0 series
2011-09-24 21:31 ` Gerald Pfeifer
@ 2011-09-27 14:36 ` Kirill Yukhin
2011-09-27 17:03 ` Gerald Pfeifer
0 siblings, 1 reply; 15+ messages in thread
From: Kirill Yukhin @ 2011-09-27 14:36 UTC (permalink / raw)
To: Gerald Pfeifer; +Cc: gcc-patches List, H.J. Lu, Uros Bizjak
Hi,
Gerald, thanks for fixing my "excellent" English :)
Here is updated patch:
Index: htdocs/gcc-4.7/changes.html
===================================================================
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.7/changes.html,v
retrieving revision 1.28
diff -p -r1.28 changes.html
*** htdocs/gcc-4.7/changes.html 12 Sep 2011 07:46:05 -0000 1.28
--- htdocs/gcc-4.7/changes.html 27 Sep 2011 13:03:09 -0000
*************** struct F: E { }; // error: deriving from
*** 270,275 ****
--- 270,291 ----
<h3>IA-32/x86-64</h3>
<ul>
+ <li>Support for Intel AVX2 intrinsics, built-in functions and
code generation is
+ available via <code>-mavx2</code>.</li>
+ <li>Support for Intel BMI2 intrinsics, built-in functions and
code generation is
+ available via <code>-mbmi2</code>.</li>
+ <li>Implementation and automatic generation of
<code>__builtin_clz*</code>
+ using the <code>lzcnt</code> instruction is available via
<code>-mlzcnt</code>.</li>
+ <li>Support for Intel FMA3 intrinsics and code generation is available via
+ <code>-mfma</code>.</li>
+ <li>A new <code>-mfsgsbase</code> command-line option is
available that makes GCC
+ generate new segment register read/write instructions through
dedicated built-ins.</li>
+ <li>Support for new Intel <code>rdrnd</code> instruction is
available via <code>-mrdrnd</code>.</li>
+ <li>Two additional AVX vector conversion instructions are
available via <code>-mf16c</code>.</li>
+ <li>Support for new Intel processor codename IvyBridge with
RDRND, FSGSBASE and F16C
+ is available through <code>-march=core-avx-i</code>.
+ <li>Support for the new Intel processor codename Haswell with
AVX2, FMA, BMI,
+ BMI2, LZCNT is available through <code>-march=core-avx2</code>.
<li>...</li>
</ul>
So, if you are ok, let's wait a couple of days for maintainers inputs.
Thanks, K
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [wwwdocs] IA-32/x86-64 Changes for upcoming 4.7.0 series
2011-09-27 14:36 ` Kirill Yukhin
@ 2011-09-27 17:03 ` Gerald Pfeifer
2011-09-30 12:00 ` Kirill Yukhin
0 siblings, 1 reply; 15+ messages in thread
From: Gerald Pfeifer @ 2011-09-27 17:03 UTC (permalink / raw)
To: Kirill Yukhin; +Cc: gcc-patches List, H.J. Lu, Uros Bizjak
On Tue, 27 Sep 2011, Kirill Yukhin wrote:
> So, if you are ok, let's wait a couple of days for maintainers inputs.
Yep, looks good. Unless you hear to the contrary from one of the
x86 maintainers, I suggest you go ahead and commit in two days.
Gerald
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [wwwdocs] IA-32/x86-64 Changes for upcoming 4.7.0 series
2011-09-27 17:03 ` Gerald Pfeifer
@ 2011-09-30 12:00 ` Kirill Yukhin
2011-09-30 16:52 ` H.J. Lu
0 siblings, 1 reply; 15+ messages in thread
From: Kirill Yukhin @ 2011-09-30 12:00 UTC (permalink / raw)
To: Gerald Pfeifer; +Cc: gcc-patches List, H.J. Lu, Uros Bizjak
Okay, seems maintainers have no objections
Could anybody please commit that to wwwdocs?
Thanks, K
On Tue, Sep 27, 2011 at 8:19 PM, Gerald Pfeifer <gerald@pfeifer.com> wrote:
> On Tue, 27 Sep 2011, Kirill Yukhin wrote:
>> So, if you are ok, let's wait a couple of days for maintainers inputs.
>
> Yep, looks good. Unless you hear to the contrary from one of the
> x86 maintainers, I suggest you go ahead and commit in two days.
>
> Gerald
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [wwwdocs] IA-32/x86-64 Changes for upcoming 4.7.0 series
2011-09-30 12:00 ` Kirill Yukhin
@ 2011-09-30 16:52 ` H.J. Lu
2011-10-03 17:20 ` Kirill Yukhin
0 siblings, 1 reply; 15+ messages in thread
From: H.J. Lu @ 2011-09-30 16:52 UTC (permalink / raw)
To: Kirill Yukhin; +Cc: Gerald Pfeifer, gcc-patches List, Uros Bizjak
On Fri, Sep 30, 2011 at 4:11 AM, Kirill Yukhin <kirill.yukhin@gmail.com> wrote:
> Okay, seems maintainers have no objections
>
> Could anybody please commit that to wwwdocs?
>
Your patch can't be applied. Please provide a proper patch.
Thanks.
--
H.J.
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [wwwdocs] IA-32/x86-64 Changes for upcoming 4.7.0 series
2011-09-30 16:52 ` H.J. Lu
@ 2011-10-03 17:20 ` Kirill Yukhin
2011-10-03 18:09 ` H.J. Lu
0 siblings, 1 reply; 15+ messages in thread
From: Kirill Yukhin @ 2011-10-03 17:20 UTC (permalink / raw)
To: H.J. Lu; +Cc: Gerald Pfeifer, gcc-patches List, Uros Bizjak
[-- Attachment #1: Type: text/plain, Size: 102 bytes --]
Hi,
I did
cvs update
cvs diff > ~/changes.html.www.patch
It is attached. Is it applying?
Thanks, K
[-- Attachment #2: changes.html.www.patch --]
[-- Type: application/octet-stream, Size: 1472 bytes --]
Index: htdocs/gcc-4.7/changes.html
===================================================================
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.7/changes.html,v
retrieving revision 1.42
diff -r1.42 changes.html
396a397,412
> <li>Support for Intel AVX2 intrinsics, built-in functions and code generation is
> available via <code>-mavx2</code>.</li>
> <li>Support for Intel BMI2 intrinsics, built-in functions and code generation is
> available via <code>-mbmi2</code>.</li>
> <li>Implementation and automatic generation of <code>__builtin_clz*</code>
> using the <code>lzcnt</code> instruction is available via <code>-mlzcnt</code>.</li>
> <li>Support for Intel FMA3 intrinsics and code generation is available via
> <code>-mfma</code>.</li>
> <li>A new <code>-mfsgsbase</code> command-line option is available that makes GCC
> generate new segment register read/write instructions through dedicated built-ins.</li>
> <li>Support for new Intel <code>rdrnd</code> instruction is available via <code>-mrdrnd</code>.</li>
> <li>Two additional AVX vector conversion instructions are available via <code>-mf16c</code>.</li>
> <li>Support for new Intel processor codename IvyBridge with RDRND, FSGSBASE and F16C
> is available through <code>-march=core-avx-i</code>.
> <li>Support for the new Intel processor codename Haswell with AVX2, FMA, BMI,
> BMI2, LZCNT is available through <code>-march=core-avx2</code>.
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [wwwdocs] IA-32/x86-64 Changes for upcoming 4.7.0 series
2011-10-03 17:20 ` Kirill Yukhin
@ 2011-10-03 18:09 ` H.J. Lu
2011-10-03 18:23 ` Kirill Yukhin
0 siblings, 1 reply; 15+ messages in thread
From: H.J. Lu @ 2011-10-03 18:09 UTC (permalink / raw)
To: Kirill Yukhin; +Cc: Gerald Pfeifer, gcc-patches List, Uros Bizjak
On Mon, Oct 3, 2011 at 10:19 AM, Kirill Yukhin <kirill.yukhin@gmail.com> wrote:
> Hi,
> I did
>
> cvs update
> cvs diff > ~/changes.html.www.patch
>
> It is attached. Is it applying?
>
> Thanks, K
>
Please use "cvs diff -up" to generate the patch.
--
H.J.
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [wwwdocs] IA-32/x86-64 Changes for upcoming 4.7.0 series
2011-10-03 18:09 ` H.J. Lu
@ 2011-10-03 18:23 ` Kirill Yukhin
2011-10-03 19:01 ` H.J. Lu
0 siblings, 1 reply; 15+ messages in thread
From: Kirill Yukhin @ 2011-10-03 18:23 UTC (permalink / raw)
To: H.J. Lu; +Cc: Gerald Pfeifer, gcc-patches List, Uros Bizjak
[-- Attachment #1: Type: text/plain, Size: 361 bytes --]
Done
K
On Mon, Oct 3, 2011 at 10:09 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
> On Mon, Oct 3, 2011 at 10:19 AM, Kirill Yukhin <kirill.yukhin@gmail.com> wrote:
>> Hi,
>> I did
>>
>> cvs update
>> cvs diff > ~/changes.html.www.patch
>>
>> It is attached. Is it applying?
>>
>> Thanks, K
>>
>
> Please use "cvs diff -up" to generate the patch.
>
>
> --
> H.J.
>
[-- Attachment #2: changes.html.www.patch --]
[-- Type: application/octet-stream, Size: 1665 bytes --]
Index: htdocs/gcc-4.7/changes.html
===================================================================
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.7/changes.html,v
retrieving revision 1.42
diff -u -p -r1.42 changes.html
--- htdocs/gcc-4.7/changes.html 3 Oct 2011 08:47:18 -0000 1.42
+++ htdocs/gcc-4.7/changes.html 3 Oct 2011 18:21:08 -0000
@@ -394,6 +394,22 @@ struct A {
<h3>IA-32/x86-64</h3>
<ul>
+ <li>Support for Intel AVX2 intrinsics, built-in functions and code generation is
+ available via <code>-mavx2</code>.</li>
+ <li>Support for Intel BMI2 intrinsics, built-in functions and code generation is
+ available via <code>-mbmi2</code>.</li>
+ <li>Implementation and automatic generation of <code>__builtin_clz*</code>
+ using the <code>lzcnt</code> instruction is available via <code>-mlzcnt</code>.</li>
+ <li>Support for Intel FMA3 intrinsics and code generation is available via
+ <code>-mfma</code>.</li>
+ <li>A new <code>-mfsgsbase</code> command-line option is available that makes GCC
+ generate new segment register read/write instructions through dedicated built-ins.</li>
+ <li>Support for new Intel <code>rdrnd</code> instruction is available via <code>-mrdrnd</code>.</li>
+ <li>Two additional AVX vector conversion instructions are available via <code>-mf16c</code>.</li>
+ <li>Support for new Intel processor codename IvyBridge with RDRND, FSGSBASE and F16C
+ is available through <code>-march=core-avx-i</code>.
+ <li>Support for the new Intel processor codename Haswell with AVX2, FMA, BMI,
+ BMI2, LZCNT is available through <code>-march=core-avx2</code>.
<li>...</li>
</ul>
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [wwwdocs] IA-32/x86-64 Changes for upcoming 4.7.0 series
2011-10-03 18:23 ` Kirill Yukhin
@ 2011-10-03 19:01 ` H.J. Lu
2011-10-03 19:39 ` H.J. Lu
0 siblings, 1 reply; 15+ messages in thread
From: H.J. Lu @ 2011-10-03 19:01 UTC (permalink / raw)
To: Kirill Yukhin; +Cc: Gerald Pfeifer, gcc-patches List, Uros Bizjak
On Mon, Oct 3, 2011 at 11:23 AM, Kirill Yukhin <kirill.yukhin@gmail.com> wrote:
> Done
>
> K
>
> On Mon, Oct 3, 2011 at 10:09 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
>> On Mon, Oct 3, 2011 at 10:19 AM, Kirill Yukhin <kirill.yukhin@gmail.com> wrote:
>>> Hi,
>>> I did
>>>
>>> cvs update
>>> cvs diff > ~/changes.html.www.patch
>>>
>>> It is attached. Is it applying?
>>>
>>> Thanks, K
>>>
>>
>> Please use "cvs diff -up" to generate the patch.
>>
>>
The new patch looks very strange. I don't think it can apply.
--
H.J.
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [wwwdocs] IA-32/x86-64 Changes for upcoming 4.7.0 series
2011-10-03 19:01 ` H.J. Lu
@ 2011-10-03 19:39 ` H.J. Lu
2011-10-04 9:30 ` Gerald Pfeifer
0 siblings, 1 reply; 15+ messages in thread
From: H.J. Lu @ 2011-10-03 19:39 UTC (permalink / raw)
To: Kirill Yukhin; +Cc: Gerald Pfeifer, gcc-patches List, Uros Bizjak
On Mon, Oct 3, 2011 at 12:01 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
> On Mon, Oct 3, 2011 at 11:23 AM, Kirill Yukhin <kirill.yukhin@gmail.com> wrote:
>> Done
>>
>> K
>>
>> On Mon, Oct 3, 2011 at 10:09 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>> On Mon, Oct 3, 2011 at 10:19 AM, Kirill Yukhin <kirill.yukhin@gmail.com> wrote:
>>>> Hi,
>>>> I did
>>>>
>>>> cvs update
>>>> cvs diff > ~/changes.html.www.patch
>>>>
>>>> It is attached. Is it applying?
>>>>
>>>> Thanks, K
>>>>
>>>
>>> Please use "cvs diff -up" to generate the patch.
>>>
>>>
>
I checked it in.
Thanks.
--
H.J.
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [wwwdocs] IA-32/x86-64 Changes for upcoming 4.7.0 series
2011-10-03 19:39 ` H.J. Lu
@ 2011-10-04 9:30 ` Gerald Pfeifer
2011-10-04 14:43 ` H.J. Lu
0 siblings, 1 reply; 15+ messages in thread
From: Gerald Pfeifer @ 2011-10-04 9:30 UTC (permalink / raw)
To: H.J. Lu; +Cc: Kirill Yukhin, gcc-patches List, Uros Bizjak
On Mon, 3 Oct 2011, H.J. Lu wrote:
> I checked it in.
Thanks, H.J.
This needed a small markup fix which I just applied; see below.
Gerald
Index: changes.html
===================================================================
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.7/changes.html,v
retrieving revision 1.43
diff -u -r1.43 changes.html
--- changes.html 3 Oct 2011 19:38:23 -0000 1.43
+++ changes.html 4 Oct 2011 09:27:15 -0000
@@ -407,9 +407,9 @@
<li>Support for new Intel <code>rdrnd</code> instruction is available via <code>-mrdrnd</code>.</li>
<li>Two additional AVX vector conversion instructions are available via <code>-mf16c</code>.</li>
<li>Support for new Intel processor codename IvyBridge with RDRND, FSGSBASE and F16C
- is available through <code>-march=core-avx-i</code>.
+ is available through <code>-march=core-avx-i</code>.</li>
<li>Support for the new Intel processor codename Haswell with AVX2, FMA, BMI,
- BMI2, LZCNT is available through <code>-march=core-avx2</code>.
+ BMI2, LZCNT is available through <code>-march=core-avx2</code>.</li>
<li>...</li>
</ul>
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2011-10-05 10:09 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2011-09-22 11:57 [wwwdocs] IA-32/x86-64 Changes for upcoming 4.7.0 series Kirill Yukhin
2011-09-22 12:09 ` Kirill Yukhin
2011-09-24 21:31 ` Gerald Pfeifer
2011-09-27 14:36 ` Kirill Yukhin
2011-09-27 17:03 ` Gerald Pfeifer
2011-09-30 12:00 ` Kirill Yukhin
2011-09-30 16:52 ` H.J. Lu
2011-10-03 17:20 ` Kirill Yukhin
2011-10-03 18:09 ` H.J. Lu
2011-10-03 18:23 ` Kirill Yukhin
2011-10-03 19:01 ` H.J. Lu
2011-10-03 19:39 ` H.J. Lu
2011-10-04 9:30 ` Gerald Pfeifer
2011-10-04 14:43 ` H.J. Lu
2011-10-05 10:22 ` Kirill Yukhin
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