From: Shiva Chen <shiva0217@gmail.com>
To: Jeff Law <law@redhat.com>, "gcc@gcc.gnu.org" <gcc@gcc.gnu.org>,
gcc-patches@gcc.gnu.org
Subject: Re: ira.c update_equiv_regs patch causes gcc/testsuite/gcc.target/arm/pr43920-2.c regression
Date: Mon, 20 Apr 2015 07:09:00 -0000 [thread overview]
Message-ID: <CAH=PD7a0ofWfFBnJqD=6e5uYJY8v_GRjcvRuOBvy-x3EZNzFJg@mail.gmail.com> (raw)
In-Reply-To: <55312EDF.90005@redhat.com>
[-- Attachment #1: Type: text/plain, Size: 3719 bytes --]
Hi, Jeff
Thanks for your advice.
can_replace_by.patch is the new patch to handle both cases.
pr43920-2.c.244r.jump2.ori is the original jump2 rtl dump
pr43920-2.c.244r.jump2.patch_can_replace_by is the jump2 rtl dump
after patch can_replace_by.patch
Could you help me to review the patch?
Thanks again.
Shiva
2015-04-18 0:03 GMT+08:00 Jeff Law <law@redhat.com>:
> On 04/17/2015 03:57 AM, Shiva Chen wrote:
>>
>> Hi,
>>
>> I think the rtl dump in
>> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64916
>> is not jump2 phase rtl dump.
>>
>> Because jump2 is after ira, the register number should be hardware
>> register number.
>>
>> the jump2 rtl dump should as follow
>>
>> ...
>> 31: NOTE_INSN_BASIC_BLOCK 5
>> 32: [r6:SI]=r4:SI
>> REG_DEAD r6:SI
>> REG_DEAD r4:SI
>> 33: [r5:SI]=r0:SI
>> REG_DEAD r5:SI
>> REG_DEAD r0:SI
>> 7: r0:SI=0
>> REG_EQUAL 0
>> 85: use r0:SI
>> 86:
>> {return;sp:SI=sp:SI+0x18;r3:SI=[sp:SI];r4:SI=[sp:SI+0x4];r5:SI=[sp:SI+0x8];r6:SI=[sp:SI+0xc];r7:SI=[sp:SI+0x10];pc:SI=[sp:SI+0x14];}
>> REG_UNUSED pc:SI
>> REG_UNUSED r3:SI
>> REG_CFA_RESTORE r7:SI
>> REG_CFA_RESTORE r6:SI
>> REG_CFA_RESTORE r5:SI
>> REG_CFA_RESTORE r4:SI
>> REG_CFA_RESTORE r3:SI
>> 77: barrier
>> 46: L46:
>> 45: NOTE_INSN_BASIC_BLOCK 6
>> 8: r0:SI=r4:SI
>> REG_DEAD r4:SI
>> REG_EQUAL 0xffffffffffffffff
>> 87: use r0:SI
>> 88:
>> {return;sp:SI=sp:SI+0x18;r3:SI=[sp:SI];r4:SI=[sp:SI+0x4];r5:SI=[sp:SI+0x8];r6:SI=[sp:SI+0xc];r7:SI=[sp:SI+0x10];pc:SI=[sp:SI+0x14];}
>> REG_UNUSED pc:SI
>> REG_UNUSED r3:SI
>> REG_CFA_RESTORE r7:SI
>> REG_CFA_RESTORE r6:SI
>> REG_CFA_RESTORE r5:SI
>> REG_CFA_RESTORE r4:SI
>> REG_CFA_RESTORE r3:SI
>> 79: barrier
>> 54: L54:
>> 53: NOTE_INSN_BASIC_BLOCK 7
>> 9: r0:SI=0xffffffffffffffff <== lost REG_EQUAL after patch
>> 34: L34:
>> 35: NOTE_INSN_BASIC_BLOCK 8
>> 41: use r0:SI
>> 90:
>> {return;sp:SI=sp:SI+0x18;r3:SI=[sp:SI];r4:SI=[sp:SI+0x4];r5:SI=[sp:SI+0x8];r6:SI=[sp:SI+0xc];r7:SI=[sp:SI+0x10];pc:SI=[sp:SI+0x14];}
>> REG_UNUSED pc:SI
>> REG_UNUSED r3:SI
>> REG_CFA_RESTORE r7:SI
>> REG_CFA_RESTORE r6:SI
>> REG_CFA_RESTORE r5:SI
>> REG_CFA_RESTORE r4:SI
>> REG_CFA_RESTORE r3:SI
>> 89: barrier
>
> Intead of the slim dump, can you please include the full RTL dump. I find
> those much easier to read.
>
>
>
>>
>> Possible patch for can_replace_by in cfgcleanup.c.
>>
>> - if (!note1 || !note2 || !rtx_equal_p (XEXP (note1, 0), XEXP (note2, 0))
>> - || !CONST_INT_P (XEXP (note1, 0)))
>> +
>> + if (!note1 || !CONST_INT_P (XEXP (note1, 0)))
>> return dir_none;
>>
>> + if (note2)
>> + {
>> + if (!rtx_equal_p (XEXP (note1, 0), XEXP (note2, 0)))
>> + return dir_none;
>> + }
>> + else
>> + {
>> + if (!CONST_INT_P (SET_SRC (s2))
>> + || !rtx_equal_p (XEXP (note1, 0), SET_SRC (s2)))
>> + return dir_none;
>> + }
>> +
>>
>> I'm not sure the idea is ok or it might crash something.
>> Any suggestion would be very helpful.
>
> Seems like you're on a reasonable path to me. I suggest you stick with it.
>
> Basically what it appears you're trying to do is unify insns from different
> blocks where one looks like
>
> (set x y) with an attached REG_EQUAL note
>
> And the other looks like
>
> (set x const_int)
>
> Where the REG_EQUAL note has the same value as the const_int in the second
> set.
>
> I think you'd want to handle both cases i1 has the note i2, no note and i1
> has no note and i2 has a note.
>
> Jeff
>
> jeff
[-- Attachment #2: can_replace_by.patch --]
[-- Type: application/octet-stream, Size: 1861 bytes --]
diff --git a/gcc/cfgcleanup.c b/gcc/cfgcleanup.c
index cee152e..8e5b502 100644
--- a/gcc/cfgcleanup.c
+++ b/gcc/cfgcleanup.c
@@ -1038,6 +1038,37 @@ equal_different_set_p (rtx p1, rtx s1, rtx p2, rtx s2)
return true;
}
+
+/* Return 1 if the value of dest registers are equal. */
+static int
+dest_reg_equal_p (rtx note1, rtx note2, rtx src1, rtx src2)
+{
+ if (note1
+ && note2
+ && CONST_INT_P (XEXP (note1, 0))
+ && rtx_equal_p (XEXP (note1, 0), XEXP (note2, 0)))
+ return 1;
+
+ if (!note1
+ && !note2
+ && CONST_INT_P (src1)
+ && CONST_INT_P (src2)
+ && rtx_equal_p (src1, src2))
+ return 1;
+
+ if (note1
+ && CONST_INT_P (src2)
+ && rtx_equal_p (XEXP (note1, 0), src2))
+ return 1;
+
+ if (note2
+ && CONST_INT_P (src1)
+ && rtx_equal_p (XEXP (note2, 0), src1))
+ return 1;
+
+ return 0;
+}
+
/* Examine register notes on I1 and I2 and return:
- dir_forward if I1 can be replaced by I2, or
- dir_backward if I2 can be replaced by I1, or
@@ -1066,8 +1097,11 @@ can_replace_by (rtx_insn *i1, rtx_insn *i2)
set dest to the same value. */
note1 = find_reg_equal_equiv_note (i1);
note2 = find_reg_equal_equiv_note (i2);
- if (!note1 || !note2 || !rtx_equal_p (XEXP (note1, 0), XEXP (note2, 0))
- || !CONST_INT_P (XEXP (note1, 0)))
+
+ src1 = SET_SRC (s1);
+ src2 = SET_SRC (s2);
+
+ if (!dest_reg_equal_p (note1, note2, src1, src2))
return dir_none;
if (!equal_different_set_p (PATTERN (i1), s1, PATTERN (i2), s2))
@@ -1079,8 +1113,6 @@ can_replace_by (rtx_insn *i1, rtx_insn *i2)
(set (dest) (reg))
because we don't know if the reg is live and has the same value at the
location of replacement. */
- src1 = SET_SRC (s1);
- src2 = SET_SRC (s2);
c1 = CONST_INT_P (src1);
c2 = CONST_INT_P (src2);
if (c1 && c2)
[-- Attachment #3: pr43920-2.c.244r.jump2.ori --]
[-- Type: application/octet-stream, Size: 23006 bytes --]
;; Function getFileStartAndLength (getFileStartAndLength, funcdef_no=0, decl_uid=5119, cgraph_uid=0, symbol_order=0)
try_optimize_cfg iteration 1
getFileStartAndLength
Dataflow summary:
;; invalidated by call 0 [r0] 1 [r1] 2 [r2] 3 [r3] 12 [ip] 14 [lr] 15 [pc] 16 [s0] 17 [s1] 18 [s2] 19 [s3] 20 [s4] 21 [s5] 22 [s6] 23 [s7] 24 [s8] 25 [s9] 26 [s10] 27 [s11] 28 [s12] 29 [s13] 30 [s14] 31 [s15] 48 [d16] 49 [?16] 50 [d17] 51 [?17] 52 [d18] 53 [?18] 54 [d19] 55 [?19] 56 [d20] 57 [?20] 58 [d21] 59 [?21] 60 [d22] 61 [?22] 62 [d23] 63 [?23] 64 [d24] 65 [?24] 66 [d25] 67 [?25] 68 [d26] 69 [?26] 70 [d27] 71 [?27] 72 [d28] 73 [?28] 74 [d29] 75 [?29] 76 [d30] 77 [?30] 78 [d31] 79 [?31] 80 [wr0] 81 [wr1] 82 [wr2] 83 [wr3] 84 [wr4] 85 [wr5] 86 [wr6] 87 [wr7] 88 [wr8] 89 [wr9] 90 [wr10] 91 [wr11] 92 [wr12] 93 [wr13] 94 [wr14] 95 [wr15] 96 [wcgr0] 97 [wcgr1] 98 [wcgr2] 99 [wcgr3] 100 [cc] 101 [vfpcc]
;; hardware regs used 13 [sp]
;; regular block artificial uses 13 [sp]
;; eh block artificial uses 13 [sp] 103 [afp]
;; entry block defs 0 [r0] 1 [r1] 2 [r2] 3 [r3] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 12 [ip] 13 [sp] 14 [lr] 16 [s0] 17 [s1] 18 [s2] 19 [s3] 20 [s4] 21 [s5] 22 [s6] 23 [s7] 24 [s8] 25 [s9] 26 [s10] 27 [s11] 28 [s12] 29 [s13] 30 [s14] 31 [s15]
;; exit block uses 0 [r0] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 14 [lr]
;; regs ever live 0[r0] 1[r1] 2[r2] 3[r3] 4[r4] 5[r5] 6[r6] 7[r7] 12[ip] 13[sp] 14[lr] 15[pc] 100[cc]
;; ref usage r0={8d,12u} r1={5d,3u} r2={5d,3u} r3={6d,1u} r4={5d,7u} r5={5d,3u} r6={5d,3u} r7={5d,3u} r12={5d} r13={5d,36u} r14={3d,2u} r15={5d} r16={3d} r17={3d} r18={3d} r19={3d} r20={3d} r21={3d} r22={3d} r23={3d} r24={3d} r25={3d} r26={3d} r27={3d} r28={3d} r29={3d} r30={3d} r31={3d} r48={2d} r49={2d} r50={2d} r51={2d} r52={2d} r53={2d} r54={2d} r55={2d} r56={2d} r57={2d} r58={2d} r59={2d} r60={2d} r61={2d} r62={2d} r63={2d} r64={2d} r65={2d} r66={2d} r67={2d} r68={2d} r69={2d} r70={2d} r71={2d} r72={2d} r73={2d} r74={2d} r75={2d} r76={2d} r77={2d} r78={2d} r79={2d} r80={2d} r81={2d} r82={2d} r83={2d} r84={2d} r85={2d} r86={2d} r87={2d} r88={2d} r89={2d} r90={2d} r91={2d} r92={2d} r93={2d} r94={2d} r95={2d} r96={2d} r97={2d} r98={2d} r99={2d} r100={5d,3u} r101={2d}
;; total ref usage 297{221d,76u,0e} in 29{27 regular + 2 call} insns.
(note 1 0 10 NOTE_INSN_DELETED)
;; basic block 2, loop depth 0, count 0, freq 10000, maybe hot
;; prev block 0, next block 3, flags: (RTL)
;; pred: ENTRY [100.0%] (FALLTHRU)
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u-1(13){ }}
;; lr in 0 [r0] 1 [r1] 2 [r2] 3 [r3] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 14 [lr]
;; lr use 0 [r0] 1 [r1] 2 [r2] 3 [r3] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 14 [lr]
;; lr def 0 [r0] 1 [r1] 2 [r2] 3 [r3] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 12 [ip] 13 [sp] 14 [lr] 15 [pc] 16 [s0] 17 [s1] 18 [s2] 19 [s3] 20 [s4] 21 [s5] 22 [s6] 23 [s7] 24 [s8] 25 [s9] 26 [s10] 27 [s11] 28 [s12] 29 [s13] 30 [s14] 31 [s15] 48 [d16] 49 [?16] 50 [d17] 51 [?17] 52 [d18] 53 [?18] 54 [d19] 55 [?19] 56 [d20] 57 [?20] 58 [d21] 59 [?21] 60 [d22] 61 [?22] 62 [d23] 63 [?23] 64 [d24] 65 [?24] 66 [d25] 67 [?25] 68 [d26] 69 [?26] 70 [d27] 71 [?27] 72 [d28] 73 [?28] 74 [d29] 75 [?29] 76 [d30] 77 [?30] 78 [d31] 79 [?31] 80 [wr0] 81 [wr1] 82 [wr2] 83 [wr3] 84 [wr4] 85 [wr5] 86 [wr6] 87 [wr7] 88 [wr8] 89 [wr9] 90 [wr10] 91 [wr11] 92 [wr12] 93 [wr13] 94 [wr14] 95 [wr15] 96 [wcgr0] 97 [wcgr1] 98 [wcgr2] 99 [wcgr3] 100 [cc] 101 [vfpcc]
;; live in 0 [r0] 1 [r1] 2 [r2] 3 [r3] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 14 [lr]
;; live gen 0 [r0] 1 [r1] 2 [r2] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 100 [cc]
;; live kill 12 [ip] 14 [lr]
(note 10 1 83 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(insn/f 83 10 84 2 (parallel [
(set (mem/c:BLK (pre_modify:SI (reg/f:SI 13 sp)
(plus:SI (reg/f:SI 13 sp)
(const_int -24 [0xffffffffffffffe8]))) [2 A8])
(unspec:BLK [
(reg:SI 3 r3)
] UNSPEC_PUSH_MULT))
(use (reg:SI 4 r4))
(use (reg:SI 5 r5))
(use (reg:SI 6 r6))
(use (reg:SI 7 r7))
(use (reg:SI 14 lr))
]) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:13 -1
(expr_list:REG_DEAD (reg:SI 14 lr)
(expr_list:REG_DEAD (reg:SI 7 r7)
(expr_list:REG_DEAD (reg:SI 6 r6)
(expr_list:REG_DEAD (reg:SI 5 r5)
(expr_list:REG_DEAD (reg:SI 4 r4)
(expr_list:REG_DEAD (reg:SI 3 r3)
(expr_list:REG_FRAME_RELATED_EXPR (sequence [
(set/f (reg/f:SI 13 sp)
(plus:SI (reg/f:SI 13 sp)
(const_int -24 [0xffffffffffffffe8])))
(set/f (mem/c:SI (reg/f:SI 13 sp) [2 S4 A32])
(reg:SI 3 r3))
(set/f (mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 4 [0x4])) [2 S4 A32])
(reg:SI 4 r4))
(set/f (mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 8 [0x8])) [2 S4 A32])
(reg:SI 5 r5))
(set/f (mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 12 [0xc])) [2 S4 A32])
(reg:SI 6 r6))
(set/f (mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 16 [0x10])) [2 S4 A32])
(reg:SI 7 r7))
(set/f (mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 20 [0x14])) [2 S4 A32])
(reg:SI 14 lr))
])
(nil)))))))))
(note 84 83 2 2 NOTE_INSN_PROLOGUE_END)
(insn 2 84 3 2 (set (reg/v:SI 7 r7 [orig:116 fd ] [116])
(reg:SI 0 r0 [ fd ])) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:13 615 {*thumb2_movsi_vfp}
(nil))
(insn 3 2 4 2 (set (reg/v/f:SI 6 r6 [orig:117 start_ ] [117])
(reg:SI 1 r1 [ start_ ])) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:13 615 {*thumb2_movsi_vfp}
(expr_list:REG_DEAD (reg:SI 1 r1 [ start_ ])
(nil)))
(insn 4 3 5 2 (set (reg/v/f:SI 5 r5 [orig:118 length_ ] [118])
(reg:SI 2 r2 [ length_ ])) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:13 615 {*thumb2_movsi_vfp}
(expr_list:REG_DEAD (reg:SI 2 r2 [ length_ ])
(nil)))
(note 5 4 12 2 NOTE_INSN_FUNCTION_BEG)
(insn 12 5 13 2 (set (reg:SI 2 r2)
(const_int 1 [0x1])) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:17 615 {*thumb2_movsi_vfp}
(nil))
(insn 13 12 15 2 (set (reg:SI 1 r1)
(const_int 0 [0])) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:17 615 {*thumb2_movsi_vfp}
(nil))
(call_insn 15 13 16 2 (parallel [
(set (reg:SI 0 r0)
(call (mem:SI (symbol_ref:SI ("lseek") [flags 0x41] <function_decl 0xb7521a80 lseek>) [0 lseek S4 A32])
(const_int 0 [0])))
(use (const_int 0 [0]))
(clobber (reg:SI 14 lr))
]) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:17 211 {*call_value_symbol}
(expr_list:REG_DEAD (reg:SI 2 r2)
(expr_list:REG_DEAD (reg:SI 1 r1)
(expr_list:REG_CALL_DECL (symbol_ref:SI ("lseek") [flags 0x41] <function_decl 0xb7521a80 lseek>)
(nil))))
(expr_list (clobber (reg:SI 12 ip))
(expr_list:SI (use (reg:SI 0 r0))
(expr_list:SI (use (reg:SI 1 r1))
(expr_list:SI (use (reg:SI 2 r2))
(nil))))))
(insn 16 15 17 2 (set (reg/v:SI 4 r4 [orig:111 start ] [111])
(reg:SI 0 r0)) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:17 615 {*thumb2_movsi_vfp}
(expr_list:REG_DEAD (reg:SI 0 r0)
(nil)))
(insn 17 16 18 2 (set (reg:SI 2 r2)
(const_int 2 [0x2])) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:18 615 {*thumb2_movsi_vfp}
(nil))
(insn 18 17 19 2 (set (reg:SI 1 r1)
(const_int 0 [0])) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:18 615 {*thumb2_movsi_vfp}
(nil))
(insn 19 18 20 2 (set (reg:SI 0 r0)
(reg/v:SI 7 r7 [orig:116 fd ] [116])) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:18 615 {*thumb2_movsi_vfp}
(expr_list:REG_DEAD (reg/v:SI 7 r7 [orig:116 fd ] [116])
(nil)))
(call_insn 20 19 22 2 (parallel [
(set (reg:SI 0 r0)
(call (mem:SI (symbol_ref:SI ("lseek") [flags 0x41] <function_decl 0xb7521a80 lseek>) [0 lseek S4 A32])
(const_int 0 [0])))
(use (const_int 0 [0]))
(clobber (reg:SI 14 lr))
]) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:18 211 {*call_value_symbol}
(expr_list:REG_DEAD (reg:SI 2 r2)
(expr_list:REG_DEAD (reg:SI 1 r1)
(expr_list:REG_CALL_DECL (symbol_ref:SI ("lseek") [flags 0x41] <function_decl 0xb7521a80 lseek>)
(nil))))
(expr_list (clobber (reg:SI 12 ip))
(expr_list:SI (use (reg:SI 0 r0))
(expr_list:SI (use (reg:SI 1 r1))
(expr_list:SI (use (reg:SI 2 r2))
(nil))))))
(insn 22 20 23 2 (set (reg:CC 100 cc)
(compare:CC (reg/v:SI 4 r4 [orig:111 start ] [111])
(const_int -1 [0xffffffffffffffff]))) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:20 186 {*arm_cmpsi_insn}
(nil))
(jump_insn 23 22 24 2 (set (pc)
(if_then_else (eq (reg:CC 100 cc)
(const_int 0 [0]))
(label_ref:SI 46)
(pc))) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:20 194 {arm_cond_branch}
(expr_list:REG_DEAD (reg:CC 100 cc)
(int_list:REG_BR_PROB 159 (nil)))
-> 46)
;; succ: 6 [1.6%]
;; 3 [98.4%] (FALLTHRU)
;; lr out 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp] 14 [lr]
;; live out 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp]
;; basic block 3, loop depth 0, count 0, freq 9841, maybe hot
;; prev block 2, next block 4, flags: (RTL)
;; pred: 2 [98.4%] (FALLTHRU)
;; bb 3 artificial_defs: { }
;; bb 3 artificial_uses: { u-1(13){ }}
;; lr in 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp] 14 [lr]
;; lr use 0 [r0] 13 [sp]
;; lr def 100 [cc]
;; live in 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp]
;; live gen 100 [cc]
;; live kill
(note 24 23 25 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
(insn 25 24 26 3 (set (reg:CC 100 cc)
(compare:CC (reg/v:SI 0 r0 [orig:112 end ] [112])
(const_int -1 [0xffffffffffffffff]))) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:20 186 {*arm_cmpsi_insn}
(nil))
(jump_insn 26 25 27 3 (set (pc)
(if_then_else (eq (reg:CC 100 cc)
(const_int 0 [0]))
(label_ref:SI 34)
(pc))) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:20 194 {arm_cond_branch}
(expr_list:REG_DEAD (reg:CC 100 cc)
(int_list:REG_BR_PROB 159 (nil)))
-> 34)
;; succ: 8 [1.6%]
;; 4 [98.4%] (FALLTHRU)
;; lr out 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp] 14 [lr]
;; live out 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp]
;; basic block 4, loop depth 0, count 0, freq 9685, maybe hot
;; prev block 3, next block 5, flags: (RTL)
;; pred: 3 [98.4%] (FALLTHRU)
;; bb 4 artificial_defs: { }
;; bb 4 artificial_uses: { u-1(13){ }}
;; lr in 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp] 14 [lr]
;; lr use 0 [r0] 4 [r4] 13 [sp]
;; lr def 0 [r0] 100 [cc]
;; live in 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp]
;; live gen 0 [r0] 100 [cc]
;; live kill
(note 27 26 28 4 [bb 4] NOTE_INSN_BASIC_BLOCK)
(note 28 27 29 4 NOTE_INSN_DELETED)
(insn 29 28 30 4 (parallel [
(set (reg:CC_NOOV 100 cc)
(compare:CC_NOOV (minus:SI (reg/v:SI 0 r0 [orig:112 end ] [112])
(reg/v:SI 4 r4 [orig:111 start ] [111]))
(const_int 0 [0])))
(set (reg/v:SI 0 r0 [orig:114 length ] [114])
(minus:SI (reg/v:SI 0 r0 [orig:112 end ] [112])
(reg/v:SI 4 r4 [orig:111 start ] [111])))
]) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:24 34 {*subsi3_compare0}
(nil))
(jump_insn 30 29 31 4 (set (pc)
(if_then_else (eq (reg:CC_NOOV 100 cc)
(const_int 0 [0]))
(label_ref:SI 54)
(pc))) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:24 194 {arm_cond_branch}
(expr_list:REG_DEAD (reg:CC_NOOV 100 cc)
(int_list:REG_BR_PROB 400 (nil)))
-> 54)
;; succ: 7 [4.0%]
;; 5 [96.0%] (FALLTHRU)
;; lr out 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp] 14 [lr]
;; live out 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp]
;; basic block 5, loop depth 0, count 0, freq 9297, maybe hot
;; prev block 4, next block 6, flags: (RTL)
;; pred: 4 [96.0%] (FALLTHRU)
;; bb 5 artificial_defs: { }
;; bb 5 artificial_uses: { u-1(13){ }}
;; lr in 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp] 14 [lr]
;; lr use 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp]
;; lr def 0 [r0] 3 [r3] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 15 [pc]
;; live in 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp]
;; live gen 0 [r0] 3 [r3] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 15 [pc]
;; live kill
(note 31 30 32 5 [bb 5] NOTE_INSN_BASIC_BLOCK)
(insn 32 31 33 5 (set (mem:SI (reg/v/f:SI 6 r6 [orig:117 start_ ] [117]) [1 *start__11(D)+0 S4 A32])
(reg/v:SI 4 r4 [orig:111 start ] [111])) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:27 615 {*thumb2_movsi_vfp}
(expr_list:REG_DEAD (reg/v/f:SI 6 r6 [orig:117 start_ ] [117])
(expr_list:REG_DEAD (reg/v:SI 4 r4 [orig:111 start ] [111])
(nil))))
(insn 33 32 7 5 (set (mem:SI (reg/v/f:SI 5 r5 [orig:118 length_ ] [118]) [1 *length__13(D)+0 S4 A32])
(reg/v:SI 0 r0 [orig:114 length ] [114])) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:28 615 {*thumb2_movsi_vfp}
(expr_list:REG_DEAD (reg/v/f:SI 5 r5 [orig:118 length_ ] [118])
(expr_list:REG_DEAD (reg/v:SI 0 r0 [orig:114 length ] [114])
(nil))))
(insn 7 33 85 5 (set (reg:SI 0 r0 [orig:110 D.5141 ] [110])
(const_int 0 [0])) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:30 615 {*thumb2_movsi_vfp}
(expr_list:REG_EQUAL (const_int 0 [0])
(nil)))
(insn 85 7 86 5 (use (reg/i:SI 0 r0)) -1
(nil))
(jump_insn 86 85 77 5 (parallel [
(return)
(set/f (reg/f:SI 13 sp)
(plus:SI (reg/f:SI 13 sp)
(const_int 24 [0x18])))
(set/f (reg:SI 3 r3)
(mem/c:SI (reg/f:SI 13 sp) [2 S4 A32]))
(set/f (reg:SI 4 r4)
(mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 4 [0x4])) [2 S4 A32]))
(set/f (reg:SI 5 r5)
(mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 8 [0x8])) [2 S4 A32]))
(set/f (reg:SI 6 r6)
(mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 12 [0xc])) [2 S4 A32]))
(set/f (reg:SI 7 r7)
(mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 16 [0x10])) [2 S4 A32]))
(set/f (reg:SI 15 pc)
(mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 20 [0x14])) [2 S4 A32]))
]) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:30 -1
(expr_list:REG_UNUSED (reg:SI 15 pc)
(expr_list:REG_UNUSED (reg:SI 3 r3)
(expr_list:REG_CFA_RESTORE (reg:SI 7 r7)
(expr_list:REG_CFA_RESTORE (reg:SI 6 r6)
(expr_list:REG_CFA_RESTORE (reg:SI 5 r5)
(expr_list:REG_CFA_RESTORE (reg:SI 4 r4)
(expr_list:REG_CFA_RESTORE (reg:SI 3 r3)
(nil))))))))
-> return)
;; succ: EXIT [100.0%]
;; lr out 0 [r0] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 14 [lr]
;; live out 0 [r0] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp]
(barrier 77 86 46)
;; basic block 6, loop depth 0, count 0, freq 159, maybe hot
;; prev block 5, next block 7, flags: (RTL)
;; pred: 2 [1.6%]
;; bb 6 artificial_defs: { }
;; bb 6 artificial_uses: { u-1(13){ }}
;; lr in 4 [r4] 13 [sp] 14 [lr]
;; lr use 4 [r4] 13 [sp]
;; lr def 0 [r0] 3 [r3] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 15 [pc]
;; live in 4 [r4] 13 [sp]
;; live gen 0 [r0] 3 [r3] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 15 [pc]
;; live kill
(code_label 46 77 45 6 3 "" [1 uses])
(note 45 46 8 6 [bb 6] NOTE_INSN_BASIC_BLOCK)
(insn 8 45 87 6 (set (reg:SI 0 r0 [orig:110 D.5141 ] [110])
(reg/v:SI 4 r4 [orig:111 start ] [111])) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:21 615 {*thumb2_movsi_vfp}
(expr_list:REG_DEAD (reg/v:SI 4 r4 [orig:111 start ] [111])
(expr_list:REG_EQUAL (const_int -1 [0xffffffffffffffff])
(nil))))
(insn 87 8 88 6 (use (reg/i:SI 0 r0)) -1
(nil))
(jump_insn 88 87 79 6 (parallel [
(return)
(set/f (reg/f:SI 13 sp)
(plus:SI (reg/f:SI 13 sp)
(const_int 24 [0x18])))
(set/f (reg:SI 3 r3)
(mem/c:SI (reg/f:SI 13 sp) [2 S4 A32]))
(set/f (reg:SI 4 r4)
(mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 4 [0x4])) [2 S4 A32]))
(set/f (reg:SI 5 r5)
(mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 8 [0x8])) [2 S4 A32]))
(set/f (reg:SI 6 r6)
(mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 12 [0xc])) [2 S4 A32]))
(set/f (reg:SI 7 r7)
(mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 16 [0x10])) [2 S4 A32]))
(set/f (reg:SI 15 pc)
(mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 20 [0x14])) [2 S4 A32]))
]) -1
(expr_list:REG_UNUSED (reg:SI 15 pc)
(expr_list:REG_UNUSED (reg:SI 3 r3)
(expr_list:REG_CFA_RESTORE (reg:SI 7 r7)
(expr_list:REG_CFA_RESTORE (reg:SI 6 r6)
(expr_list:REG_CFA_RESTORE (reg:SI 5 r5)
(expr_list:REG_CFA_RESTORE (reg:SI 4 r4)
(expr_list:REG_CFA_RESTORE (reg:SI 3 r3)
(nil))))))))
-> return)
;; succ: EXIT [100.0%]
;; lr out 0 [r0] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 14 [lr]
;; live out 0 [r0] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp]
(barrier 79 88 54)
;; basic block 7, loop depth 0, count 0, freq 387, maybe hot
;; prev block 6, next block 8, flags: (RTL)
;; pred: 4 [4.0%]
;; bb 7 artificial_defs: { }
;; bb 7 artificial_uses: { u-1(13){ }}
;; lr in 13 [sp] 14 [lr]
;; lr use 13 [sp]
;; lr def 0 [r0]
;; live in 13 [sp]
;; live gen 0 [r0]
;; live kill
(code_label 54 79 53 7 5 "" [1 uses])
(note 53 54 9 7 [bb 7] NOTE_INSN_BASIC_BLOCK)
(insn 9 53 34 7 (set (reg:SI 0 r0 [orig:110 D.5141 ] [110])
(const_int -1 [0xffffffffffffffff])) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:21 615 {*thumb2_movsi_vfp}
(nil))
;; succ: 8 [100.0%] (FALLTHRU)
;; lr out 0 [r0] 13 [sp] 14 [lr]
;; live out 0 [r0] 13 [sp]
;; basic block 8, loop depth 0, count 0, freq 10000, maybe hot
;; Invalid sum of incoming frequencies 543, should be 10000
;; prev block 7, next block 1, flags: (RTL)
;; pred: 3 [1.6%]
;; 7 [100.0%] (FALLTHRU)
;; bb 8 artificial_defs: { }
;; bb 8 artificial_uses: { u-1(13){ }}
;; lr in 0 [r0] 13 [sp] 14 [lr]
;; lr use 0 [r0] 13 [sp]
;; lr def 3 [r3] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 15 [pc]
;; live in 0 [r0] 13 [sp]
;; live gen 3 [r3] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 15 [pc]
;; live kill
(code_label 34 9 35 8 2 "" [1 uses])
(note 35 34 41 8 [bb 8] NOTE_INSN_BASIC_BLOCK)
(insn 41 35 90 8 (use (reg/i:SI 0 r0)) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:31 -1
(nil))
(jump_insn 90 41 89 8 (parallel [
(return)
(set/f (reg/f:SI 13 sp)
(plus:SI (reg/f:SI 13 sp)
(const_int 24 [0x18])))
(set/f (reg:SI 3 r3)
(mem/c:SI (reg/f:SI 13 sp) [2 S4 A32]))
(set/f (reg:SI 4 r4)
(mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 4 [0x4])) [2 S4 A32]))
(set/f (reg:SI 5 r5)
(mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 8 [0x8])) [2 S4 A32]))
(set/f (reg:SI 6 r6)
(mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 12 [0xc])) [2 S4 A32]))
(set/f (reg:SI 7 r7)
(mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 16 [0x10])) [2 S4 A32]))
(set/f (reg:SI 15 pc)
(mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 20 [0x14])) [2 S4 A32]))
]) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:31 -1
(expr_list:REG_UNUSED (reg:SI 15 pc)
(expr_list:REG_UNUSED (reg:SI 3 r3)
(expr_list:REG_CFA_RESTORE (reg:SI 7 r7)
(expr_list:REG_CFA_RESTORE (reg:SI 6 r6)
(expr_list:REG_CFA_RESTORE (reg:SI 5 r5)
(expr_list:REG_CFA_RESTORE (reg:SI 4 r4)
(expr_list:REG_CFA_RESTORE (reg:SI 3 r3)
(nil))))))))
-> return)
;; succ: EXIT [100.0%]
;; lr out 0 [r0] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 14 [lr]
;; live out 0 [r0] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp]
(barrier 89 90 82)
(note 82 89 0 NOTE_INSN_DELETED)
[-- Attachment #4: pr43920-2.c.244r.jump2.patch_can_replace_by --]
[-- Type: application/octet-stream, Size: 29539 bytes --]
;; Function getFileStartAndLength (getFileStartAndLength, funcdef_no=0, decl_uid=5119, cgraph_uid=0, symbol_order=0)
try_optimize_cfg iteration 1
Cross jumping from bb 6 to bb 7; 1 common insns
changing bb of uid 91
unscanned insn
changing bb of uid 8
from 6 to 9
changing bb of uid 87
from 6 to 9
changing bb of uid 88
from 6 to 9
scanning new insn with uid = 92.
deleting insn with uid = 88.
deleting insn with uid = 87.
deleting insn with uid = 8.
deleting block 9
try_optimize_cfg iteration 2
verify found no changes in insn with uid = 23.
Edge 2->6 redirected to 7
deleting insn with uid = 92.
deleting block 6
starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called
df_worklist_dataflow_doublequeue:n_basic_blocks 8 n_edges 10 count 8 ( 1)
df_worklist_dataflow_doublequeue:n_basic_blocks 8 n_edges 10 count 8 ( 1)
try_optimize_cfg iteration 3
starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called
getFileStartAndLength
Dataflow summary:
;; invalidated by call 0 [r0] 1 [r1] 2 [r2] 3 [r3] 12 [ip] 14 [lr] 15 [pc] 16 [s0] 17 [s1] 18 [s2] 19 [s3] 20 [s4] 21 [s5] 22 [s6] 23 [s7] 24 [s8] 25 [s9] 26 [s10] 27 [s11] 28 [s12] 29 [s13] 30 [s14] 31 [s15] 48 [d16] 49 [?16] 50 [d17] 51 [?17] 52 [d18] 53 [?18] 54 [d19] 55 [?19] 56 [d20] 57 [?20] 58 [d21] 59 [?21] 60 [d22] 61 [?22] 62 [d23] 63 [?23] 64 [d24] 65 [?24] 66 [d25] 67 [?25] 68 [d26] 69 [?26] 70 [d27] 71 [?27] 72 [d28] 73 [?28] 74 [d29] 75 [?29] 76 [d30] 77 [?30] 78 [d31] 79 [?31] 80 [wr0] 81 [wr1] 82 [wr2] 83 [wr3] 84 [wr4] 85 [wr5] 86 [wr6] 87 [wr7] 88 [wr8] 89 [wr9] 90 [wr10] 91 [wr11] 92 [wr12] 93 [wr13] 94 [wr14] 95 [wr15] 96 [wcgr0] 97 [wcgr1] 98 [wcgr2] 99 [wcgr3] 100 [cc] 101 [vfpcc]
;; hardware regs used 13 [sp]
;; regular block artificial uses 13 [sp]
;; eh block artificial uses 13 [sp] 103 [afp]
;; entry block defs 0 [r0] 1 [r1] 2 [r2] 3 [r3] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 12 [ip] 13 [sp] 14 [lr] 16 [s0] 17 [s1] 18 [s2] 19 [s3] 20 [s4] 21 [s5] 22 [s6] 23 [s7] 24 [s8] 25 [s9] 26 [s10] 27 [s11] 28 [s12] 29 [s13] 30 [s14] 31 [s15]
;; exit block uses 0 [r0] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 14 [lr]
;; regs ever live 0[r0] 1[r1] 2[r2] 3[r3] 4[r4] 5[r5] 6[r6] 7[r7] 12[ip] 13[sp] 14[lr] 15[pc] 100[cc]
;; ref usage r0={7d,11u} r1={5d,3u} r2={5d,3u} r3={5d,1u} r4={4d,6u} r5={4d,3u} r6={4d,3u} r7={4d,3u} r12={5d} r13={4d,27u} r14={3d,2u} r15={4d} r16={3d} r17={3d} r18={3d} r19={3d} r20={3d} r21={3d} r22={3d} r23={3d} r24={3d} r25={3d} r26={3d} r27={3d} r28={3d} r29={3d} r30={3d} r31={3d} r48={2d} r49={2d} r50={2d} r51={2d} r52={2d} r53={2d} r54={2d} r55={2d} r56={2d} r57={2d} r58={2d} r59={2d} r60={2d} r61={2d} r62={2d} r63={2d} r64={2d} r65={2d} r66={2d} r67={2d} r68={2d} r69={2d} r70={2d} r71={2d} r72={2d} r73={2d} r74={2d} r75={2d} r76={2d} r77={2d} r78={2d} r79={2d} r80={2d} r81={2d} r82={2d} r83={2d} r84={2d} r85={2d} r86={2d} r87={2d} r88={2d} r89={2d} r90={2d} r91={2d} r92={2d} r93={2d} r94={2d} r95={2d} r96={2d} r97={2d} r98={2d} r99={2d} r100={5d,3u} r101={2d}
;; total ref usage 278{213d,65u,0e} in 26{24 regular + 2 call} insns.
( )->[0]->( 2 )
;; bb 0 artificial_defs: { d-1(0){ }d-1(1){ }d-1(2){ }d-1(3){ }d-1(4){ }d-1(5){ }d-1(6){ }d-1(7){ }d-1(12){ }d-1(13){ }d-1(14){ }d-1(16){ }d-1(17){ }d-1(18){ }d-1(19){ }d-1(20){ }d-1(21){ }d-1(22){ }d-1(23){ }d-1(24){ }d-1(25){ }d-1(26){ }d-1(27){ }d-1(28){ }d-1(29){ }d-1(30){ }d-1(31){ }}
;; bb 0 artificial_uses: { }
;; lr in
;; lr use
;; lr def 0 [r0] 1 [r1] 2 [r2] 3 [r3] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 12 [ip] 13 [sp] 14 [lr] 16 [s0] 17 [s1] 18 [s2] 19 [s3] 20 [s4] 21 [s5] 22 [s6] 23 [s7] 24 [s8] 25 [s9] 26 [s10] 27 [s11] 28 [s12] 29 [s13] 30 [s14] 31 [s15]
;; live in
;; live gen 0 [r0] 1 [r1] 2 [r2] 3 [r3] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 12 [ip] 13 [sp] 14 [lr] 16 [s0] 17 [s1] 18 [s2] 19 [s3] 20 [s4] 21 [s5] 22 [s6] 23 [s7] 24 [s8] 25 [s9] 26 [s10] 27 [s11] 28 [s12] 29 [s13] 30 [s14] 31 [s15]
;; live kill
;; lr out 0 [r0] 1 [r1] 2 [r2] 3 [r3] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 14 [lr]
;; live out 0 [r0] 1 [r1] 2 [r2] 3 [r3] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 14 [lr]
( 0 )->[2]->( 7 3 )
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u-1(13){ }}
;; lr in 0 [r0] 1 [r1] 2 [r2] 3 [r3] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 14 [lr]
;; lr use 0 [r0] 1 [r1] 2 [r2] 3 [r3] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 14 [lr]
;; lr def 0 [r0] 1 [r1] 2 [r2] 3 [r3] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 12 [ip] 13 [sp] 14 [lr] 15 [pc] 16 [s0] 17 [s1] 18 [s2] 19 [s3] 20 [s4] 21 [s5] 22 [s6] 23 [s7] 24 [s8] 25 [s9] 26 [s10] 27 [s11] 28 [s12] 29 [s13] 30 [s14] 31 [s15] 48 [d16] 49 [?16] 50 [d17] 51 [?17] 52 [d18] 53 [?18] 54 [d19] 55 [?19] 56 [d20] 57 [?20] 58 [d21] 59 [?21] 60 [d22] 61 [?22] 62 [d23] 63 [?23] 64 [d24] 65 [?24] 66 [d25] 67 [?25] 68 [d26] 69 [?26] 70 [d27] 71 [?27] 72 [d28] 73 [?28] 74 [d29] 75 [?29] 76 [d30] 77 [?30] 78 [d31] 79 [?31] 80 [wr0] 81 [wr1] 82 [wr2] 83 [wr3] 84 [wr4] 85 [wr5] 86 [wr6] 87 [wr7] 88 [wr8] 89 [wr9] 90 [wr10] 91 [wr11] 92 [wr12] 93 [wr13] 94 [wr14] 95 [wr15] 96 [wcgr0] 97 [wcgr1] 98 [wcgr2] 99 [wcgr3] 100 [cc] 101 [vfpcc]
;; live in 0 [r0] 1 [r1] 2 [r2] 3 [r3] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 14 [lr]
;; live gen 0 [r0] 1 [r1] 2 [r2] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 100 [cc]
;; live kill 12 [ip] 14 [lr]
;; lr out 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp] 14 [lr]
;; live out 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp]
( 2 )->[3]->( 8 4 )
;; bb 3 artificial_defs: { }
;; bb 3 artificial_uses: { u-1(13){ }}
;; lr in 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp] 14 [lr]
;; lr use 0 [r0] 13 [sp]
;; lr def 100 [cc]
;; live in 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp]
;; live gen 100 [cc]
;; live kill
;; lr out 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp] 14 [lr]
;; live out 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp]
( 3 )->[4]->( 7 5 )
;; bb 4 artificial_defs: { }
;; bb 4 artificial_uses: { u-1(13){ }}
;; lr in 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp] 14 [lr]
;; lr use 0 [r0] 4 [r4] 13 [sp]
;; lr def 0 [r0] 100 [cc]
;; live in 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp]
;; live gen 0 [r0] 100 [cc]
;; live kill
;; lr out 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp] 14 [lr]
;; live out 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp]
( 4 )->[5]->( 1 )
;; bb 5 artificial_defs: { }
;; bb 5 artificial_uses: { u-1(13){ }}
;; lr in 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp] 14 [lr]
;; lr use 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp]
;; lr def 0 [r0] 3 [r3] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 15 [pc]
;; live in 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp]
;; live gen 0 [r0] 3 [r3] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 15 [pc]
;; live kill
;; lr out 0 [r0] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 14 [lr]
;; live out 0 [r0] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp]
( 4 2 )->[7]->( 8 )
;; bb 7 artificial_defs: { }
;; bb 7 artificial_uses: { u-1(13){ }}
;; lr in 13 [sp] 14 [lr]
;; lr use 13 [sp]
;; lr def 0 [r0]
;; live in 13 [sp]
;; live gen 0 [r0]
;; live kill
;; lr out 0 [r0] 13 [sp] 14 [lr]
;; live out 0 [r0] 13 [sp]
( 3 7 )->[8]->( 1 )
;; bb 8 artificial_defs: { }
;; bb 8 artificial_uses: { u-1(13){ }}
;; lr in 0 [r0] 13 [sp] 14 [lr]
;; lr use 0 [r0] 13 [sp]
;; lr def 3 [r3] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 15 [pc]
;; live in 0 [r0] 13 [sp]
;; live gen 3 [r3] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 15 [pc]
;; live kill
;; lr out 0 [r0] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 14 [lr]
;; live out 0 [r0] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp]
( 8 5 )->[1]->( )
;; bb 1 artificial_defs: { }
;; bb 1 artificial_uses: { u-1(0){ }u-1(4){ }u-1(5){ }u-1(6){ }u-1(7){ }u-1(13){ }u-1(14){ }}
;; lr in 0 [r0] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 14 [lr]
;; lr use 0 [r0] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 14 [lr]
;; lr def
;; live in 0 [r0] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp]
;; live gen
;; live kill
;; lr out
;; live out
Finding needed instructions:
Adding insn 23 to worklist
Adding insn 20 to worklist
Adding insn 15 to worklist
Adding insn 83 to worklist
Adding insn 26 to worklist
Adding insn 30 to worklist
Adding insn 86 to worklist
Adding insn 85 to worklist
Adding insn 33 to worklist
Adding insn 32 to worklist
Adding insn 90 to worklist
Adding insn 41 to worklist
Finished finding needed instructions:
processing block 8 lr out = 0 [r0] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 14 [lr]
processing block 7 lr out = 0 [r0] 13 [sp] 14 [lr]
Adding insn 9 to worklist
processing block 5 lr out = 0 [r0] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 14 [lr]
Adding insn 7 to worklist
processing block 4 lr out = 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp] 14 [lr]
Adding insn 29 to worklist
processing block 3 lr out = 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp] 14 [lr]
Adding insn 25 to worklist
processing block 2 lr out = 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp] 14 [lr]
Adding insn 22 to worklist
Adding insn 19 to worklist
Adding insn 18 to worklist
Adding insn 17 to worklist
Adding insn 16 to worklist
Adding insn 13 to worklist
Adding insn 12 to worklist
Adding insn 4 to worklist
Adding insn 3 to worklist
Adding insn 2 to worklist
try_optimize_cfg iteration 1
getFileStartAndLength
Dataflow summary:
;; invalidated by call 0 [r0] 1 [r1] 2 [r2] 3 [r3] 12 [ip] 14 [lr] 15 [pc] 16 [s0] 17 [s1] 18 [s2] 19 [s3] 20 [s4] 21 [s5] 22 [s6] 23 [s7] 24 [s8] 25 [s9] 26 [s10] 27 [s11] 28 [s12] 29 [s13] 30 [s14] 31 [s15] 48 [d16] 49 [?16] 50 [d17] 51 [?17] 52 [d18] 53 [?18] 54 [d19] 55 [?19] 56 [d20] 57 [?20] 58 [d21] 59 [?21] 60 [d22] 61 [?22] 62 [d23] 63 [?23] 64 [d24] 65 [?24] 66 [d25] 67 [?25] 68 [d26] 69 [?26] 70 [d27] 71 [?27] 72 [d28] 73 [?28] 74 [d29] 75 [?29] 76 [d30] 77 [?30] 78 [d31] 79 [?31] 80 [wr0] 81 [wr1] 82 [wr2] 83 [wr3] 84 [wr4] 85 [wr5] 86 [wr6] 87 [wr7] 88 [wr8] 89 [wr9] 90 [wr10] 91 [wr11] 92 [wr12] 93 [wr13] 94 [wr14] 95 [wr15] 96 [wcgr0] 97 [wcgr1] 98 [wcgr2] 99 [wcgr3] 100 [cc] 101 [vfpcc]
;; hardware regs used 13 [sp]
;; regular block artificial uses 13 [sp]
;; eh block artificial uses 13 [sp] 103 [afp]
;; entry block defs 0 [r0] 1 [r1] 2 [r2] 3 [r3] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 12 [ip] 13 [sp] 14 [lr] 16 [s0] 17 [s1] 18 [s2] 19 [s3] 20 [s4] 21 [s5] 22 [s6] 23 [s7] 24 [s8] 25 [s9] 26 [s10] 27 [s11] 28 [s12] 29 [s13] 30 [s14] 31 [s15]
;; exit block uses 0 [r0] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 14 [lr]
;; regs ever live 0[r0] 1[r1] 2[r2] 3[r3] 4[r4] 5[r5] 6[r6] 7[r7] 12[ip] 13[sp] 14[lr] 15[pc] 100[cc]
;; ref usage r0={7d,11u} r1={5d,3u} r2={5d,3u} r3={5d,1u} r4={4d,6u} r5={4d,3u} r6={4d,3u} r7={4d,3u} r12={5d} r13={4d,27u} r14={3d,2u} r15={4d} r16={3d} r17={3d} r18={3d} r19={3d} r20={3d} r21={3d} r22={3d} r23={3d} r24={3d} r25={3d} r26={3d} r27={3d} r28={3d} r29={3d} r30={3d} r31={3d} r48={2d} r49={2d} r50={2d} r51={2d} r52={2d} r53={2d} r54={2d} r55={2d} r56={2d} r57={2d} r58={2d} r59={2d} r60={2d} r61={2d} r62={2d} r63={2d} r64={2d} r65={2d} r66={2d} r67={2d} r68={2d} r69={2d} r70={2d} r71={2d} r72={2d} r73={2d} r74={2d} r75={2d} r76={2d} r77={2d} r78={2d} r79={2d} r80={2d} r81={2d} r82={2d} r83={2d} r84={2d} r85={2d} r86={2d} r87={2d} r88={2d} r89={2d} r90={2d} r91={2d} r92={2d} r93={2d} r94={2d} r95={2d} r96={2d} r97={2d} r98={2d} r99={2d} r100={5d,3u} r101={2d}
;; total ref usage 278{213d,65u,0e} in 26{24 regular + 2 call} insns.
(note 1 0 10 NOTE_INSN_DELETED)
;; basic block 2, loop depth 0, count 0, freq 10000, maybe hot
;; prev block 0, next block 3, flags: (RTL)
;; pred: ENTRY [100.0%] (FALLTHRU)
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u-1(13){ }}
;; lr in 0 [r0] 1 [r1] 2 [r2] 3 [r3] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 14 [lr]
;; lr use 0 [r0] 1 [r1] 2 [r2] 3 [r3] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 14 [lr]
;; lr def 0 [r0] 1 [r1] 2 [r2] 3 [r3] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 12 [ip] 13 [sp] 14 [lr] 15 [pc] 16 [s0] 17 [s1] 18 [s2] 19 [s3] 20 [s4] 21 [s5] 22 [s6] 23 [s7] 24 [s8] 25 [s9] 26 [s10] 27 [s11] 28 [s12] 29 [s13] 30 [s14] 31 [s15] 48 [d16] 49 [?16] 50 [d17] 51 [?17] 52 [d18] 53 [?18] 54 [d19] 55 [?19] 56 [d20] 57 [?20] 58 [d21] 59 [?21] 60 [d22] 61 [?22] 62 [d23] 63 [?23] 64 [d24] 65 [?24] 66 [d25] 67 [?25] 68 [d26] 69 [?26] 70 [d27] 71 [?27] 72 [d28] 73 [?28] 74 [d29] 75 [?29] 76 [d30] 77 [?30] 78 [d31] 79 [?31] 80 [wr0] 81 [wr1] 82 [wr2] 83 [wr3] 84 [wr4] 85 [wr5] 86 [wr6] 87 [wr7] 88 [wr8] 89 [wr9] 90 [wr10] 91 [wr11] 92 [wr12] 93 [wr13] 94 [wr14] 95 [wr15] 96 [wcgr0] 97 [wcgr1] 98 [wcgr2] 99 [wcgr3] 100 [cc] 101 [vfpcc]
;; live in 0 [r0] 1 [r1] 2 [r2] 3 [r3] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 14 [lr]
;; live gen 0 [r0] 1 [r1] 2 [r2] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 100 [cc]
;; live kill 12 [ip] 14 [lr]
(note 10 1 83 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(insn/f 83 10 84 2 (parallel [
(set (mem/c:BLK (pre_modify:SI (reg/f:SI 13 sp)
(plus:SI (reg/f:SI 13 sp)
(const_int -24 [0xffffffffffffffe8]))) [2 A8])
(unspec:BLK [
(reg:SI 3 r3)
] UNSPEC_PUSH_MULT))
(use (reg:SI 4 r4))
(use (reg:SI 5 r5))
(use (reg:SI 6 r6))
(use (reg:SI 7 r7))
(use (reg:SI 14 lr))
]) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:13 -1
(expr_list:REG_DEAD (reg:SI 14 lr)
(expr_list:REG_DEAD (reg:SI 7 r7)
(expr_list:REG_DEAD (reg:SI 6 r6)
(expr_list:REG_DEAD (reg:SI 5 r5)
(expr_list:REG_DEAD (reg:SI 4 r4)
(expr_list:REG_DEAD (reg:SI 3 r3)
(expr_list:REG_FRAME_RELATED_EXPR (sequence [
(set/f (reg/f:SI 13 sp)
(plus:SI (reg/f:SI 13 sp)
(const_int -24 [0xffffffffffffffe8])))
(set/f (mem/c:SI (reg/f:SI 13 sp) [2 S4 A32])
(reg:SI 3 r3))
(set/f (mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 4 [0x4])) [2 S4 A32])
(reg:SI 4 r4))
(set/f (mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 8 [0x8])) [2 S4 A32])
(reg:SI 5 r5))
(set/f (mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 12 [0xc])) [2 S4 A32])
(reg:SI 6 r6))
(set/f (mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 16 [0x10])) [2 S4 A32])
(reg:SI 7 r7))
(set/f (mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 20 [0x14])) [2 S4 A32])
(reg:SI 14 lr))
])
(nil)))))))))
(note 84 83 2 2 NOTE_INSN_PROLOGUE_END)
(insn 2 84 3 2 (set (reg/v:SI 7 r7 [orig:116 fd ] [116])
(reg:SI 0 r0 [ fd ])) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:13 615 {*thumb2_movsi_vfp}
(nil))
(insn 3 2 4 2 (set (reg/v/f:SI 6 r6 [orig:117 start_ ] [117])
(reg:SI 1 r1 [ start_ ])) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:13 615 {*thumb2_movsi_vfp}
(expr_list:REG_DEAD (reg:SI 1 r1 [ start_ ])
(nil)))
(insn 4 3 5 2 (set (reg/v/f:SI 5 r5 [orig:118 length_ ] [118])
(reg:SI 2 r2 [ length_ ])) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:13 615 {*thumb2_movsi_vfp}
(expr_list:REG_DEAD (reg:SI 2 r2 [ length_ ])
(nil)))
(note 5 4 12 2 NOTE_INSN_FUNCTION_BEG)
(insn 12 5 13 2 (set (reg:SI 2 r2)
(const_int 1 [0x1])) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:17 615 {*thumb2_movsi_vfp}
(nil))
(insn 13 12 15 2 (set (reg:SI 1 r1)
(const_int 0 [0])) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:17 615 {*thumb2_movsi_vfp}
(nil))
(call_insn 15 13 16 2 (parallel [
(set (reg:SI 0 r0)
(call (mem:SI (symbol_ref:SI ("lseek") [flags 0x41] <function_decl 0xb756aa80 lseek>) [0 lseek S4 A32])
(const_int 0 [0])))
(use (const_int 0 [0]))
(clobber (reg:SI 14 lr))
]) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:17 211 {*call_value_symbol}
(expr_list:REG_DEAD (reg:SI 2 r2)
(expr_list:REG_DEAD (reg:SI 1 r1)
(expr_list:REG_CALL_DECL (symbol_ref:SI ("lseek") [flags 0x41] <function_decl 0xb756aa80 lseek>)
(nil))))
(expr_list (clobber (reg:SI 12 ip))
(expr_list:SI (use (reg:SI 0 r0))
(expr_list:SI (use (reg:SI 1 r1))
(expr_list:SI (use (reg:SI 2 r2))
(nil))))))
(insn 16 15 17 2 (set (reg/v:SI 4 r4 [orig:111 start ] [111])
(reg:SI 0 r0)) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:17 615 {*thumb2_movsi_vfp}
(expr_list:REG_DEAD (reg:SI 0 r0)
(nil)))
(insn 17 16 18 2 (set (reg:SI 2 r2)
(const_int 2 [0x2])) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:18 615 {*thumb2_movsi_vfp}
(nil))
(insn 18 17 19 2 (set (reg:SI 1 r1)
(const_int 0 [0])) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:18 615 {*thumb2_movsi_vfp}
(nil))
(insn 19 18 20 2 (set (reg:SI 0 r0)
(reg/v:SI 7 r7 [orig:116 fd ] [116])) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:18 615 {*thumb2_movsi_vfp}
(expr_list:REG_DEAD (reg/v:SI 7 r7 [orig:116 fd ] [116])
(nil)))
(call_insn 20 19 22 2 (parallel [
(set (reg:SI 0 r0)
(call (mem:SI (symbol_ref:SI ("lseek") [flags 0x41] <function_decl 0xb756aa80 lseek>) [0 lseek S4 A32])
(const_int 0 [0])))
(use (const_int 0 [0]))
(clobber (reg:SI 14 lr))
]) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:18 211 {*call_value_symbol}
(expr_list:REG_DEAD (reg:SI 2 r2)
(expr_list:REG_DEAD (reg:SI 1 r1)
(expr_list:REG_CALL_DECL (symbol_ref:SI ("lseek") [flags 0x41] <function_decl 0xb756aa80 lseek>)
(nil))))
(expr_list (clobber (reg:SI 12 ip))
(expr_list:SI (use (reg:SI 0 r0))
(expr_list:SI (use (reg:SI 1 r1))
(expr_list:SI (use (reg:SI 2 r2))
(nil))))))
(insn 22 20 23 2 (set (reg:CC 100 cc)
(compare:CC (reg/v:SI 4 r4 [orig:111 start ] [111])
(const_int -1 [0xffffffffffffffff]))) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:20 186 {*arm_cmpsi_insn}
(nil))
(jump_insn 23 22 24 2 (set (pc)
(if_then_else (eq (reg:CC 100 cc)
(const_int 0 [0]))
(label_ref:SI 54)
(pc))) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:20 194 {arm_cond_branch}
(expr_list:REG_DEAD (reg:CC 100 cc)
(int_list:REG_BR_PROB 159 (nil)))
-> 54)
;; succ: 7 [1.6%]
;; 3 [98.4%] (FALLTHRU)
;; lr out 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp] 14 [lr]
;; live out 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp]
;; basic block 3, loop depth 0, count 0, freq 9841, maybe hot
;; prev block 2, next block 4, flags: (RTL)
;; pred: 2 [98.4%] (FALLTHRU)
;; bb 3 artificial_defs: { }
;; bb 3 artificial_uses: { u-1(13){ }}
;; lr in 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp] 14 [lr]
;; lr use 0 [r0] 13 [sp]
;; lr def 100 [cc]
;; live in 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp]
;; live gen 100 [cc]
;; live kill
(note 24 23 25 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
(insn 25 24 26 3 (set (reg:CC 100 cc)
(compare:CC (reg/v:SI 0 r0 [orig:112 end ] [112])
(const_int -1 [0xffffffffffffffff]))) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:20 186 {*arm_cmpsi_insn}
(nil))
(jump_insn 26 25 27 3 (set (pc)
(if_then_else (eq (reg:CC 100 cc)
(const_int 0 [0]))
(label_ref:SI 34)
(pc))) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:20 194 {arm_cond_branch}
(expr_list:REG_DEAD (reg:CC 100 cc)
(int_list:REG_BR_PROB 159 (nil)))
-> 34)
;; succ: 8 [1.6%]
;; 4 [98.4%] (FALLTHRU)
;; lr out 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp] 14 [lr]
;; live out 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp]
;; basic block 4, loop depth 0, count 0, freq 9685, maybe hot
;; prev block 3, next block 5, flags: (RTL)
;; pred: 3 [98.4%] (FALLTHRU)
;; bb 4 artificial_defs: { }
;; bb 4 artificial_uses: { u-1(13){ }}
;; lr in 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp] 14 [lr]
;; lr use 0 [r0] 4 [r4] 13 [sp]
;; lr def 0 [r0] 100 [cc]
;; live in 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp]
;; live gen 0 [r0] 100 [cc]
;; live kill
(note 27 26 28 4 [bb 4] NOTE_INSN_BASIC_BLOCK)
(note 28 27 29 4 NOTE_INSN_DELETED)
(insn 29 28 30 4 (parallel [
(set (reg:CC_NOOV 100 cc)
(compare:CC_NOOV (minus:SI (reg/v:SI 0 r0 [orig:112 end ] [112])
(reg/v:SI 4 r4 [orig:111 start ] [111]))
(const_int 0 [0])))
(set (reg/v:SI 0 r0 [orig:114 length ] [114])
(minus:SI (reg/v:SI 0 r0 [orig:112 end ] [112])
(reg/v:SI 4 r4 [orig:111 start ] [111])))
]) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:24 34 {*subsi3_compare0}
(nil))
(jump_insn 30 29 31 4 (set (pc)
(if_then_else (eq (reg:CC_NOOV 100 cc)
(const_int 0 [0]))
(label_ref:SI 54)
(pc))) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:24 194 {arm_cond_branch}
(expr_list:REG_DEAD (reg:CC_NOOV 100 cc)
(int_list:REG_BR_PROB 400 (nil)))
-> 54)
;; succ: 7 [4.0%]
;; 5 [96.0%] (FALLTHRU)
;; lr out 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp] 14 [lr]
;; live out 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp]
;; basic block 5, loop depth 0, count 0, freq 9297, maybe hot
;; prev block 4, next block 7, flags: (RTL)
;; pred: 4 [96.0%] (FALLTHRU)
;; bb 5 artificial_defs: { }
;; bb 5 artificial_uses: { u-1(13){ }}
;; lr in 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp] 14 [lr]
;; lr use 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp]
;; lr def 0 [r0] 3 [r3] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 15 [pc]
;; live in 0 [r0] 4 [r4] 5 [r5] 6 [r6] 13 [sp]
;; live gen 0 [r0] 3 [r3] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 15 [pc]
;; live kill
(note 31 30 32 5 [bb 5] NOTE_INSN_BASIC_BLOCK)
(insn 32 31 33 5 (set (mem:SI (reg/v/f:SI 6 r6 [orig:117 start_ ] [117]) [1 *start__11(D)+0 S4 A32])
(reg/v:SI 4 r4 [orig:111 start ] [111])) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:27 615 {*thumb2_movsi_vfp}
(expr_list:REG_DEAD (reg/v/f:SI 6 r6 [orig:117 start_ ] [117])
(expr_list:REG_DEAD (reg/v:SI 4 r4 [orig:111 start ] [111])
(nil))))
(insn 33 32 7 5 (set (mem:SI (reg/v/f:SI 5 r5 [orig:118 length_ ] [118]) [1 *length__13(D)+0 S4 A32])
(reg/v:SI 0 r0 [orig:114 length ] [114])) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:28 615 {*thumb2_movsi_vfp}
(expr_list:REG_DEAD (reg/v/f:SI 5 r5 [orig:118 length_ ] [118])
(expr_list:REG_DEAD (reg/v:SI 0 r0 [orig:114 length ] [114])
(nil))))
(insn 7 33 85 5 (set (reg:SI 0 r0 [orig:110 D.5141 ] [110])
(const_int 0 [0])) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:30 615 {*thumb2_movsi_vfp}
(expr_list:REG_EQUAL (const_int 0 [0])
(nil)))
(insn 85 7 86 5 (use (reg/i:SI 0 r0)) -1
(nil))
(jump_insn 86 85 77 5 (parallel [
(return)
(set/f (reg/f:SI 13 sp)
(plus:SI (reg/f:SI 13 sp)
(const_int 24 [0x18])))
(set/f (reg:SI 3 r3)
(mem/c:SI (reg/f:SI 13 sp) [2 S4 A32]))
(set/f (reg:SI 4 r4)
(mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 4 [0x4])) [2 S4 A32]))
(set/f (reg:SI 5 r5)
(mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 8 [0x8])) [2 S4 A32]))
(set/f (reg:SI 6 r6)
(mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 12 [0xc])) [2 S4 A32]))
(set/f (reg:SI 7 r7)
(mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 16 [0x10])) [2 S4 A32]))
(set/f (reg:SI 15 pc)
(mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 20 [0x14])) [2 S4 A32]))
]) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:30 -1
(expr_list:REG_UNUSED (reg:SI 15 pc)
(expr_list:REG_UNUSED (reg:SI 3 r3)
(expr_list:REG_CFA_RESTORE (reg:SI 7 r7)
(expr_list:REG_CFA_RESTORE (reg:SI 6 r6)
(expr_list:REG_CFA_RESTORE (reg:SI 5 r5)
(expr_list:REG_CFA_RESTORE (reg:SI 4 r4)
(expr_list:REG_CFA_RESTORE (reg:SI 3 r3)
(nil))))))))
-> return)
;; succ: EXIT [100.0%]
;; lr out 0 [r0] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 14 [lr]
;; live out 0 [r0] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp]
(barrier 77 86 54)
;; basic block 7, loop depth 0, count 0, freq 546, maybe hot
;; prev block 5, next block 8, flags: (RTL)
;; pred: 4 [4.0%]
;; 2 [1.6%]
;; bb 7 artificial_defs: { }
;; bb 7 artificial_uses: { u-1(13){ }}
;; lr in 13 [sp] 14 [lr]
;; lr use 13 [sp]
;; lr def 0 [r0]
;; live in 13 [sp]
;; live gen 0 [r0]
;; live kill
(code_label 54 77 53 7 5 "" [2 uses])
(note 53 54 9 7 [bb 7] NOTE_INSN_BASIC_BLOCK)
(insn 9 53 34 7 (set (reg:SI 0 r0 [orig:110 D.5141 ] [110])
(const_int -1 [0xffffffffffffffff])) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:21 615 {*thumb2_movsi_vfp}
(nil))
;; succ: 8 [100.0%] (FALLTHRU)
;; lr out 0 [r0] 13 [sp] 14 [lr]
;; live out 0 [r0] 13 [sp]
;; basic block 8, loop depth 0, count 0, freq 10000, maybe hot
;; Invalid sum of incoming frequencies 702, should be 10000
;; prev block 7, next block 1, flags: (RTL)
;; pred: 3 [1.6%]
;; 7 [100.0%] (FALLTHRU)
;; bb 8 artificial_defs: { }
;; bb 8 artificial_uses: { u-1(13){ }}
;; lr in 0 [r0] 13 [sp] 14 [lr]
;; lr use 0 [r0] 13 [sp]
;; lr def 3 [r3] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 15 [pc]
;; live in 0 [r0] 13 [sp]
;; live gen 3 [r3] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 15 [pc]
;; live kill
(code_label 34 9 35 8 2 "" [1 uses])
(note 35 34 41 8 [bb 8] NOTE_INSN_BASIC_BLOCK)
(insn 41 35 90 8 (use (reg/i:SI 0 r0)) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:31 -1
(nil))
(jump_insn 90 41 89 8 (parallel [
(return)
(set/f (reg/f:SI 13 sp)
(plus:SI (reg/f:SI 13 sp)
(const_int 24 [0x18])))
(set/f (reg:SI 3 r3)
(mem/c:SI (reg/f:SI 13 sp) [2 S4 A32]))
(set/f (reg:SI 4 r4)
(mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 4 [0x4])) [2 S4 A32]))
(set/f (reg:SI 5 r5)
(mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 8 [0x8])) [2 S4 A32]))
(set/f (reg:SI 6 r6)
(mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 12 [0xc])) [2 S4 A32]))
(set/f (reg:SI 7 r7)
(mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 16 [0x10])) [2 S4 A32]))
(set/f (reg:SI 15 pc)
(mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 20 [0x14])) [2 S4 A32]))
]) /home/shivac/build-system-4.8/src/gcc-src/gcc/testsuite/gcc.target/arm/pr43920-2.c:31 -1
(expr_list:REG_UNUSED (reg:SI 15 pc)
(expr_list:REG_UNUSED (reg:SI 3 r3)
(expr_list:REG_CFA_RESTORE (reg:SI 7 r7)
(expr_list:REG_CFA_RESTORE (reg:SI 6 r6)
(expr_list:REG_CFA_RESTORE (reg:SI 5 r5)
(expr_list:REG_CFA_RESTORE (reg:SI 4 r4)
(expr_list:REG_CFA_RESTORE (reg:SI 3 r3)
(nil))))))))
-> return)
;; succ: EXIT [100.0%]
;; lr out 0 [r0] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp] 14 [lr]
;; live out 0 [r0] 4 [r4] 5 [r5] 6 [r6] 7 [r7] 13 [sp]
(barrier 89 90 82)
(note 82 89 0 NOTE_INSN_DELETED)
[-- Attachment #5: Changelog.can_replace_by --]
[-- Type: application/octet-stream, Size: 423 bytes --]
2015-04-20 Shiva Chen <shiva0217@gmail.com>
Fix testcase pr43920-2.c fail after ira.c update_equiv_regs patch
remove REG_EQUAL note of (set x const_int)
* cfgcleanup.c (can_replace_by): call new function dest_reg_equal_p
to compare the destination register value.
(dest_reg_equal_p): To handle the the case if one of the instruction's
REG_EQUAL is missing but the rtx pattern is (set x const_int).
next parent reply other threads:[~2015-04-20 7:09 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CAH=PD7Z2s3Yw+nWkhKBzEVrvg=aeBLhL-rZJQ=VtpgOjZZ+DLA@mail.gmail.com>
[not found] ` <55312EDF.90005@redhat.com>
2015-04-20 7:09 ` Shiva Chen [this message]
2015-04-21 5:27 ` Jeff Law
2015-07-28 18:55 ` Alex Velenko
2015-07-29 22:44 ` Jeff Law
2015-07-31 11:07 ` Alex Velenko
2015-08-18 9:36 ` Alex Velenko
2015-08-18 9:56 ` Marcus Shawcroft
2015-08-18 10:02 ` Alex Velenko
2015-08-18 10:05 ` Ramana Radhakrishnan
2015-08-18 13:30 ` Ramana Radhakrishnan
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