* [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code
@ 2015-06-03 5:27 Shiva Chen
2015-06-03 8:31 ` Ramana Radhakrishnan
2015-06-03 8:36 ` Kyrill Tkachov
0 siblings, 2 replies; 21+ messages in thread
From: Shiva Chen @ 2015-06-03 5:27 UTC (permalink / raw)
To: GCC Patches, nickc, richard.earnshaw, ramana.radhakrishnan
[-- Attachment #1: Type: text/plain, Size: 2010 bytes --]
Hi,
I noticed that armv8(32 bit target) linux toolchain
run asan testcase would get the following message:
FAIL: c-c++-common/asan/heap-overflow-1.c -O0 output pattern test, is
Executing on host:
/home/gccbuilder-x86/test/mgcc5.0/testsuite/../tools/x86_64/install/bin/qemu-arm
-E LD_LIBRARY_PATH=/home/gccbuilder-x86/test/mgcc5.0/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/bin/../arm-linux-gnueabihf/libc/lib/arm-linux-gnueabihf:/home/gccbuilder-x86/test/mgcc5.0/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/bin/../arm-linux-gnueabihf/libc/usr/lib/arm-linux-gnueabihf
-L /home/gccbuilder-x86/test/mgcc5.0/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/bin/../arm-linux-gnueabihf/libc
./heap-overflow-1.exe
=================================================================
==2182==ERROR: AddressSanitizer: heap-buffer-overflow on address
0xf4a007fa at pc 0x000108a0 bp 0xf6ffc264 sp 0xf6ffc25c
READ of size 1 at 0xf4a007fa thread T0
ASAN:SIGSEGV
sanitizer library use the source in gcc-src/libbacktrace to allocate memory.
The error cause by null pointer reference in libbacktrace/mmap.c
void
backtrace_free (struct backtrace_state *state, void *addr, size_t size,
backtrace_error_callback error_callback ATTRIBUTE_UNUSED,
void *data ATTRIBUTE_UNUSED)
...
if (locked)
{
backtrace_free_locked (state, addr, size);
if (state->threaded) <= line 201
__sync_lock_release (&state->lock_alloc); <= line 202
}
}
.loc 1 201 0
cmp r3, #0 <= r3 contain the value of state->threaded
.loc 1 202 0
addne r3, r5, #32
movne r2, #0
stl r2, [r3] <= should be conditional execution
when r3 is 0, line 202 should not execute.
It seems that stl should generate as stlne.
Otherwise, slt will get null reference when r3 is 0.
To fix the issue, add %? when output stl assembly pattern in sync.md.
Is this patch ok for trunk?
Thanks,
Shiva
[-- Attachment #2: Fix_slt_lda_missing_conditional_code.diff --]
[-- Type: text/plain, Size: 877 bytes --]
diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md
index 44cda61..79b039e 100644
--- a/gcc/config/arm/sync.md
+++ b/gcc/config/arm/sync.md
@@ -75,9 +75,9 @@
{
enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_release (model))
- return \"ldr<sync_sfx>\\t%0, %1\";
+ return \"ldr<sync_sfx>%?\\t%0, %1\";
else
- return \"lda<sync_sfx>\\t%0, %1\";
+ return \"lda<sync_sfx>%?\\t%0, %1\";
}
)
@@ -91,9 +91,9 @@
{
enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_acquire (model))
- return \"str<sync_sfx>\t%1, %0\";
+ return \"str<sync_sfx>%?\t%1, %0\";
else
- return \"stl<sync_sfx>\t%1, %0\";
+ return \"stl<sync_sfx>%?\t%1, %0\";
}
)
[-- Attachment #3: ChangeLog.fix_slt_lda_missing_conditional_code --]
[-- Type: application/octet-stream, Size: 247 bytes --]
2015-06-03 Shiva Chen <shiva0217@gmail.com>
Add conditional code for arm load acquire/store release instructions
* sync.md (atomic_load<mode>): add conditional code for lda/ldr
(atomic_store<mode>): add conditional code for stl/str
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code 2015-06-03 5:27 [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code Shiva Chen @ 2015-06-03 8:31 ` Ramana Radhakrishnan 2015-06-03 8:36 ` Kyrill Tkachov 1 sibling, 0 replies; 21+ messages in thread From: Ramana Radhakrishnan @ 2015-06-03 8:31 UTC (permalink / raw) To: Shiva Chen, GCC Patches, nickc, Richard Earnshaw On 03/06/15 05:12, Shiva Chen wrote: <snip> > > It seems that stl should generate as stlne. > > Otherwise, slt will get null reference when r3 is 0. > > > To fix the issue, add %? when output stl assembly pattern in sync.md. Please also mark these patterns as predicable. i.e. (set_attr "predicable" "yes"). > > Is this patch ok for trunk? Ouch, ok with that change for trunk and affected release branches after a round of regression testing. Can I also confirm you have a copyright assignment on file ? regards Ramana > > Thanks, > Shiva > ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code 2015-06-03 5:27 [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code Shiva Chen 2015-06-03 8:31 ` Ramana Radhakrishnan @ 2015-06-03 8:36 ` Kyrill Tkachov [not found] ` <556EBBAC.2020504@arm.com> 1 sibling, 1 reply; 21+ messages in thread From: Kyrill Tkachov @ 2015-06-03 8:36 UTC (permalink / raw) To: Shiva Chen, GCC Patches, nickc, Richard Earnshaw, Ramana Radhakrishnan Hi Shiva, On 03/06/15 05:12, Shiva Chen wrote: > Hi, > > I noticed that armv8(32 bit target) linux toolchain > > run asan testcase would get the following message: > > > FAIL: c-c++-common/asan/heap-overflow-1.c -O0 output pattern test, is > Executing on host: > /home/gccbuilder-x86/test/mgcc5.0/testsuite/../tools/x86_64/install/bin/qemu-arm > -E LD_LIBRARY_PATH=/home/gccbuilder-x86/test/mgcc5.0/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/bin/../arm-linux-gnueabihf/libc/lib/arm-linux-gnueabihf:/home/gccbuilder-x86/test/mgcc5.0/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/bin/../arm-linux-gnueabihf/libc/usr/lib/arm-linux-gnueabihf > -L/home/gccbuilder-x86/test/mgcc5.0/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/bin/../arm-linux-gnueabihf/libc > ./heap-overflow-1.exe > ================================================================= > ==2182==ERROR: AddressSanitizer: heap-buffer-overflow on address > 0xf4a007fa at pc 0x000108a0 bp 0xf6ffc264 sp 0xf6ffc25c > READ of size 1 at 0xf4a007fa thread T0 > ASAN:SIGSEGV > > > sanitizer library use the source in gcc-src/libbacktrace to allocate memory. > > The error cause by null pointer reference in libbacktrace/mmap.c > > > void > backtrace_free (struct backtrace_state *state, void *addr, size_t size, > backtrace_error_callback error_callback ATTRIBUTE_UNUSED, > void *data ATTRIBUTE_UNUSED) > ... > if (locked) > { > backtrace_free_locked (state, addr, size); > > if (state->threaded) <= line 201 > __sync_lock_release (&state->lock_alloc); <= line 202 > } > } > > .loc 1 201 0 > cmp r3, #0 <= r3 contain the value of state->threaded > .loc 1 202 0 > addne r3, r5, #32 > movne r2, #0 > stl r2, [r3] <= should be conditional execution I think you're right. > > when r3 is 0, line 202 should not execute. > > It seems that stl should generate as stlne. > > Otherwise, slt will get null reference when r3 is 0. > > > To fix the issue, add %? when output stl assembly pattern in sync.md. > > Is this patch ok for trunk? > > Thanks, > Shiva > > Fix_slt_lda_missing_conditional_code.diff > > > diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md > index 44cda61..79b039e 100644 > --- a/gcc/config/arm/sync.md > +++ b/gcc/config/arm/sync.md > @@ -75,9 +75,9 @@ > { > enum memmodel model = memmodel_from_int (INTVAL (operands[2])); > if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_release (model)) > - return \"ldr<sync_sfx>\\t%0, %1\"; > + return \"ldr<sync_sfx>%?\\t%0, %1\"; > else > - return \"lda<sync_sfx>\\t%0, %1\"; > + return \"lda<sync_sfx>%?\\t%0, %1\"; > } > ) This pattern is not predicable though, i.e. it doesn't have the "predicable" attribute set to "yes". Therefore the compiler should be trying to branch around here rather than try to do a cond_exec. Why does the generated code above look like it's converted to conditional execution? Could you produce a self-contained reduced testcase for this? Thanks, Kyrill > > @@ -91,9 +91,9 @@ > { > enum memmodel model = memmodel_from_int (INTVAL (operands[2])); > if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_acquire (model)) > - return \"str<sync_sfx>\t%1, %0\"; > + return \"str<sync_sfx>%?\t%1, %0\"; > else > - return \"stl<sync_sfx>\t%1, %0\"; > + return \"stl<sync_sfx>%?\t%1, %0\"; > } > ) > ^ permalink raw reply [flat|nested] 21+ messages in thread
[parent not found: <556EBBAC.2020504@arm.com>]
* Re: [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code [not found] ` <556EBBAC.2020504@arm.com> @ 2015-06-03 8:53 ` Kyrill Tkachov 2015-06-03 9:33 ` Shiva Chen 0 siblings, 1 reply; 21+ messages in thread From: Kyrill Tkachov @ 2015-06-03 8:53 UTC (permalink / raw) To: Ramana Radhakrishnan, Shiva Chen, GCC Patches, nickc, Richard Earnshaw On 03/06/15 09:32, Ramana Radhakrishnan wrote: >> This pattern is not predicable though, i.e. it doesn't have the "predicable" attribute set to "yes". >> Therefore the compiler should be trying to branch around here rather than try to do a cond_exec. >> Why does the generated code above look like it's converted to conditional execution? >> Could you produce a self-contained reduced testcase for this? > CCFSM state machine in ARM state. > > arm.c (final_prescan_insn). Ah ok. This patch makes sense then. As Ramana mentioned, please mark the pattern with "predicable" and also set the "predicable_short_it" attribute to "no" so that it will not be conditionalised in Thumb2 mode or when -mrestrict-it is enabled. Thanks, Kyrill > > Ramana > >> Thanks, >> Kyrill >> >>> @@ -91,9 +91,9 @@ >>> { >>> enum memmodel model = memmodel_from_int (INTVAL (operands[2])); >>> if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_acquire (model)) >>> - return \"str<sync_sfx>\t%1, %0\"; >>> + return \"str<sync_sfx>%?\t%1, %0\"; >>> else >>> - return \"stl<sync_sfx>\t%1, %0\"; >>> + return \"stl<sync_sfx>%?\t%1, %0\"; >>> } >>> ) >>> ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code 2015-06-03 8:53 ` Kyrill Tkachov @ 2015-06-03 9:33 ` Shiva Chen 2015-06-04 4:51 ` Shiva Chen 0 siblings, 1 reply; 21+ messages in thread From: Shiva Chen @ 2015-06-03 9:33 UTC (permalink / raw) To: Kyrill Tkachov; +Cc: Ramana Radhakrishnan, GCC Patches, nickc, Richard Earnshaw [-- Attachment #1: Type: text/plain, Size: 1606 bytes --] Hi, Ramana I'm not sure what copyright assignment means ? Does it mean the patch have copyright assignment or not ? I update the patch to add "predicable" and "predicable_short_it" attribute as suggestion. However, I don't have svn write access yet. Shiva 2015-06-03 16:36 GMT+08:00 Kyrill Tkachov <kyrylo.tkachov@arm.com>: > > On 03/06/15 09:32, Ramana Radhakrishnan wrote: >>> >>> This pattern is not predicable though, i.e. it doesn't have the >>> "predicable" attribute set to "yes". >>> Therefore the compiler should be trying to branch around here rather than >>> try to do a cond_exec. >>> Why does the generated code above look like it's converted to conditional >>> execution? >>> Could you produce a self-contained reduced testcase for this? >> >> CCFSM state machine in ARM state. >> >> arm.c (final_prescan_insn). > > > Ah ok. > This patch makes sense then. > As Ramana mentioned, please mark the pattern with "predicable" and also set > the "predicable_short_it" attribute to "no" so that it will not be > conditionalised in Thumb2 mode or when -mrestrict-it is enabled. > > Thanks, > Kyrill > > > >> >> Ramana >> >>> Thanks, >>> Kyrill >>> >>>> @@ -91,9 +91,9 @@ >>>> { >>>> enum memmodel model = memmodel_from_int (INTVAL (operands[2])); >>>> if (is_mm_relaxed (model) || is_mm_consume (model) || >>>> is_mm_acquire (model)) >>>> - return \"str<sync_sfx>\t%1, %0\"; >>>> + return \"str<sync_sfx>%?\t%1, %0\"; >>>> else >>>> - return \"stl<sync_sfx>\t%1, %0\"; >>>> + return \"stl<sync_sfx>%?\t%1, %0\"; >>>> } >>>> ) >>>> > [-- Attachment #2: Fix_slt_lda_missing_conditional_code.diff --] [-- Type: text/plain, Size: 1274 bytes --] diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md index 44cda61..cf8f3a3 100644 --- a/gcc/config/arm/sync.md +++ b/gcc/config/arm/sync.md @@ -75,11 +75,12 @@ { enum memmodel model = memmodel_from_int (INTVAL (operands[2])); if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_release (model)) - return \"ldr<sync_sfx>\\t%0, %1\"; + return \"ldr<sync_sfx>%?\\t%0, %1\"; else - return \"lda<sync_sfx>\\t%0, %1\"; + return \"lda<sync_sfx>%?\\t%0, %1\"; } -) + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no")]) (define_insn "atomic_store<mode>" [(set (match_operand:QHSI 0 "memory_operand" "=Q") @@ -91,11 +92,12 @@ { enum memmodel model = memmodel_from_int (INTVAL (operands[2])); if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_acquire (model)) - return \"str<sync_sfx>\t%1, %0\"; + return \"str<sync_sfx>%?\t%1, %0\"; else - return \"stl<sync_sfx>\t%1, %0\"; + return \"stl<sync_sfx>%?\t%1, %0\"; } -) + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no")]) ;; Note that ldrd and vldr are *not* guaranteed to be single-copy atomic, ;; even for a 64-bit aligned address. Instead we use a ldrexd unparied ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code 2015-06-03 9:33 ` Shiva Chen @ 2015-06-04 4:51 ` Shiva Chen 2015-06-04 8:24 ` Kyrill Tkachov 0 siblings, 1 reply; 21+ messages in thread From: Shiva Chen @ 2015-06-04 4:51 UTC (permalink / raw) To: Kyrill Tkachov Cc: Ramana Radhakrishnan, GCC Patches, nickc, Richard Earnshaw, shivac [-- Attachment #1: Type: text/plain, Size: 2620 bytes --] Hi, Ramana Currently, I work for Marvell and the company have copyright assignment on file. Hi, all After adding the attribute and rebuild gcc, I got the assembler error message load_n.s:39: Error: bad instruction `ldrbeq r0,[r0]' When i look into armv8 ISA document, it seems ldrb Encoding A1 have conditional code field. Does it mean we should also patch assembler or I just miss understanding something ? Following command use to generate load_n.s: /home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/./gcc/cc1 -fpreprocessed load_n.i -quiet -dumpbase load_n.c -march=armv8-a -mfloat-abi=hard -mfpu=fp-armv8 -mtls-dialect=gnu -auxbase-strip .libs/load_1_.o -g3 -O2 -Wall -Werror -version -fPIC -funwind-tables -o load_n.s The test.c is a simple test case to reproduce missing conditional code in mmap.c. Any suggestion ? Shiva 2015-06-03 17:29 GMT+08:00 Shiva Chen <shiva0217@gmail.com>: > Hi, Ramana > > I'm not sure what copyright assignment means ? > > Does it mean the patch have copyright assignment or not ? > > I update the patch to add "predicable" and "predicable_short_it" > attribute as suggestion. > > However, I don't have svn write access yet. > > Shiva > > 2015-06-03 16:36 GMT+08:00 Kyrill Tkachov <kyrylo.tkachov@arm.com>: >> >> On 03/06/15 09:32, Ramana Radhakrishnan wrote: >>>> >>>> This pattern is not predicable though, i.e. it doesn't have the >>>> "predicable" attribute set to "yes". >>>> Therefore the compiler should be trying to branch around here rather than >>>> try to do a cond_exec. >>>> Why does the generated code above look like it's converted to conditional >>>> execution? >>>> Could you produce a self-contained reduced testcase for this? >>> >>> CCFSM state machine in ARM state. >>> >>> arm.c (final_prescan_insn). >> >> >> Ah ok. >> This patch makes sense then. >> As Ramana mentioned, please mark the pattern with "predicable" and also set >> the "predicable_short_it" attribute to "no" so that it will not be >> conditionalised in Thumb2 mode or when -mrestrict-it is enabled. >> >> Thanks, >> Kyrill >> >> >> >>> >>> Ramana >>> >>>> Thanks, >>>> Kyrill >>>> >>>>> @@ -91,9 +91,9 @@ >>>>> { >>>>> enum memmodel model = memmodel_from_int (INTVAL (operands[2])); >>>>> if (is_mm_relaxed (model) || is_mm_consume (model) || >>>>> is_mm_acquire (model)) >>>>> - return \"str<sync_sfx>\t%1, %0\"; >>>>> + return \"str<sync_sfx>%?\t%1, %0\"; >>>>> else >>>>> - return \"stl<sync_sfx>\t%1, %0\"; >>>>> + return \"stl<sync_sfx>%?\t%1, %0\"; >>>>> } >>>>> ) >>>>> >> [-- Attachment #2: load_n.i --] [-- Type: application/octet-stream, Size: 98256 bytes --] # 1 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/config/linux/arm/load_n.c" # 1 "/home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/arm-linux-gnueabihf/libatomic//" # 1 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__UINTMAX_C(c) c ## ULL #define __SIG_ATOMIC_MAX__ 0x7fffffff #define __SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1) #define __INT8_MAX__ 0x7f #define __INT16_MAX__ 0x7fff #define __INT32_MAX__ 0x7fffffff #define __INT64_MAX__ 0x7fffffffffffffffLL #define __UINT8_MAX__ 0xff #define __UINT16_MAX__ 0xffff #define __UINT32_MAX__ 0xffffffffU #define __UINT64_MAX__ 0xffffffffffffffffULL #define __INT_LEAST8_MAX__ 0x7f #define __INT8_C(c) c #define __INT_LEAST16_MAX__ 0x7fff #define __INT16_C(c) c #define __INT_LEAST32_MAX__ 0x7fffffff #define __INT32_C(c) c #define __INT_LEAST64_MAX__ 0x7fffffffffffffffLL #define __INT64_C(c) c ## LL #define __UINT_LEAST8_MAX__ 0xff #define __UINT8_C(c) c #define __UINT_LEAST16_MAX__ 0xffff #define __UINT16_C(c) c #define __UINT_LEAST32_MAX__ 0xffffffffU #define __UINT32_C(c) c ## U #define __UINT_LEAST64_MAX__ 0xffffffffffffffffULL #define __UINT64_C(c) c ## ULL #define __INT_FAST8_MAX__ 0x7f #define __INT_FAST16_MAX__ 0x7fffffff #define __INT_FAST32_MAX__ 0x7fffffff #define __INT_FAST64_MAX__ 0x7fffffffffffffffLL #define __UINT_FAST8_MAX__ 0xff #define __UINT_FAST16_MAX__ 0xffffffffU #define __UINT_FAST32_MAX__ 0xffffffffU #define __UINT_FAST64_MAX__ 0xffffffffffffffffULL #define __INTPTR_MAX__ 0x7fffffff #define __UINTPTR_MAX__ 0xffffffffU #define __GCC_IEC_559 2 #define __GCC_IEC_559_COMPLEX 2 #define __FLT_EVAL_METHOD__ 0 #define __DEC_EVAL_METHOD__ 2 #define __FLT_RADIX__ 2 #define __FLT_MANT_DIG__ 24 #define __FLT_DIG__ 6 #define __FLT_MIN_EXP__ (-125) #define __FLT_MIN_10_EXP__ (-37) #define __FLT_MAX_EXP__ 128 #define __FLT_MAX_10_EXP__ 38 #define __FLT_DECIMAL_DIG__ 9 #define __FLT_MAX__ 3.4028234663852886e+38F #define __FLT_MIN__ 1.1754943508222875e-38F #define __FLT_EPSILON__ 1.1920928955078125e-7F #define __FLT_DENORM_MIN__ 1.4012984643248171e-45F #define __FLT_HAS_DENORM__ 1 #define __FLT_HAS_INFINITY__ 1 #define __FLT_HAS_QUIET_NAN__ 1 #define __FP_FAST_FMAF 1 #define __DBL_MANT_DIG__ 53 #define __DBL_DIG__ 15 #define __DBL_MIN_EXP__ (-1021) #define __DBL_MIN_10_EXP__ (-307) #define __DBL_MAX_EXP__ 1024 #define __DBL_MAX_10_EXP__ 308 #define __DBL_DECIMAL_DIG__ 17 #define __DBL_MAX__ ((double)1.7976931348623157e+308L) #define __DBL_MIN__ ((double)2.2250738585072014e-308L) #define __DBL_EPSILON__ ((double)2.2204460492503131e-16L) #define __DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L) #define __DBL_HAS_DENORM__ 1 #define __DBL_HAS_INFINITY__ 1 #define __DBL_HAS_QUIET_NAN__ 1 #define __FP_FAST_FMA 1 #define __LDBL_MANT_DIG__ 53 #define __LDBL_DIG__ 15 #define __LDBL_MIN_EXP__ (-1021) #define __LDBL_MIN_10_EXP__ (-307) #define __LDBL_MAX_EXP__ 1024 #define __LDBL_MAX_10_EXP__ 308 #define __DECIMAL_DIG__ 17 #define __LDBL_MAX__ 1.7976931348623157e+308L #define __LDBL_MIN__ 2.2250738585072014e-308L #define __LDBL_EPSILON__ 2.2204460492503131e-16L #define __LDBL_DENORM_MIN__ 4.9406564584124654e-324L #define __LDBL_HAS_DENORM__ 1 #define __LDBL_HAS_INFINITY__ 1 #define __LDBL_HAS_QUIET_NAN__ 1 #define __FP_FAST_FMAL 1 #define __DEC32_MANT_DIG__ 7 #define __DEC32_MIN_EXP__ (-94) #define __DEC32_MAX_EXP__ 97 #define __DEC32_MIN__ 1E-95DF #define __DEC32_MAX__ 9.999999E96DF #define __DEC32_EPSILON__ 1E-6DF #define __DEC32_SUBNORMAL_MIN__ 0.000001E-95DF #define __DEC64_MANT_DIG__ 16 #define __DEC64_MIN_EXP__ (-382) #define __DEC64_MAX_EXP__ 385 #define __DEC64_MIN__ 1E-383DD #define __DEC64_MAX__ 9.999999999999999E384DD #define __DEC64_EPSILON__ 1E-15DD #define __DEC64_SUBNORMAL_MIN__ 0.000000000000001E-383DD #define __DEC128_MANT_DIG__ 34 #define __DEC128_MIN_EXP__ (-6142) #define __DEC128_MAX_EXP__ 6145 #define __DEC128_MIN__ 1E-6143DL #define __DEC128_MAX__ 9.999999999999999999999999999999999E6144DL #define __DEC128_EPSILON__ 1E-33DL #define __DEC128_SUBNORMAL_MIN__ 0.000000000000000000000000000000001E-6143DL #define __SFRACT_FBIT__ 7 #define __SFRACT_IBIT__ 0 #define __SFRACT_MIN__ (-0.5HR-0.5HR) #define __SFRACT_MAX__ 0X7FP-7HR #define __SFRACT_EPSILON__ 0x1P-7HR #define __USFRACT_FBIT__ 8 #define __USFRACT_IBIT__ 0 #define __USFRACT_MIN__ 0.0UHR #define __USFRACT_MAX__ 0XFFP-8UHR #define __USFRACT_EPSILON__ 0x1P-8UHR #define __FRACT_FBIT__ 15 #define __FRACT_IBIT__ 0 #define __FRACT_MIN__ (-0.5R-0.5R) #define __FRACT_MAX__ 0X7FFFP-15R #define __FRACT_EPSILON__ 0x1P-15R #define __UFRACT_FBIT__ 16 #define __UFRACT_IBIT__ 0 #define __UFRACT_MIN__ 0.0UR #define __UFRACT_MAX__ 0XFFFFP-16UR #define __UFRACT_EPSILON__ 0x1P-16UR #define __LFRACT_FBIT__ 31 #define __LFRACT_IBIT__ 0 #define __LFRACT_MIN__ (-0.5LR-0.5LR) #define __LFRACT_MAX__ 0X7FFFFFFFP-31LR #define __LFRACT_EPSILON__ 0x1P-31LR #define __ULFRACT_FBIT__ 32 #define __ULFRACT_IBIT__ 0 #define __ULFRACT_MIN__ 0.0ULR #define __ULFRACT_MAX__ 0XFFFFFFFFP-32ULR #define __ULFRACT_EPSILON__ 0x1P-32ULR #define __LLFRACT_FBIT__ 63 #define __LLFRACT_IBIT__ 0 #define __LLFRACT_MIN__ (-0.5LLR-0.5LLR) #define __LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLR #define __LLFRACT_EPSILON__ 0x1P-63LLR #define __ULLFRACT_FBIT__ 64 #define __ULLFRACT_IBIT__ 0 #define __ULLFRACT_MIN__ 0.0ULLR #define __ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLR #define __ULLFRACT_EPSILON__ 0x1P-64ULLR #define __SACCUM_FBIT__ 7 #define __SACCUM_IBIT__ 8 #define __SACCUM_MIN__ (-0X1P7HK-0X1P7HK) #define __SACCUM_MAX__ 0X7FFFP-7HK #define __SACCUM_EPSILON__ 0x1P-7HK #define __USACCUM_FBIT__ 8 #define __USACCUM_IBIT__ 8 #define __USACCUM_MIN__ 0.0UHK #define __USACCUM_MAX__ 0XFFFFP-8UHK #define __USACCUM_EPSILON__ 0x1P-8UHK #define __ACCUM_FBIT__ 15 #define __ACCUM_IBIT__ 16 #define __ACCUM_MIN__ (-0X1P15K-0X1P15K) #define __ACCUM_MAX__ 0X7FFFFFFFP-15K #define __ACCUM_EPSILON__ 0x1P-15K #define __UACCUM_FBIT__ 16 #define __UACCUM_IBIT__ 16 #define __UACCUM_MIN__ 0.0UK #define __UACCUM_MAX__ 0XFFFFFFFFP-16UK #define __UACCUM_EPSILON__ 0x1P-16UK #define __LACCUM_FBIT__ 31 #define __LACCUM_IBIT__ 32 #define __LACCUM_MIN__ (-0X1P31LK-0X1P31LK) #define __LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK #define __LACCUM_EPSILON__ 0x1P-31LK #define __ULACCUM_FBIT__ 32 #define __ULACCUM_IBIT__ 32 #define __ULACCUM_MIN__ 0.0ULK #define __ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULK #define __ULACCUM_EPSILON__ 0x1P-32ULK #define __LLACCUM_FBIT__ 31 #define __LLACCUM_IBIT__ 32 #define __LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK) #define __LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK #define __LLACCUM_EPSILON__ 0x1P-31LLK #define __ULLACCUM_FBIT__ 32 #define __ULLACCUM_IBIT__ 32 #define __ULLACCUM_MIN__ 0.0ULLK #define __ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLK #define __ULLACCUM_EPSILON__ 0x1P-32ULLK #define __QQ_FBIT__ 7 #define __QQ_IBIT__ 0 #define __HQ_FBIT__ 15 #define __HQ_IBIT__ 0 #define __SQ_FBIT__ 31 #define __SQ_IBIT__ 0 #define __DQ_FBIT__ 63 #define __DQ_IBIT__ 0 #define __TQ_FBIT__ 127 #define __TQ_IBIT__ 0 #define __UQQ_FBIT__ 8 #define __UQQ_IBIT__ 0 #define __UHQ_FBIT__ 16 #define __UHQ_IBIT__ 0 #define __USQ_FBIT__ 32 #define __USQ_IBIT__ 0 #define __UDQ_FBIT__ 64 #define __UDQ_IBIT__ 0 #define __UTQ_FBIT__ 128 #define __UTQ_IBIT__ 0 #define __HA_FBIT__ 7 #define __HA_IBIT__ 8 #define __SA_FBIT__ 15 #define __SA_IBIT__ 16 #define __DA_FBIT__ 31 #define __DA_IBIT__ 32 #define __TA_FBIT__ 63 #define __TA_IBIT__ 64 #define __UHA_FBIT__ 8 #define __UHA_IBIT__ 8 #define __USA_FBIT__ 16 #define __USA_IBIT__ 16 #define __UDA_FBIT__ 32 #define __UDA_IBIT__ 32 #define __UTA_FBIT__ 64 #define __UTA_IBIT__ 64 #define __REGISTER_PREFIX__ #define __USER_LABEL_PREFIX__ #define __GNUC_STDC_INLINE__ 1 #define __CHAR_UNSIGNED__ 1 #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1 #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1 #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1 #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1 #define __GCC_ATOMIC_BOOL_LOCK_FREE 2 #define __GCC_ATOMIC_CHAR_LOCK_FREE 2 #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2 #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2 #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2 #define __GCC_ATOMIC_SHORT_LOCK_FREE 2 #define __GCC_ATOMIC_INT_LOCK_FREE 2 #define __GCC_ATOMIC_LONG_LOCK_FREE 2 #define __GCC_ATOMIC_LLONG_LOCK_FREE 2 #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1 #define __GCC_ATOMIC_POINTER_LOCK_FREE 2 #define __GCC_HAVE_DWARF2_CFI_ASM 1 #define __PRAGMA_REDEFINE_EXTNAME 1 #define __SIZEOF_WCHAR_T__ 4 #define __SIZEOF_WINT_T__ 4 #define __SIZEOF_PTRDIFF_T__ 4 #define __ARM_FEATURE_DSP 1 #define __ARM_FEATURE_QBIT 1 #define __ARM_FEATURE_SAT 1 #define __ARM_FEATURE_UNALIGNED 1 #define __ARM_32BIT_STATE 1 #define __ARM_FEATURE_LDREX 15 #define __ARM_FEATURE_CLZ 1 #define __ARM_FEATURE_SIMD32 1 #define __ARM_SIZEOF_MINIMAL_ENUM 4 #define __ARM_SIZEOF_WCHAR_T 4 #define __ARM_ARCH_PROFILE 65 #define __arm__ 1 #define __ARM_ARCH 8 #define __ARM_ARCH_ISA_ARM 1 #define __APCS_32__ 1 #define __ARM_ARCH_ISA_THUMB 2 #define __ARMEL__ 1 #define __VFP_FP__ 1 #define __ARM_FP 14 #define __ARM_FEATURE_FMA 1 #define __THUMB_INTERWORK__ 1 #define __ARM_ARCH_8A__ 1 #define __ARM_PCS_VFP 1 #define __ARM_EABI__ 1 #define __ARM_ARCH_EXT_IDIV__ 1 #define __ARM_FEATURE_IDIV 1 #define __GXX_TYPEINFO_EQUALITY_INLINE 0 #define __gnu_linux__ 1 #define __linux 1 #define __linux__ 1 #define linux 1 #define __unix 1 #define __unix__ 1 #define unix 1 #define __ELF__ 1 # 1 "<command-line>" #define _REENTRANT 1 #define HAVE_CONFIG_H 1 #define N 1 #define PIC 1 # 1 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/stdc-predef.h" 1 3 4 # 19 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/stdc-predef.h" 3 4 #define _STDC_PREDEF_H 1 # 38 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/stdc-predef.h" 3 4 #define __STDC_IEC_559__ 1 #define __STDC_IEC_559_COMPLEX__ 1 # 59 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/stdc-predef.h" 3 4 #define __STDC_ISO_10646__ 201304L #define __STDC_NO_THREADS__ 1 # 1 "<command-line>" 2 # 1 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/config/linux/arm/load_n.c" # 25 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/config/linux/arm/load_n.c" # 1 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" 1 # 29 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" #define LIBATOMIC_H 1 # 1 "./auto-config.h" 1 #define HAVE_ATOMIC_CAS_1 1 #define HAVE_ATOMIC_CAS_16 0 #define HAVE_ATOMIC_CAS_2 1 #define HAVE_ATOMIC_CAS_4 1 #define HAVE_ATOMIC_CAS_8 1 #define HAVE_ATOMIC_EXCHANGE_1 1 #define HAVE_ATOMIC_EXCHANGE_16 0 #define HAVE_ATOMIC_EXCHANGE_2 1 #define HAVE_ATOMIC_EXCHANGE_4 1 #define HAVE_ATOMIC_EXCHANGE_8 1 #define HAVE_ATOMIC_FETCH_ADD_1 1 #define HAVE_ATOMIC_FETCH_ADD_16 0 #define HAVE_ATOMIC_FETCH_ADD_2 1 #define HAVE_ATOMIC_FETCH_ADD_4 1 #define HAVE_ATOMIC_FETCH_ADD_8 1 #define HAVE_ATOMIC_FETCH_OP_1 1 #define HAVE_ATOMIC_FETCH_OP_16 0 #define HAVE_ATOMIC_FETCH_OP_2 1 #define HAVE_ATOMIC_FETCH_OP_4 1 #define HAVE_ATOMIC_FETCH_OP_8 1 #define HAVE_ATOMIC_LDST_1 1 #define HAVE_ATOMIC_LDST_16 0 #define HAVE_ATOMIC_LDST_2 1 #define HAVE_ATOMIC_LDST_4 1 #define HAVE_ATOMIC_LDST_8 1 #define HAVE_ATOMIC_TAS_1 1 #define HAVE_ATOMIC_TAS_16 0 #define HAVE_ATOMIC_TAS_2 1 #define HAVE_ATOMIC_TAS_4 1 #define HAVE_ATOMIC_TAS_8 1 #define HAVE_ATTRIBUTE_ALIAS 1 #define HAVE_ATTRIBUTE_VISIBILITY 1 #define HAVE_DLFCN_H 1 #define HAVE_FENV_H 1 #define HAVE_IFUNC 1 #define HAVE_INT1 1 #define HAVE_INT16 0 #define HAVE_INT2 1 #define HAVE_INT4 1 #define HAVE_INT8 1 #define HAVE_INTTYPES_H 1 #define HAVE_MEMORY_H 1 #define HAVE_STDINT_H 1 #define HAVE_STDLIB_H 1 #define HAVE_STRINGS_H 1 #define HAVE_STRING_H 1 #define HAVE_SYS_STAT_H 1 #define HAVE_SYS_TYPES_H 1 #define HAVE_UNISTD_H 1 #define LIBAT_GNU_SYMBOL_VERSIONING 1 #define LT_OBJDIR ".libs/" #define PACKAGE "libatomic" #define PACKAGE_BUGREPORT "" #define PACKAGE_NAME "GNU Atomic Library" #define PACKAGE_STRING "GNU Atomic Library 1.0" #define PACKAGE_TARNAME "libatomic" #define PACKAGE_URL "http://www.gnu.org/software/libatomic/" #define PACKAGE_VERSION "1.0" # 201 "./auto-config.h" #define STDC_HEADERS 1 #define STRING_WITH_STRINGS 1 #define VERSION "1.0" #define WORDSIZE 4 # 224 "./auto-config.h" #define MAYBE_HAVE_ATOMIC_LDST_1 HAVE_ATOMIC_LDST_1 #define MAYBE_HAVE_ATOMIC_TAS_16 HAVE_ATOMIC_TAS_16 #define MAYBE_HAVE_ATOMIC_EXCHANGE_1 HAVE_ATOMIC_EXCHANGE_1 #define MAYBE_HAVE_ATOMIC_EXCHANGE_2 HAVE_ATOMIC_EXCHANGE_2 #define MAYBE_HAVE_ATOMIC_EXCHANGE_4 HAVE_ATOMIC_EXCHANGE_4 #define MAYBE_HAVE_ATOMIC_EXCHANGE_8 HAVE_ATOMIC_EXCHANGE_8 #define MAYBE_HAVE_ATOMIC_EXCHANGE_16 HAVE_ATOMIC_EXCHANGE_16 #define MAYBE_HAVE_ATOMIC_CAS_1 HAVE_ATOMIC_CAS_1 #define MAYBE_HAVE_ATOMIC_CAS_2 HAVE_ATOMIC_CAS_2 #define MAYBE_HAVE_ATOMIC_CAS_4 HAVE_ATOMIC_CAS_4 #define MAYBE_HAVE_ATOMIC_CAS_8 HAVE_ATOMIC_CAS_8 #define MAYBE_HAVE_ATOMIC_LDST_2 HAVE_ATOMIC_LDST_2 #define MAYBE_HAVE_ATOMIC_CAS_16 HAVE_ATOMIC_CAS_16 #define MAYBE_HAVE_ATOMIC_FETCH_ADD_1 HAVE_ATOMIC_FETCH_ADD_1 #define MAYBE_HAVE_ATOMIC_FETCH_ADD_2 HAVE_ATOMIC_FETCH_ADD_2 #define MAYBE_HAVE_ATOMIC_FETCH_ADD_4 HAVE_ATOMIC_FETCH_ADD_4 #define MAYBE_HAVE_ATOMIC_FETCH_ADD_8 HAVE_ATOMIC_FETCH_ADD_8 #define MAYBE_HAVE_ATOMIC_FETCH_ADD_16 HAVE_ATOMIC_FETCH_ADD_16 #define MAYBE_HAVE_ATOMIC_FETCH_OP_1 HAVE_ATOMIC_FETCH_OP_1 #define MAYBE_HAVE_ATOMIC_FETCH_OP_2 HAVE_ATOMIC_FETCH_OP_2 #define MAYBE_HAVE_ATOMIC_FETCH_OP_4 HAVE_ATOMIC_FETCH_OP_4 #define MAYBE_HAVE_ATOMIC_FETCH_OP_8 HAVE_ATOMIC_FETCH_OP_8 #define MAYBE_HAVE_ATOMIC_LDST_4 HAVE_ATOMIC_LDST_4 #define MAYBE_HAVE_ATOMIC_FETCH_OP_16 HAVE_ATOMIC_FETCH_OP_16 #define WORDS_BIGENDIAN 0 #define MAYBE_HAVE_ATOMIC_LDST_8 HAVE_ATOMIC_LDST_8 #define MAYBE_HAVE_ATOMIC_LDST_16 HAVE_ATOMIC_LDST_16 #define MAYBE_HAVE_ATOMIC_TAS_1 HAVE_ATOMIC_TAS_1 #define MAYBE_HAVE_ATOMIC_TAS_2 HAVE_ATOMIC_TAS_2 #define MAYBE_HAVE_ATOMIC_TAS_4 HAVE_ATOMIC_TAS_4 #define MAYBE_HAVE_ATOMIC_TAS_8 HAVE_ATOMIC_TAS_8 # 32 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" 2 # 1 "/home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/gcc/include/stdbool.h" 1 3 4 # 29 "/home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/gcc/include/stdbool.h" 3 4 #define _STDBOOL_H #define bool _Bool #define true 1 #define false 0 # 52 "/home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/gcc/include/stdbool.h" 3 4 #define __bool_true_false_are_defined 1 # 33 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" 2 # 1 "/home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/gcc/include/stdint.h" 1 3 4 # 9 "/home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/gcc/include/stdint.h" 3 4 # 1 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/stdint.h" 1 3 4 # 23 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/stdint.h" 3 4 #define _STDINT_H 1 # 1 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/features.h" 1 3 4 # 19 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/features.h" 3 4 #define _FEATURES_H 1 # 97 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/features.h" 3 4 #undef __USE_ISOC11 #undef __USE_ISOC99 #undef __USE_ISOC95 #undef __USE_ISOCXX11 #undef __USE_POSIX #undef __USE_POSIX2 #undef __USE_POSIX199309 #undef __USE_POSIX199506 #undef __USE_XOPEN #undef __USE_XOPEN_EXTENDED #undef __USE_UNIX98 #undef __USE_XOPEN2K #undef __USE_XOPEN2KXSI #undef __USE_XOPEN2K8 #undef __USE_XOPEN2K8XSI #undef __USE_LARGEFILE #undef __USE_LARGEFILE64 #undef __USE_FILE_OFFSET64 #undef __USE_MISC #undef __USE_ATFILE #undef __USE_GNU #undef __USE_REENTRANT #undef __USE_FORTIFY_LEVEL #undef __KERNEL_STRICT_NAMES #define __KERNEL_STRICT_NAMES # 136 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/features.h" 3 4 #define __GNUC_PREREQ(maj,min) ((__GNUC__ << 16) + __GNUC_MINOR__ >= ((maj) << 16) + (min)) # 184 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/features.h" 3 4 #undef _DEFAULT_SOURCE #define _DEFAULT_SOURCE 1 #define __USE_ISOC11 1 #define __USE_ISOC99 1 #define __USE_ISOC95 1 # 220 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/features.h" 3 4 #define __USE_POSIX_IMPLICITLY 1 #undef _POSIX_SOURCE #define _POSIX_SOURCE 1 #undef _POSIX_C_SOURCE #define _POSIX_C_SOURCE 200809L # 243 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/features.h" 3 4 #define __USE_POSIX 1 #define __USE_POSIX2 1 #define __USE_POSIX199309 1 #define __USE_POSIX199506 1 #define __USE_XOPEN2K 1 #undef __USE_ISOC95 #define __USE_ISOC95 1 #undef __USE_ISOC99 #define __USE_ISOC99 1 #define __USE_XOPEN2K8 1 #undef _ATFILE_SOURCE #define _ATFILE_SOURCE 1 # 311 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/features.h" 3 4 #define __USE_MISC 1 #define __USE_ATFILE 1 #define __USE_REENTRANT 1 # 338 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/features.h" 3 4 #define __USE_FORTIFY_LEVEL 0 # 351 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/features.h" 3 4 #undef __GNU_LIBRARY__ #define __GNU_LIBRARY__ 6 #define __GLIBC__ 2 #define __GLIBC_MINOR__ 21 #define __GLIBC_PREREQ(maj,min) ((__GLIBC__ << 16) + __GLIBC_MINOR__ >= ((maj) << 16) + (min)) # 1 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/sys/cdefs.h" 1 3 4 # 19 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/sys/cdefs.h" 3 4 #define _SYS_CDEFS_H 1 # 34 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/sys/cdefs.h" 3 4 #undef __P #undef __PMT #define __LEAF , __leaf__ #define __LEAF_ATTR __attribute__ ((__leaf__)) # 55 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/sys/cdefs.h" 3 4 #define __THROW __attribute__ ((__nothrow__ __LEAF)) #define __THROWNL __attribute__ ((__nothrow__)) #define __NTH(fct) __attribute__ ((__nothrow__ __LEAF)) fct # 82 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/sys/cdefs.h" 3 4 #define __P(args) args #define __PMT(args) args #define __CONCAT(x,y) x ## y #define __STRING(x) #x #define __ptr_t void * #define __long_double_t long double #define __BEGIN_DECLS #define __END_DECLS # 122 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/sys/cdefs.h" 3 4 #define __BEGIN_NAMESPACE_STD #define __END_NAMESPACE_STD #define __USING_NAMESPACE_STD(name) #define __BEGIN_NAMESPACE_C99 #define __END_NAMESPACE_C99 #define __USING_NAMESPACE_C99(name) #define __bos(ptr) __builtin_object_size (ptr, __USE_FORTIFY_LEVEL > 1) #define __bos0(ptr) __builtin_object_size (ptr, 0) #define __warndecl(name,msg) extern void name (void) __attribute__((__warning__ (msg))) #define __warnattr(msg) __attribute__((__warning__ (msg))) #define __errordecl(name,msg) extern void name (void) __attribute__((__error__ (msg))) # 150 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/sys/cdefs.h" 3 4 #define __flexarr [] # 177 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/sys/cdefs.h" 3 4 #define __REDIRECT(name,proto,alias) name proto __asm__ (__ASMNAME (#alias)) #define __REDIRECT_NTH(name,proto,alias) name proto __asm__ (__ASMNAME (#alias)) __THROW #define __REDIRECT_NTHNL(name,proto,alias) name proto __asm__ (__ASMNAME (#alias)) __THROWNL #define __ASMNAME(cname) __ASMNAME2 (__USER_LABEL_PREFIX__, cname) #define __ASMNAME2(prefix,cname) __STRING (prefix) cname # 211 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/sys/cdefs.h" 3 4 #define __attribute_malloc__ __attribute__ ((__malloc__)) #define __attribute_alloc_size__(params) __attribute__ ((__alloc_size__ params)) # 229 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/sys/cdefs.h" 3 4 #define __attribute_pure__ __attribute__ ((__pure__)) #define __attribute_const__ __attribute__ ((__const__)) # 245 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/sys/cdefs.h" 3 4 #define __attribute_used__ __attribute__ ((__used__)) #define __attribute_noinline__ __attribute__ ((__noinline__)) #define __attribute_deprecated__ __attribute__ ((__deprecated__)) # 266 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/sys/cdefs.h" 3 4 #define __attribute_format_arg__(x) __attribute__ ((__format_arg__ (x))) # 276 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/sys/cdefs.h" 3 4 #define __attribute_format_strfmon__(a,b) __attribute__ ((__format__ (__strfmon__, a, b))) # 285 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/sys/cdefs.h" 3 4 #define __nonnull(params) __attribute__ ((__nonnull__ params)) #define __attribute_warn_unused_result__ __attribute__ ((__warn_unused_result__)) # 302 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/sys/cdefs.h" 3 4 #define __wur #define __always_inline __inline __attribute__ ((__always_inline__)) #define __attribute_artificial__ __attribute__ ((__artificial__)) # 333 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/sys/cdefs.h" 3 4 #define __extern_inline extern __inline __attribute__ ((__gnu_inline__)) #define __extern_always_inline extern __always_inline __attribute__ ((__gnu_inline__)) # 343 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/sys/cdefs.h" 3 4 #define __fortify_function __extern_always_inline __attribute_artificial__ #define __va_arg_pack() __builtin_va_arg_pack () #define __va_arg_pack_len() __builtin_va_arg_pack_len () # 370 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/sys/cdefs.h" 3 4 #define __restrict_arr __restrict # 385 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/sys/cdefs.h" 3 4 #define __glibc_unlikely(cond) __builtin_expect ((cond), 0) #define __glibc_likely(cond) __builtin_expect ((cond), 1) # 410 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/sys/cdefs.h" 3 4 # 1 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/wordsize.h" 1 3 4 # 18 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/wordsize.h" 3 4 #define __WORDSIZE 32 # 411 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/sys/cdefs.h" 2 3 4 # 432 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/sys/cdefs.h" 3 4 #define __LDBL_REDIR1(name,proto,alias) name proto #define __LDBL_REDIR(name,proto) name proto #define __LDBL_REDIR1_NTH(name,proto,alias) name proto __THROW #define __LDBL_REDIR_NTH(name,proto) name proto __THROW #define __LDBL_REDIR_DECL(name) #define __REDIRECT_LDBL(name,proto,alias) __REDIRECT (name, proto, alias) #define __REDIRECT_NTH_LDBL(name,proto,alias) __REDIRECT_NTH (name, proto, alias) # 366 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/features.h" 2 3 4 # 381 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/features.h" 3 4 #define __USE_EXTERN_INLINES 1 # 1 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/gnu/stubs.h" 1 3 4 # 10 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/gnu/stubs.h" 3 4 # 1 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/gnu/stubs-hard.h" 1 3 4 # 10 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/gnu/stubs-hard.h" 3 4 #define __stub_chflags #define __stub_create_module #define __stub_fattach #define __stub_fchflags #define __stub_fdetach #define __stub_get_kernel_syms #define __stub_getmsg #define __stub_getpmsg #define __stub_gtty #define __stub_lchmod #define __stub_putmsg #define __stub_putpmsg #define __stub_query_module #define __stub_revoke #define __stub_setlogin #define __stub_sigreturn #define __stub_sstk #define __stub_stty # 11 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/gnu/stubs.h" 2 3 4 # 390 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/features.h" 2 3 4 # 26 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/stdint.h" 2 3 4 # 1 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/wchar.h" 1 3 4 # 20 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/wchar.h" 3 4 #define _BITS_WCHAR_H 1 # 34 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/wchar.h" 3 4 #define __WCHAR_MAX __WCHAR_MAX__ #define __WCHAR_MIN __WCHAR_MIN__ # 27 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/stdint.h" 2 3 4 # 1 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/wordsize.h" 1 3 4 # 18 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/wordsize.h" 3 4 #define __WORDSIZE 32 # 28 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/stdint.h" 2 3 4 #define __int8_t_defined # 36 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/stdint.h" 3 4 typedef signed char int8_t; typedef short int int16_t; typedef int int32_t; __extension__ typedef long long int int64_t; typedef unsigned char uint8_t; typedef unsigned short int uint16_t; typedef unsigned int uint32_t; #define __uint32_t_defined __extension__ typedef unsigned long long int uint64_t; typedef signed char int_least8_t; typedef short int int_least16_t; typedef int int_least32_t; __extension__ typedef long long int int_least64_t; typedef unsigned char uint_least8_t; typedef unsigned short int uint_least16_t; typedef unsigned int uint_least32_t; __extension__ typedef unsigned long long int uint_least64_t; typedef signed char int_fast8_t; typedef int int_fast16_t; typedef int int_fast32_t; __extension__ typedef long long int int_fast64_t; typedef unsigned char uint_fast8_t; typedef unsigned int uint_fast16_t; typedef unsigned int uint_fast32_t; __extension__ typedef unsigned long long int uint_fast64_t; # 125 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/stdint.h" 3 4 typedef int intptr_t; #define __intptr_t_defined typedef unsigned int uintptr_t; # 137 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/stdint.h" 3 4 __extension__ typedef long long int intmax_t; __extension__ typedef unsigned long long int uintmax_t; #define __INT64_C(c) c ## LL #define __UINT64_C(c) c ## ULL #define INT8_MIN (-128) #define INT16_MIN (-32767-1) #define INT32_MIN (-2147483647-1) #define INT64_MIN (-__INT64_C(9223372036854775807)-1) #define INT8_MAX (127) #define INT16_MAX (32767) #define INT32_MAX (2147483647) #define INT64_MAX (__INT64_C(9223372036854775807)) #define UINT8_MAX (255) #define UINT16_MAX (65535) #define UINT32_MAX (4294967295U) #define UINT64_MAX (__UINT64_C(18446744073709551615)) #define INT_LEAST8_MIN (-128) #define INT_LEAST16_MIN (-32767-1) #define INT_LEAST32_MIN (-2147483647-1) #define INT_LEAST64_MIN (-__INT64_C(9223372036854775807)-1) #define INT_LEAST8_MAX (127) #define INT_LEAST16_MAX (32767) #define INT_LEAST32_MAX (2147483647) #define INT_LEAST64_MAX (__INT64_C(9223372036854775807)) #define UINT_LEAST8_MAX (255) #define UINT_LEAST16_MAX (65535) #define UINT_LEAST32_MAX (4294967295U) #define UINT_LEAST64_MAX (__UINT64_C(18446744073709551615)) #define INT_FAST8_MIN (-128) #define INT_FAST16_MIN (-2147483647-1) #define INT_FAST32_MIN (-2147483647-1) #define INT_FAST64_MIN (-__INT64_C(9223372036854775807)-1) #define INT_FAST8_MAX (127) #define INT_FAST16_MAX (2147483647) #define INT_FAST32_MAX (2147483647) #define INT_FAST64_MAX (__INT64_C(9223372036854775807)) #define UINT_FAST8_MAX (255) #define UINT_FAST16_MAX (4294967295U) #define UINT_FAST32_MAX (4294967295U) #define UINT_FAST64_MAX (__UINT64_C(18446744073709551615)) # 229 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/stdint.h" 3 4 #define INTPTR_MIN (-2147483647-1) #define INTPTR_MAX (2147483647) #define UINTPTR_MAX (4294967295U) #define INTMAX_MIN (-__INT64_C(9223372036854775807)-1) #define INTMAX_MAX (__INT64_C(9223372036854775807)) #define UINTMAX_MAX (__UINT64_C(18446744073709551615)) # 251 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/stdint.h" 3 4 #define PTRDIFF_MIN (-2147483647-1) #define PTRDIFF_MAX (2147483647) #define SIG_ATOMIC_MIN (-2147483647-1) #define SIG_ATOMIC_MAX (2147483647) # 266 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/stdint.h" 3 4 #define SIZE_MAX (4294967295U) #define WCHAR_MIN __WCHAR_MIN #define WCHAR_MAX __WCHAR_MAX #define WINT_MIN (0u) #define WINT_MAX (4294967295u) #define INT8_C(c) c #define INT16_C(c) c #define INT32_C(c) c #define INT64_C(c) c ## LL #define UINT8_C(c) c #define UINT16_C(c) c #define UINT32_C(c) c ## U #define UINT64_C(c) c ## ULL #define INTMAX_C(c) c ## LL #define UINTMAX_C(c) c ## ULL # 10 "/home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/gcc/include/stdint.h" 2 3 4 #define _GCC_WRAP_STDINT_H # 34 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" 2 # 1 "/home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/gcc/include/stddef.h" 1 3 4 # 39 "/home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/gcc/include/stddef.h" 3 4 #define _STDDEF_H #define _STDDEF_H_ #define _ANSI_STDDEF_H # 137 "/home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/gcc/include/stddef.h" 3 4 #define _PTRDIFF_T #define _T_PTRDIFF_ #define _T_PTRDIFF #define __PTRDIFF_T #define _PTRDIFF_T_ #define _BSD_PTRDIFF_T_ #define ___int_ptrdiff_t_h #define _GCC_PTRDIFF_T #define _PTRDIFF_T_DECLARED typedef int ptrdiff_t; # 161 "/home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/gcc/include/stddef.h" 3 4 #undef __need_ptrdiff_t # 187 "/home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/gcc/include/stddef.h" 3 4 #define __size_t__ #define __SIZE_T__ #define _SIZE_T #define _SYS_SIZE_T_H #define _T_SIZE_ #define _T_SIZE #define __SIZE_T #define _SIZE_T_ #define _BSD_SIZE_T_ #define _SIZE_T_DEFINED_ #define _SIZE_T_DEFINED #define _BSD_SIZE_T_DEFINED_ #define _SIZE_T_DECLARED #define ___int_size_t_h #define _GCC_SIZE_T #define _SIZET_ #define __size_t typedef unsigned int size_t; # 238 "/home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/gcc/include/stddef.h" 3 4 #undef __need_size_t # 267 "/home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/gcc/include/stddef.h" 3 4 #define __wchar_t__ #define __WCHAR_T__ #define _WCHAR_T #define _T_WCHAR_ #define _T_WCHAR #define __WCHAR_T #define _WCHAR_T_ #define _BSD_WCHAR_T_ #define _WCHAR_T_DEFINED_ #define _WCHAR_T_DEFINED #define _WCHAR_T_H #define ___int_wchar_t_h #define __INT_WCHAR_T_H #define _GCC_WCHAR_T #define _WCHAR_T_DECLARED # 294 "/home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/gcc/include/stddef.h" 3 4 #undef _BSD_WCHAR_T_ # 328 "/home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/gcc/include/stddef.h" 3 4 typedef unsigned int wchar_t; # 347 "/home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/gcc/include/stddef.h" 3 4 #undef __need_wchar_t # 401 "/home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/gcc/include/stddef.h" 3 4 #undef NULL #define NULL ((void *)0) #undef __need_NULL #define offsetof(TYPE,MEMBER) __builtin_offsetof (TYPE, MEMBER) #define _GCC_MAX_ALIGN_T typedef struct { long long __max_align_ll __attribute__((__aligned__(__alignof__(long long)))); long double __max_align_ld __attribute__((__aligned__(__alignof__(long double)))); } max_align_t; # 35 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" 2 # 1 "/home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/gcc/include-fixed/limits.h" 1 3 4 # 30 "/home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/gcc/include-fixed/limits.h" 3 4 #define _GCC_LIMITS_H_ # 1 "/home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/gcc/include-fixed/syslimits.h" 1 3 4 #define _GCC_NEXT_LIMITS_H # 1 "/home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/gcc/include-fixed/limits.h" 1 3 4 # 168 "/home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/gcc/include-fixed/limits.h" 3 4 # 1 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/limits.h" 1 3 4 # 23 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/limits.h" 3 4 #define _LIBC_LIMITS_H_ 1 #define MB_LEN_MAX 16 # 131 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/limits.h" 3 4 #define LLONG_MIN (-LLONG_MAX-1) #define LLONG_MAX __LONG_LONG_MAX__ #define ULLONG_MAX (LLONG_MAX * 2ULL + 1) # 1 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/posix1_lim.h" 1 3 4 # 25 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/posix1_lim.h" 3 4 #define _BITS_POSIX1_LIM_H 1 #define _POSIX_AIO_LISTIO_MAX 2 #define _POSIX_AIO_MAX 1 #define _POSIX_ARG_MAX 4096 #define _POSIX_CHILD_MAX 25 #define _POSIX_DELAYTIMER_MAX 32 #define _POSIX_HOST_NAME_MAX 255 #define _POSIX_LINK_MAX 8 #define _POSIX_LOGIN_NAME_MAX 9 #define _POSIX_MAX_CANON 255 #define _POSIX_MAX_INPUT 255 #define _POSIX_MQ_OPEN_MAX 8 #define _POSIX_MQ_PRIO_MAX 32 #define _POSIX_NAME_MAX 14 #define _POSIX_NGROUPS_MAX 8 #define _POSIX_OPEN_MAX 20 # 96 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/posix1_lim.h" 3 4 #define _POSIX_PATH_MAX 256 #define _POSIX_PIPE_BUF 512 #define _POSIX_RE_DUP_MAX 255 #define _POSIX_RTSIG_MAX 8 #define _POSIX_SEM_NSEMS_MAX 256 #define _POSIX_SEM_VALUE_MAX 32767 #define _POSIX_SIGQUEUE_MAX 32 #define _POSIX_SSIZE_MAX 32767 #define _POSIX_STREAM_MAX 8 #define _POSIX_SYMLINK_MAX 255 #define _POSIX_SYMLOOP_MAX 8 #define _POSIX_TIMER_MAX 32 #define _POSIX_TTY_NAME_MAX 9 #define _POSIX_TZNAME_MAX 6 # 156 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/posix1_lim.h" 3 4 #define _POSIX_CLOCKRES_MIN 20000000 # 1 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/local_lim.h" 1 3 4 # 25 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/local_lim.h" 3 4 #define __undef_NR_OPEN #define __undef_LINK_MAX #define __undef_OPEN_MAX #define __undef_ARG_MAX # 1 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/linux/limits.h" 1 3 4 #define _LINUX_LIMITS_H #define NR_OPEN 1024 #define NGROUPS_MAX 65536 #define ARG_MAX 131072 #define LINK_MAX 127 #define MAX_CANON 255 #define MAX_INPUT 255 #define NAME_MAX 255 #define PATH_MAX 4096 #define PIPE_BUF 4096 #define XATTR_NAME_MAX 255 #define XATTR_SIZE_MAX 65536 #define XATTR_LIST_MAX 65536 #define RTSIG_MAX 32 # 39 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/local_lim.h" 2 3 4 #undef NR_OPEN #undef __undef_NR_OPEN #undef LINK_MAX #undef __undef_LINK_MAX #undef OPEN_MAX #undef __undef_OPEN_MAX #undef ARG_MAX #undef __undef_ARG_MAX #define _POSIX_THREAD_KEYS_MAX 128 #define PTHREAD_KEYS_MAX 1024 #define _POSIX_THREAD_DESTRUCTOR_ITERATIONS 4 #define PTHREAD_DESTRUCTOR_ITERATIONS _POSIX_THREAD_DESTRUCTOR_ITERATIONS #define _POSIX_THREAD_THREADS_MAX 64 #undef PTHREAD_THREADS_MAX #define AIO_PRIO_DELTA_MAX 20 # 90 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/local_lim.h" 3 4 #define PTHREAD_STACK_MIN 131072 #define DELAYTIMER_MAX 2147483647 #define TTY_NAME_MAX 32 #define LOGIN_NAME_MAX 256 #define HOST_NAME_MAX 64 #define MQ_PRIO_MAX 32768 #define SEM_VALUE_MAX (2147483647) # 161 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/posix1_lim.h" 2 3 4 #define SSIZE_MAX LONG_MAX # 144 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/limits.h" 2 3 4 # 1 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/posix2_lim.h" 1 3 4 # 23 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/posix2_lim.h" 3 4 #define _BITS_POSIX2_LIM_H 1 #define _POSIX2_BC_BASE_MAX 99 #define _POSIX2_BC_DIM_MAX 2048 #define _POSIX2_BC_SCALE_MAX 99 #define _POSIX2_BC_STRING_MAX 1000 #define _POSIX2_COLL_WEIGHTS_MAX 2 #define _POSIX2_EXPR_NEST_MAX 32 #define _POSIX2_LINE_MAX 2048 #define _POSIX2_RE_DUP_MAX 255 #define _POSIX2_CHARCLASS_NAME_MAX 14 #define BC_BASE_MAX _POSIX2_BC_BASE_MAX #define BC_DIM_MAX _POSIX2_BC_DIM_MAX #define BC_SCALE_MAX _POSIX2_BC_SCALE_MAX #define BC_STRING_MAX _POSIX2_BC_STRING_MAX #define COLL_WEIGHTS_MAX 255 #define EXPR_NEST_MAX _POSIX2_EXPR_NEST_MAX #define LINE_MAX _POSIX2_LINE_MAX #define CHARCLASS_NAME_MAX 2048 #define RE_DUP_MAX (0x7fff) # 148 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/limits.h" 2 3 4 # 169 "/home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/gcc/include-fixed/limits.h" 2 3 4 # 8 "/home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/gcc/include-fixed/syslimits.h" 2 3 4 #undef _GCC_NEXT_LIMITS_H # 35 "/home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/gcc/include-fixed/limits.h" 2 3 4 # 60 "/home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/gcc/include-fixed/limits.h" 3 4 #define _LIMITS_H___ #undef CHAR_BIT #define CHAR_BIT __CHAR_BIT__ #undef SCHAR_MIN #define SCHAR_MIN (-SCHAR_MAX - 1) #undef SCHAR_MAX #define SCHAR_MAX __SCHAR_MAX__ #undef UCHAR_MAX #define UCHAR_MAX (SCHAR_MAX * 2 + 1) #undef CHAR_MIN #define CHAR_MIN 0 #undef CHAR_MAX #define CHAR_MAX UCHAR_MAX # 103 "/home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/gcc/include-fixed/limits.h" 3 4 #undef SHRT_MIN #define SHRT_MIN (-SHRT_MAX - 1) #undef SHRT_MAX #define SHRT_MAX __SHRT_MAX__ #undef USHRT_MAX #define USHRT_MAX (SHRT_MAX * 2 + 1) #undef INT_MIN #define INT_MIN (-INT_MAX - 1) #undef INT_MAX #define INT_MAX __INT_MAX__ #undef UINT_MAX #define UINT_MAX (INT_MAX * 2U + 1U) #undef LONG_MIN #define LONG_MIN (-LONG_MAX - 1L) #undef LONG_MAX #define LONG_MAX __LONG_MAX__ #undef ULONG_MAX #define ULONG_MAX (LONG_MAX * 2UL + 1UL) #undef LLONG_MIN #define LLONG_MIN (-LLONG_MAX - 1LL) #undef LLONG_MAX #define LLONG_MAX __LONG_LONG_MAX__ #undef ULLONG_MAX #define ULLONG_MAX (LLONG_MAX * 2ULL + 1ULL) # 36 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" 2 # 1 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/string.h" 1 3 4 # 23 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/string.h" 3 4 #define _STRING_H 1 #define __need_size_t #define __need_NULL # 1 "/home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/gcc/include/stddef.h" 1 3 4 # 161 "/home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/gcc/include/stddef.h" 3 4 #undef __need_ptrdiff_t # 238 "/home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/gcc/include/stddef.h" 3 4 #undef __need_size_t # 347 "/home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/gcc/include/stddef.h" 3 4 #undef __need_wchar_t # 401 "/home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/gcc/include/stddef.h" 3 4 #undef NULL #define NULL ((void *)0) #undef __need_NULL #define offsetof(TYPE,MEMBER) __builtin_offsetof (TYPE, MEMBER) # 33 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/string.h" 2 3 4 extern void *memcpy (void *__restrict __dest, const void *__restrict __src, size_t __n) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__nonnull__ (1, 2))); extern void *memmove (void *__dest, const void *__src, size_t __n) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__nonnull__ (1, 2))); extern void *memccpy (void *__restrict __dest, const void *__restrict __src, int __c, size_t __n) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__nonnull__ (1, 2))); extern void *memset (void *__s, int __c, size_t __n) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__nonnull__ (1))); extern int memcmp (const void *__s1, const void *__s2, size_t __n) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__pure__)) __attribute__ ((__nonnull__ (1, 2))); # 92 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/string.h" 3 4 extern void *memchr (const void *__s, int __c, size_t __n) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__pure__)) __attribute__ ((__nonnull__ (1))); # 123 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/string.h" 3 4 extern char *strcpy (char *__restrict __dest, const char *__restrict __src) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__nonnull__ (1, 2))); extern char *strncpy (char *__restrict __dest, const char *__restrict __src, size_t __n) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__nonnull__ (1, 2))); extern char *strcat (char *__restrict __dest, const char *__restrict __src) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__nonnull__ (1, 2))); extern char *strncat (char *__restrict __dest, const char *__restrict __src, size_t __n) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__nonnull__ (1, 2))); extern int strcmp (const char *__s1, const char *__s2) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__pure__)) __attribute__ ((__nonnull__ (1, 2))); extern int strncmp (const char *__s1, const char *__s2, size_t __n) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__pure__)) __attribute__ ((__nonnull__ (1, 2))); extern int strcoll (const char *__s1, const char *__s2) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__pure__)) __attribute__ ((__nonnull__ (1, 2))); extern size_t strxfrm (char *__restrict __dest, const char *__restrict __src, size_t __n) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__nonnull__ (2))); # 1 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/xlocale.h" 1 3 4 # 21 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/xlocale.h" 3 4 #define _XLOCALE_H 1 typedef struct __locale_struct { struct __locale_data *__locales[13]; const unsigned short int *__ctype_b; const int *__ctype_tolower; const int *__ctype_toupper; const char *__names[13]; } *__locale_t; typedef __locale_t locale_t; # 160 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/string.h" 2 3 4 extern int strcoll_l (const char *__s1, const char *__s2, __locale_t __l) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__pure__)) __attribute__ ((__nonnull__ (1, 2, 3))); extern size_t strxfrm_l (char *__dest, const char *__src, size_t __n, __locale_t __l) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__nonnull__ (2, 4))); extern char *strdup (const char *__s) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__malloc__)) __attribute__ ((__nonnull__ (1))); extern char *strndup (const char *__string, size_t __n) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__malloc__)) __attribute__ ((__nonnull__ (1))); # 206 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/string.h" 3 4 # 231 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/string.h" 3 4 extern char *strchr (const char *__s, int __c) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__pure__)) __attribute__ ((__nonnull__ (1))); # 258 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/string.h" 3 4 extern char *strrchr (const char *__s, int __c) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__pure__)) __attribute__ ((__nonnull__ (1))); # 277 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/string.h" 3 4 extern size_t strcspn (const char *__s, const char *__reject) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__pure__)) __attribute__ ((__nonnull__ (1, 2))); extern size_t strspn (const char *__s, const char *__accept) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__pure__)) __attribute__ ((__nonnull__ (1, 2))); # 310 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/string.h" 3 4 extern char *strpbrk (const char *__s, const char *__accept) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__pure__)) __attribute__ ((__nonnull__ (1, 2))); # 337 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/string.h" 3 4 extern char *strstr (const char *__haystack, const char *__needle) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__pure__)) __attribute__ ((__nonnull__ (1, 2))); extern char *strtok (char *__restrict __s, const char *__restrict __delim) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__nonnull__ (2))); extern char *__strtok_r (char *__restrict __s, const char *__restrict __delim, char **__restrict __save_ptr) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__nonnull__ (2, 3))); extern char *strtok_r (char *__restrict __s, const char *__restrict __delim, char **__restrict __save_ptr) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__nonnull__ (2, 3))); # 392 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/string.h" 3 4 extern size_t strlen (const char *__s) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__pure__)) __attribute__ ((__nonnull__ (1))); extern size_t strnlen (const char *__string, size_t __maxlen) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__pure__)) __attribute__ ((__nonnull__ (1))); extern char *strerror (int __errnum) __attribute__ ((__nothrow__ , __leaf__)); # 422 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/string.h" 3 4 extern int strerror_r (int __errnum, char *__buf, size_t __buflen) __asm__ ("" "__xpg_strerror_r") __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__nonnull__ (2))); # 440 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/string.h" 3 4 extern char *strerror_l (int __errnum, __locale_t __l) __attribute__ ((__nothrow__ , __leaf__)); extern void __bzero (void *__s, size_t __n) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__nonnull__ (1))); extern void bcopy (const void *__src, void *__dest, size_t __n) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__nonnull__ (1, 2))); extern void bzero (void *__s, size_t __n) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__nonnull__ (1))); extern int bcmp (const void *__s1, const void *__s2, size_t __n) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__pure__)) __attribute__ ((__nonnull__ (1, 2))); # 484 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/string.h" 3 4 extern char *index (const char *__s, int __c) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__pure__)) __attribute__ ((__nonnull__ (1))); # 512 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/string.h" 3 4 extern char *rindex (const char *__s, int __c) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__pure__)) __attribute__ ((__nonnull__ (1))); extern int ffs (int __i) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__const__)); # 529 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/string.h" 3 4 extern int strcasecmp (const char *__s1, const char *__s2) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__pure__)) __attribute__ ((__nonnull__ (1, 2))); extern int strncasecmp (const char *__s1, const char *__s2, size_t __n) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__pure__)) __attribute__ ((__nonnull__ (1, 2))); # 552 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/string.h" 3 4 extern char *strsep (char **__restrict __stringp, const char *__restrict __delim) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__nonnull__ (1, 2))); extern char *strsignal (int __sig) __attribute__ ((__nothrow__ , __leaf__)); extern char *__stpcpy (char *__restrict __dest, const char *__restrict __src) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__nonnull__ (1, 2))); extern char *stpcpy (char *__restrict __dest, const char *__restrict __src) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__nonnull__ (1, 2))); extern char *__stpncpy (char *__restrict __dest, const char *__restrict __src, size_t __n) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__nonnull__ (1, 2))); extern char *stpncpy (char *__restrict __dest, const char *__restrict __src, size_t __n) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__nonnull__ (1, 2))); # 627 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/string.h" 3 4 # 1 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/string.h" 1 3 4 # 9 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/string.h" 3 4 #define _BITS_STRING_H 1 #define _STRING_ARCH_unaligned 0 # 628 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/string.h" 2 3 4 # 1 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/string2.h" 1 3 4 # 45 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/string2.h" 3 4 #define __STRING_INLINE __extern_inline # 76 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/string2.h" 3 4 #define __STRING2_COPY_TYPE(N) typedef struct { unsigned char __arr[N]; } __attribute__ ((__packed__)) __STRING2_COPY_ARR ##N typedef struct { unsigned char __arr[2]; } __attribute__ ((__packed__)) __STRING2_COPY_ARR2; typedef struct { unsigned char __arr[3]; } __attribute__ ((__packed__)) __STRING2_COPY_ARR3; typedef struct { unsigned char __arr[4]; } __attribute__ ((__packed__)) __STRING2_COPY_ARR4; typedef struct { unsigned char __arr[5]; } __attribute__ ((__packed__)) __STRING2_COPY_ARR5; typedef struct { unsigned char __arr[6]; } __attribute__ ((__packed__)) __STRING2_COPY_ARR6; typedef struct { unsigned char __arr[7]; } __attribute__ ((__packed__)) __STRING2_COPY_ARR7; typedef struct { unsigned char __arr[8]; } __attribute__ ((__packed__)) __STRING2_COPY_ARR8; #undef __STRING2_COPY_TYPE #define __string2_1bptr_p(__x) ((size_t)(const void *)((__x) + 1) - (size_t)(const void *)(__x) == 1) # 194 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/string2.h" 3 4 #define __bzero(s,n) __builtin_memset (s, '\0', n) # 393 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/string2.h" 3 4 extern void *__rawmemchr (const void *__s, int __c); #define strchr(s,c) (__extension__ (__builtin_constant_p (c) && !__builtin_constant_p (s) && (c) == '\0' ? (char *) __rawmemchr (s, c) : __builtin_strchr (s, c))) # 760 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/string2.h" 3 4 #define strncpy(dest,src,n) __builtin_strncpy (dest, src, n) # 784 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/string2.h" 3 4 #define strncat(dest,src,n) __builtin_strncat (dest, src, n) # 799 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/string2.h" 3 4 #define strcmp(s1,s2) __extension__ ({ size_t __s1_len, __s2_len; (__builtin_constant_p (s1) && __builtin_constant_p (s2) && (__s1_len = strlen (s1), __s2_len = strlen (s2), (!__string2_1bptr_p (s1) || __s1_len >= 4) && (!__string2_1bptr_p (s2) || __s2_len >= 4)) ? __builtin_strcmp (s1, s2) : (__builtin_constant_p (s1) && __string2_1bptr_p (s1) && (__s1_len = strlen (s1), __s1_len < 4) ? (__builtin_constant_p (s2) && __string2_1bptr_p (s2) ? __builtin_strcmp (s1, s2) : __strcmp_cg (s1, s2, __s1_len)) : (__builtin_constant_p (s2) && __string2_1bptr_p (s2) && (__s2_len = strlen (s2), __s2_len < 4) ? (__builtin_constant_p (s1) && __string2_1bptr_p (s1) ? __builtin_strcmp (s1, s2) : __strcmp_gc (s1, s2, __s2_len)) : __builtin_strcmp (s1, s2)))); }) # 841 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/string2.h" 3 4 #define __strcmp_cc(s1,s2,l) (__extension__ ({ int __result = (((const unsigned char *) (const char *) (s1))[0] - ((const unsigned char *) (const char *)(s2))[0]); if (l > 0 && __result == 0) { __result = (((const unsigned char *) (const char *) (s1))[1] - ((const unsigned char *) (const char *) (s2))[1]); if (l > 1 && __result == 0) { __result = (((const unsigned char *) (const char *) (s1))[2] - ((const unsigned char *) (const char *) (s2))[2]); if (l > 2 && __result == 0) __result = (((const unsigned char *) (const char *) (s1))[3] - ((const unsigned char *) (const char *) (s2))[3]); } } __result; })) # 868 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/string2.h" 3 4 #define __strcmp_cg(s1,s2,l1) (__extension__ ({ const unsigned char *__s2 = (const unsigned char *) (const char *) (s2); int __result = (((const unsigned char *) (const char *) (s1))[0] - __s2[0]); if (l1 > 0 && __result == 0) { __result = (((const unsigned char *) (const char *) (s1))[1] - __s2[1]); if (l1 > 1 && __result == 0) { __result = (((const unsigned char *) (const char *) (s1))[2] - __s2[2]); if (l1 > 2 && __result == 0) __result = (((const unsigned char *) (const char *) (s1))[3] - __s2[3]); } } __result; })) # 890 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/string2.h" 3 4 #define __strcmp_gc(s1,s2,l2) (- __strcmp_cg (s2, s1, l2)) #define strncmp(s1,s2,n) (__extension__ (__builtin_constant_p (n) && ((__builtin_constant_p (s1) && strlen (s1) < ((size_t) (n))) || (__builtin_constant_p (s2) && strlen (s2) < ((size_t) (n)))) ? strcmp (s1, s2) : strncmp (s1, s2, n))) # 911 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/string2.h" 3 4 #define strcspn(s,reject) __extension__ ({ char __r0, __r1, __r2; (__builtin_constant_p (reject) && __string2_1bptr_p (reject) ? ((__builtin_constant_p (s) && __string2_1bptr_p (s)) ? __builtin_strcspn (s, reject) : ((__r0 = ((const char *) (reject))[0], __r0 == '\0') ? strlen (s) : ((__r1 = ((const char *) (reject))[1], __r1 == '\0') ? __strcspn_c1 (s, __r0) : ((__r2 = ((const char *) (reject))[2], __r2 == '\0') ? __strcspn_c2 (s, __r0, __r1) : (((const char *) (reject))[3] == '\0' ? __strcspn_c3 (s, __r0, __r1, __r2) : __builtin_strcspn (s, reject)))))) : __builtin_strcspn (s, reject)); }) # 945 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/string2.h" 3 4 extern __inline __attribute__ ((__gnu_inline__)) size_t __strcspn_c1 (const char *__s, int __reject); extern __inline __attribute__ ((__gnu_inline__)) size_t __strcspn_c1 (const char *__s, int __reject) { size_t __result = 0; while (__s[__result] != '\0' && __s[__result] != __reject) ++__result; return __result; } extern __inline __attribute__ ((__gnu_inline__)) size_t __strcspn_c2 (const char *__s, int __reject1, int __reject2); extern __inline __attribute__ ((__gnu_inline__)) size_t __strcspn_c2 (const char *__s, int __reject1, int __reject2) { size_t __result = 0; while (__s[__result] != '\0' && __s[__result] != __reject1 && __s[__result] != __reject2) ++__result; return __result; } extern __inline __attribute__ ((__gnu_inline__)) size_t __strcspn_c3 (const char *__s, int __reject1, int __reject2, int __reject3); extern __inline __attribute__ ((__gnu_inline__)) size_t __strcspn_c3 (const char *__s, int __reject1, int __reject2, int __reject3) { size_t __result = 0; while (__s[__result] != '\0' && __s[__result] != __reject1 && __s[__result] != __reject2 && __s[__result] != __reject3) ++__result; return __result; } # 987 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/string2.h" 3 4 #define strspn(s,accept) __extension__ ({ char __a0, __a1, __a2; (__builtin_constant_p (accept) && __string2_1bptr_p (accept) ? ((__builtin_constant_p (s) && __string2_1bptr_p (s)) ? __builtin_strspn (s, accept) : ((__a0 = ((const char *) (accept))[0], __a0 == '\0') ? ((void) (s), (size_t) 0) : ((__a1 = ((const char *) (accept))[1], __a1 == '\0') ? __strspn_c1 (s, __a0) : ((__a2 = ((const char *) (accept))[2], __a2 == '\0') ? __strspn_c2 (s, __a0, __a1) : (((const char *) (accept))[3] == '\0' ? __strspn_c3 (s, __a0, __a1, __a2) : __builtin_strspn (s, accept)))))) : __builtin_strspn (s, accept)); }) # 1021 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/string2.h" 3 4 extern __inline __attribute__ ((__gnu_inline__)) size_t __strspn_c1 (const char *__s, int __accept); extern __inline __attribute__ ((__gnu_inline__)) size_t __strspn_c1 (const char *__s, int __accept) { size_t __result = 0; while (__s[__result] == __accept) ++__result; return __result; } extern __inline __attribute__ ((__gnu_inline__)) size_t __strspn_c2 (const char *__s, int __accept1, int __accept2); extern __inline __attribute__ ((__gnu_inline__)) size_t __strspn_c2 (const char *__s, int __accept1, int __accept2) { size_t __result = 0; while (__s[__result] == __accept1 || __s[__result] == __accept2) ++__result; return __result; } extern __inline __attribute__ ((__gnu_inline__)) size_t __strspn_c3 (const char *__s, int __accept1, int __accept2, int __accept3); extern __inline __attribute__ ((__gnu_inline__)) size_t __strspn_c3 (const char *__s, int __accept1, int __accept2, int __accept3) { size_t __result = 0; while (__s[__result] == __accept1 || __s[__result] == __accept2 || __s[__result] == __accept3) ++__result; return __result; } #define strpbrk(s,accept) __extension__ ({ char __a0, __a1, __a2; (__builtin_constant_p (accept) && __string2_1bptr_p (accept) ? ((__builtin_constant_p (s) && __string2_1bptr_p (s)) ? __builtin_strpbrk (s, accept) : ((__a0 = ((const char *) (accept))[0], __a0 == '\0') ? ((void) (s), (char *) NULL) : ((__a1 = ((const char *) (accept))[1], __a1 == '\0') ? __builtin_strchr (s, __a0) : ((__a2 = ((const char *) (accept))[2], __a2 == '\0') ? __strpbrk_c2 (s, __a0, __a1) : (((const char *) (accept))[3] == '\0' ? __strpbrk_c3 (s, __a0, __a1, __a2) : __builtin_strpbrk (s, accept)))))) : __builtin_strpbrk (s, accept)); }) # 1097 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/string2.h" 3 4 extern __inline __attribute__ ((__gnu_inline__)) char *__strpbrk_c2 (const char *__s, int __accept1, int __accept2); extern __inline __attribute__ ((__gnu_inline__)) char * __strpbrk_c2 (const char *__s, int __accept1, int __accept2) { while (*__s != '\0' && *__s != __accept1 && *__s != __accept2) ++__s; return *__s == '\0' ? ((void *)0) : (char *) (size_t) __s; } extern __inline __attribute__ ((__gnu_inline__)) char *__strpbrk_c3 (const char *__s, int __accept1, int __accept2, int __accept3); extern __inline __attribute__ ((__gnu_inline__)) char * __strpbrk_c3 (const char *__s, int __accept1, int __accept2, int __accept3) { while (*__s != '\0' && *__s != __accept1 && *__s != __accept2 && *__s != __accept3) ++__s; return *__s == '\0' ? ((void *)0) : (char *) (size_t) __s; } # 1139 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/string2.h" 3 4 #define __strtok_r(s,sep,nextp) (__extension__ (__builtin_constant_p (sep) && __string2_1bptr_p (sep) && ((const char *) (sep))[0] != '\0' && ((const char *) (sep))[1] == '\0' ? __strtok_r_1c (s, ((const char *) (sep))[0], nextp) : __strtok_r (s, sep, nextp))) extern __inline __attribute__ ((__gnu_inline__)) char *__strtok_r_1c (char *__s, char __sep, char **__nextp); extern __inline __attribute__ ((__gnu_inline__)) char * __strtok_r_1c (char *__s, char __sep, char **__nextp) { char *__result; if (__s == ((void *)0)) __s = *__nextp; while (*__s == __sep) ++__s; __result = ((void *)0); if (*__s != '\0') { __result = __s++; while (*__s != '\0') if (*__s++ == __sep) { __s[-1] = '\0'; break; } } *__nextp = __s; return __result; } #define strtok_r(s,sep,nextp) __strtok_r (s, sep, nextp) extern char *__strsep_g (char **__stringp, const char *__delim); #define __strsep(s,reject) __extension__ ({ char __r0, __r1, __r2; (__builtin_constant_p (reject) && __string2_1bptr_p (reject) && (__r0 = ((const char *) (reject))[0], ((const char *) (reject))[0] != '\0') ? ((__r1 = ((const char *) (reject))[1], ((const char *) (reject))[1] == '\0') ? __strsep_1c (s, __r0) : ((__r2 = ((const char *) (reject))[2], __r2 == '\0') ? __strsep_2c (s, __r0, __r1) : (((const char *) (reject))[3] == '\0' ? __strsep_3c (s, __r0, __r1, __r2) : __strsep_g (s, reject)))) : __strsep_g (s, reject)); }) # 1197 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/string2.h" 3 4 extern __inline __attribute__ ((__gnu_inline__)) char *__strsep_1c (char **__s, char __reject); extern __inline __attribute__ ((__gnu_inline__)) char * __strsep_1c (char **__s, char __reject) { char *__retval = *__s; if (__retval != ((void *)0) && (*__s = (__extension__ (__builtin_constant_p (__reject) && !__builtin_constant_p (__retval) && (__reject) == '\0' ? (char *) __rawmemchr (__retval, __reject) : __builtin_strchr (__retval, __reject)))) != ((void *)0)) *(*__s)++ = '\0'; return __retval; } extern __inline __attribute__ ((__gnu_inline__)) char *__strsep_2c (char **__s, char __reject1, char __reject2); extern __inline __attribute__ ((__gnu_inline__)) char * __strsep_2c (char **__s, char __reject1, char __reject2) { char *__retval = *__s; if (__retval != ((void *)0)) { char *__cp = __retval; while (1) { if (*__cp == '\0') { __cp = ((void *)0); break; } if (*__cp == __reject1 || *__cp == __reject2) { *__cp++ = '\0'; break; } ++__cp; } *__s = __cp; } return __retval; } extern __inline __attribute__ ((__gnu_inline__)) char *__strsep_3c (char **__s, char __reject1, char __reject2, char __reject3); extern __inline __attribute__ ((__gnu_inline__)) char * __strsep_3c (char **__s, char __reject1, char __reject2, char __reject3) { char *__retval = *__s; if (__retval != ((void *)0)) { char *__cp = __retval; while (1) { if (*__cp == '\0') { __cp = ((void *)0); break; } if (*__cp == __reject1 || *__cp == __reject2 || *__cp == __reject3) { *__cp++ = '\0'; break; } ++__cp; } *__s = __cp; } return __retval; } #define strsep(s,reject) __strsep (s, reject) # 1272 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/string2.h" 3 4 #define __need_malloc_and_calloc # 1 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/stdlib.h" 1 3 4 # 27 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/stdlib.h" 3 4 #define __need_size_t # 1 "/home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/gcc/include/stddef.h" 1 3 4 # 161 "/home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/gcc/include/stddef.h" 3 4 #undef __need_ptrdiff_t # 238 "/home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/gcc/include/stddef.h" 3 4 #undef __need_size_t # 347 "/home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/gcc/include/stddef.h" 3 4 #undef __need_wchar_t # 401 "/home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/gcc/include/stddef.h" 3 4 #undef NULL #define NULL ((void *)0) #undef __need_NULL #define offsetof(TYPE,MEMBER) __builtin_offsetof (TYPE, MEMBER) # 33 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/stdlib.h" 2 3 4 # 463 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/stdlib.h" 3 4 #define __malloc_and_calloc_defined extern void *malloc (size_t __size) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__malloc__)) ; extern void *calloc (size_t __nmemb, size_t __size) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__malloc__)) ; # 965 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/stdlib.h" 3 4 #undef __need_malloc_and_calloc # 1274 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/string2.h" 2 3 4 extern char *__strdup (const char *__string) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__malloc__)); #define __strdup(s) (__extension__ (__builtin_constant_p (s) && __string2_1bptr_p (s) ? (((const char *) (s))[0] == '\0' ? (char *) calloc ((size_t) 1, (size_t) 1) : ({ size_t __len = strlen (s) + 1; char *__retval = (char *) malloc (__len); if (__retval != NULL) __retval = (char *) memcpy (__retval, s, __len); __retval; })) : __strdup (s))) # 1291 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/string2.h" 3 4 #define strdup(s) __strdup (s) extern char *__strndup (const char *__string, size_t __n) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__malloc__)); #define __strndup(s,n) (__extension__ (__builtin_constant_p (s) && __string2_1bptr_p (s) ? (((const char *) (s))[0] == '\0' ? (char *) calloc ((size_t) 1, (size_t) 1) : ({ size_t __len = strlen (s) + 1; size_t __n = (n); char *__retval; if (__n < __len) __len = __n + 1; __retval = (char *) malloc (__len); if (__retval != NULL) { __retval[__len - 1] = '\0'; __retval = (char *) memcpy (__retval, s, __len - 1); } __retval; })) : __strndup (s, n))) # 1319 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/bits/string2.h" 3 4 #define strndup(s,n) __strndup (s, n) #undef __STRING_INLINE # 631 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/string.h" 2 3 4 # 639 "/home/shivac/build-system-trunk/Release/install/armv8-marvell-linux-gnueabihf-hard-5.1.1_x86_64/arm-linux-gnueabihf/libc/usr/include/string.h" 3 4 # 37 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" 2 #define C2_(X,Y) X ## Y #define C2(X,Y) C2_(X,Y) #define C3_(X,Y,Z) X ## Y ## Z #define C3(X,Y,Z) C3_(X,Y,Z) #define C4_(W,X,Y,Z) W ## X ## Y ## Z #define C4(W,X,Y,Z) C4_(W,X,Y,Z) #define S2(X) #X #define S(X) S2(X) # 52 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" typedef unsigned U_1 __attribute__((mode(QI))); typedef unsigned U_2 __attribute__((mode(HI))); typedef unsigned U_4 __attribute__((mode(SI))); typedef unsigned U_8 __attribute__((mode(DI))); # 70 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" #define MAX_SIZE 8 typedef U_8 U_MAX; # 93 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" typedef U_MAX U_16; union max_size_u { U_1 b[8]; U_2 i2; U_4 i4; U_8 i8; U_16 i16; }; typedef unsigned UWORD __attribute__((mode(word))); #define MASK_1 ((UWORD)0xff) #define MASK_2 ((UWORD)0xffff) #define MASK_4 ((UWORD)0xffffffff) #define INVERT_MASK_1 ((UWORD)WORDS_BIGENDIAN << ((WORDSIZE - 1) * CHAR_BIT)) #define INVERT_MASK_2 ((UWORD)WORDS_BIGENDIAN << ((WORDSIZE - 2) * CHAR_BIT)) #define INVERT_MASK_4 ((UWORD)WORDS_BIGENDIAN << ((WORDSIZE - 4) * CHAR_BIT)) #define SIZE(X) C3(X,_,N) #define WSIZE(X) C3(X,_,WORDSIZE) #define PTR(N,X) ((C2(U_,N) *)X) #define ITYPE SIZE(I) #define UTYPE SIZE(U) #define UNUSED __attribute__((unused)) #define HIDDEN __attribute__((visibility("hidden"))) #define ASMNAME(X) __asm__(S(C2(__USER_LABEL_PREFIX__,X))) # 156 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" void libat_lock_n (void *ptr, size_t n); void libat_unlock_n (void *ptr, size_t n); #define DECLARE_ALL_SIZED(N) DECLARE_ALL_SIZED_(N,C2(U_,N)) #define DECLARE_ALL_SIZED_(N,T) DECLARE_1(T, C2(load_,N), (T *mptr, int)); DECLARE_1(void, C2(store_,N), (T *mptr, T val, int)); DECLARE_1(T, C2(exchange_,N), (T *mptr, T, int)); DECLARE_1(bool, C2(compare_exchange_,N), (T *mptr, T *, T, int, int)); DECLARE_1(bool, C2(test_and_set_,N), (T *mptr, int)); DECLARE_1(T, C2(fetch_add_,N), (T *mptr, T, int)); DECLARE_1(T, C2(fetch_sub_,N), (T *mptr, T, int)); DECLARE_1(T, C2(fetch_and_,N), (T *mptr, T, int)); DECLARE_1(T, C2(fetch_xor_,N), (T *mptr, T, int)); DECLARE_1(T, C2(fetch_or_,N), (T *mptr, T, int)); DECLARE_1(T, C2(fetch_nand_,N), (T *mptr, T, int)); DECLARE_1(T, C2(add_fetch_,N), (T *mptr, T, int)); DECLARE_1(T, C2(sub_fetch_,N), (T *mptr, T, int)); DECLARE_1(T, C2(and_fetch_,N), (T *mptr, T, int)); DECLARE_1(T, C2(xor_fetch_,N), (T *mptr, T, int)); DECLARE_1(T, C2(or_fetch_,N), (T *mptr, T, int)); DECLARE_1(T, C2(nand_fetch_,N), (T *mptr, T, int)) # 190 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" #define MAN(X) HIDDEN # 200 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" #define DECLARE_1(RET,NAME,ARGS) RET C2(libat_,NAME) ARGS MAN(NAME) #define local_ ifunc_ U_1 libat_load_1 (U_1 *mptr, int) __attribute__((visibility("hidden"))); void libat_store_1 (U_1 *mptr, U_1 val, int) __attribute__((visibility("hidden"))); U_1 libat_exchange_1 (U_1 *mptr, U_1, int) __attribute__((visibility("hidden"))); # 210 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" 3 4 _Bool # 210 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" libat_compare_exchange_1 (U_1 *mptr, U_1 *, U_1, int, int) __attribute__((visibility("hidden"))); # 210 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" 3 4 _Bool # 210 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" libat_test_and_set_1 (U_1 *mptr, int) __attribute__((visibility("hidden"))); U_1 libat_fetch_add_1 (U_1 *mptr, U_1, int) __attribute__((visibility("hidden"))); U_1 libat_fetch_sub_1 (U_1 *mptr, U_1, int) __attribute__((visibility("hidden"))); U_1 libat_fetch_and_1 (U_1 *mptr, U_1, int) __attribute__((visibility("hidden"))); U_1 libat_fetch_xor_1 (U_1 *mptr, U_1, int) __attribute__((visibility("hidden"))); U_1 libat_fetch_or_1 (U_1 *mptr, U_1, int) __attribute__((visibility("hidden"))); U_1 libat_fetch_nand_1 (U_1 *mptr, U_1, int) __attribute__((visibility("hidden"))); U_1 libat_add_fetch_1 (U_1 *mptr, U_1, int) __attribute__((visibility("hidden"))); U_1 libat_sub_fetch_1 (U_1 *mptr, U_1, int) __attribute__((visibility("hidden"))); U_1 libat_and_fetch_1 (U_1 *mptr, U_1, int) __attribute__((visibility("hidden"))); U_1 libat_xor_fetch_1 (U_1 *mptr, U_1, int) __attribute__((visibility("hidden"))); U_1 libat_or_fetch_1 (U_1 *mptr, U_1, int) __attribute__((visibility("hidden"))); U_1 libat_nand_fetch_1 (U_1 *mptr, U_1, int) __attribute__((visibility("hidden"))); U_2 libat_load_2 (U_2 *mptr, int) __attribute__((visibility("hidden"))); void libat_store_2 (U_2 *mptr, U_2 val, int) __attribute__((visibility("hidden"))); U_2 libat_exchange_2 (U_2 *mptr, U_2, int) __attribute__((visibility("hidden"))); # 211 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" 3 4 _Bool # 211 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" libat_compare_exchange_2 (U_2 *mptr, U_2 *, U_2, int, int) __attribute__((visibility("hidden"))); # 211 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" 3 4 _Bool # 211 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" libat_test_and_set_2 (U_2 *mptr, int) __attribute__((visibility("hidden"))); U_2 libat_fetch_add_2 (U_2 *mptr, U_2, int) __attribute__((visibility("hidden"))); U_2 libat_fetch_sub_2 (U_2 *mptr, U_2, int) __attribute__((visibility("hidden"))); U_2 libat_fetch_and_2 (U_2 *mptr, U_2, int) __attribute__((visibility("hidden"))); U_2 libat_fetch_xor_2 (U_2 *mptr, U_2, int) __attribute__((visibility("hidden"))); U_2 libat_fetch_or_2 (U_2 *mptr, U_2, int) __attribute__((visibility("hidden"))); U_2 libat_fetch_nand_2 (U_2 *mptr, U_2, int) __attribute__((visibility("hidden"))); U_2 libat_add_fetch_2 (U_2 *mptr, U_2, int) __attribute__((visibility("hidden"))); U_2 libat_sub_fetch_2 (U_2 *mptr, U_2, int) __attribute__((visibility("hidden"))); U_2 libat_and_fetch_2 (U_2 *mptr, U_2, int) __attribute__((visibility("hidden"))); U_2 libat_xor_fetch_2 (U_2 *mptr, U_2, int) __attribute__((visibility("hidden"))); U_2 libat_or_fetch_2 (U_2 *mptr, U_2, int) __attribute__((visibility("hidden"))); U_2 libat_nand_fetch_2 (U_2 *mptr, U_2, int) __attribute__((visibility("hidden"))); U_4 libat_load_4 (U_4 *mptr, int) __attribute__((visibility("hidden"))); void libat_store_4 (U_4 *mptr, U_4 val, int) __attribute__((visibility("hidden"))); U_4 libat_exchange_4 (U_4 *mptr, U_4, int) __attribute__((visibility("hidden"))); # 212 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" 3 4 _Bool # 212 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" libat_compare_exchange_4 (U_4 *mptr, U_4 *, U_4, int, int) __attribute__((visibility("hidden"))); # 212 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" 3 4 _Bool # 212 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" libat_test_and_set_4 (U_4 *mptr, int) __attribute__((visibility("hidden"))); U_4 libat_fetch_add_4 (U_4 *mptr, U_4, int) __attribute__((visibility("hidden"))); U_4 libat_fetch_sub_4 (U_4 *mptr, U_4, int) __attribute__((visibility("hidden"))); U_4 libat_fetch_and_4 (U_4 *mptr, U_4, int) __attribute__((visibility("hidden"))); U_4 libat_fetch_xor_4 (U_4 *mptr, U_4, int) __attribute__((visibility("hidden"))); U_4 libat_fetch_or_4 (U_4 *mptr, U_4, int) __attribute__((visibility("hidden"))); U_4 libat_fetch_nand_4 (U_4 *mptr, U_4, int) __attribute__((visibility("hidden"))); U_4 libat_add_fetch_4 (U_4 *mptr, U_4, int) __attribute__((visibility("hidden"))); U_4 libat_sub_fetch_4 (U_4 *mptr, U_4, int) __attribute__((visibility("hidden"))); U_4 libat_and_fetch_4 (U_4 *mptr, U_4, int) __attribute__((visibility("hidden"))); U_4 libat_xor_fetch_4 (U_4 *mptr, U_4, int) __attribute__((visibility("hidden"))); U_4 libat_or_fetch_4 (U_4 *mptr, U_4, int) __attribute__((visibility("hidden"))); U_4 libat_nand_fetch_4 (U_4 *mptr, U_4, int) __attribute__((visibility("hidden"))); U_8 libat_load_8 (U_8 *mptr, int) __attribute__((visibility("hidden"))); void libat_store_8 (U_8 *mptr, U_8 val, int) __attribute__((visibility("hidden"))); U_8 libat_exchange_8 (U_8 *mptr, U_8, int) __attribute__((visibility("hidden"))); # 213 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" 3 4 _Bool # 213 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" libat_compare_exchange_8 (U_8 *mptr, U_8 *, U_8, int, int) __attribute__((visibility("hidden"))); # 213 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" 3 4 _Bool # 213 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" libat_test_and_set_8 (U_8 *mptr, int) __attribute__((visibility("hidden"))); U_8 libat_fetch_add_8 (U_8 *mptr, U_8, int) __attribute__((visibility("hidden"))); U_8 libat_fetch_sub_8 (U_8 *mptr, U_8, int) __attribute__((visibility("hidden"))); U_8 libat_fetch_and_8 (U_8 *mptr, U_8, int) __attribute__((visibility("hidden"))); U_8 libat_fetch_xor_8 (U_8 *mptr, U_8, int) __attribute__((visibility("hidden"))); U_8 libat_fetch_or_8 (U_8 *mptr, U_8, int) __attribute__((visibility("hidden"))); U_8 libat_fetch_nand_8 (U_8 *mptr, U_8, int) __attribute__((visibility("hidden"))); U_8 libat_add_fetch_8 (U_8 *mptr, U_8, int) __attribute__((visibility("hidden"))); U_8 libat_sub_fetch_8 (U_8 *mptr, U_8, int) __attribute__((visibility("hidden"))); U_8 libat_and_fetch_8 (U_8 *mptr, U_8, int) __attribute__((visibility("hidden"))); U_8 libat_xor_fetch_8 (U_8 *mptr, U_8, int) __attribute__((visibility("hidden"))); U_8 libat_or_fetch_8 (U_8 *mptr, U_8, int) __attribute__((visibility("hidden"))); U_8 libat_nand_fetch_8 (U_8 *mptr, U_8, int) __attribute__((visibility("hidden"))); U_16 libat_load_16 (U_16 *mptr, int) __attribute__((visibility("hidden"))); void libat_store_16 (U_16 *mptr, U_16 val, int) __attribute__((visibility("hidden"))); U_16 libat_exchange_16 (U_16 *mptr, U_16, int) __attribute__((visibility("hidden"))); # 214 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" 3 4 _Bool # 214 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" libat_compare_exchange_16 (U_16 *mptr, U_16 *, U_16, int, int) __attribute__((visibility("hidden"))); # 214 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" 3 4 _Bool # 214 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" libat_test_and_set_16 (U_16 *mptr, int) __attribute__((visibility("hidden"))); U_16 libat_fetch_add_16 (U_16 *mptr, U_16, int) __attribute__((visibility("hidden"))); U_16 libat_fetch_sub_16 (U_16 *mptr, U_16, int) __attribute__((visibility("hidden"))); U_16 libat_fetch_and_16 (U_16 *mptr, U_16, int) __attribute__((visibility("hidden"))); U_16 libat_fetch_xor_16 (U_16 *mptr, U_16, int) __attribute__((visibility("hidden"))); U_16 libat_fetch_or_16 (U_16 *mptr, U_16, int) __attribute__((visibility("hidden"))); U_16 libat_fetch_nand_16 (U_16 *mptr, U_16, int) __attribute__((visibility("hidden"))); U_16 libat_add_fetch_16 (U_16 *mptr, U_16, int) __attribute__((visibility("hidden"))); U_16 libat_sub_fetch_16 (U_16 *mptr, U_16, int) __attribute__((visibility("hidden"))); U_16 libat_and_fetch_16 (U_16 *mptr, U_16, int) __attribute__((visibility("hidden"))); U_16 libat_xor_fetch_16 (U_16 *mptr, U_16, int) __attribute__((visibility("hidden"))); U_16 libat_or_fetch_16 (U_16 *mptr, U_16, int) __attribute__((visibility("hidden"))); U_16 libat_nand_fetch_16 (U_16 *mptr, U_16, int) __attribute__((visibility("hidden"))); #undef DECLARE_1 #undef DECLARE_ALL_SIZED #undef DECLARE_ALL_SIZED_ void libat_load (size_t, void *, void *, int) __attribute__((visibility("hidden"))); void libat_store (size_t, void *, void *, int) __attribute__((visibility("hidden"))); void libat_exchange (size_t, void *, void *, void *, int) __attribute__((visibility("hidden"))); # 224 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" 3 4 _Bool # 224 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" libat_compare_exchange (size_t, void *, void *, void *, int, int) __attribute__((visibility("hidden"))); # 226 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" 3 4 _Bool # 226 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" libat_is_lock_free (size_t, void *) __attribute__((visibility("hidden"))); #undef MAN # 1 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/config/arm/host-config.h" 1 #define WANT_SPECIALCASE_RELAXED # 1 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/config/linux/arm/host-config.h" 1 # 25 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/config/linux/arm/host-config.h" # 1 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/config/arm/arm-config.h" 1 # 61 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/config/arm/arm-config.h" #define __ARM_ARCH__ 8 #define HAVE_STREX 1 #define HAVE_STREXBHD 1 #define HAVE_DMB 1 # 26 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/config/linux/arm/host-config.h" 2 typedef int (__kernel_cmpxchg_t) (UWORD oldval, UWORD newval, UWORD *ptr); #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *) 0xffff0fc0) typedef int (__kernel_cmpxchg64_t) (const U_8 * oldval, const U_8 * newval, U_8 *ptr); #define __kernel_cmpxchg64 (*(__kernel_cmpxchg64_t *) 0xffff0f60) typedef void (__kernel_dmb_t) (void); #define __kernel_dmb (*(__kernel_dmb_t *) 0xffff0fa0) #define __kernel_helper_version (*(unsigned int *)0xffff0ffc) # 101 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/config/linux/arm/host-config.h" extern # 101 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/config/linux/arm/host-config.h" 3 4 _Bool # 101 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/config/linux/arm/host-config.h" libat_have_strexbhd __attribute__((visibility("hidden"))); #define IFUNC_COND_1 libat_have_strexbhd #define IFUNC_COND_2 (__kernel_helper_version >= 5) # 150 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/config/linux/arm/host-config.h" #undef MAYBE_HAVE_ATOMIC_CAS_1 #define MAYBE_HAVE_ATOMIC_CAS_1 IFUNC_COND_1 #undef MAYBE_HAVE_ATOMIC_EXCHANGE_1 #define MAYBE_HAVE_ATOMIC_EXCHANGE_1 MAYBE_HAVE_ATOMIC_CAS_1 #undef MAYBE_HAVE_ATOMIC_LDST_1 #define MAYBE_HAVE_ATOMIC_LDST_1 MAYBE_HAVE_ATOMIC_CAS_1 #undef MAYBE_HAVE_ATOMIC_CAS_2 #define MAYBE_HAVE_ATOMIC_CAS_2 IFUNC_COND_1 #undef MAYBE_HAVE_ATOMIC_EXCHANGE_2 #define MAYBE_HAVE_ATOMIC_EXCHANGE_2 MAYBE_HAVE_ATOMIC_CAS_2 #undef MAYBE_HAVE_ATOMIC_LDST_2 #define MAYBE_HAVE_ATOMIC_LDST_2 MAYBE_HAVE_ATOMIC_CAS_2 #undef MAYBE_HAVE_ATOMIC_CAS_4 #define MAYBE_HAVE_ATOMIC_CAS_4 IFUNC_COND_1 #undef MAYBE_HAVE_ATOMIC_EXCHANGE_4 #define MAYBE_HAVE_ATOMIC_EXCHANGE_4 MAYBE_HAVE_ATOMIC_CAS_4 #undef MAYBE_HAVE_ATOMIC_LDST_4 #define MAYBE_HAVE_ATOMIC_LDST_4 MAYBE_HAVE_ATOMIC_CAS_4 #undef MAYBE_HAVE_ATOMIC_CAS_8 #define MAYBE_HAVE_ATOMIC_CAS_8 (IFUNC_COND_1 | IFUNC_COND_2) #undef MAYBE_HAVE_ATOMIC_EXCHANGE_8 #define MAYBE_HAVE_ATOMIC_EXCHANGE_8 MAYBE_HAVE_ATOMIC_CAS_8 #undef MAYBE_HAVE_ATOMIC_LDST_8 #define MAYBE_HAVE_ATOMIC_LDST_8 MAYBE_HAVE_ATOMIC_CAS_8 #define IFUNC_NCOND(N) (N == 8 ? 2 : 1) # 1 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/config/posix/host-config.h" 1 # 30 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/config/posix/host-config.h" #pragma GCC visibility push(hidden) void libat_lock_1 (void *ptr); void libat_unlock_1 (void *ptr); static inline UWORD protect_start (void *ptr) { libat_lock_1 (ptr); return 0; } static inline void protect_end (void *ptr, UWORD dummy __attribute__((unused))) { libat_unlock_1 (ptr); } #define protect_start_end 1 #pragma GCC visibility pop # 1 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/host-config.h" 1 # 30 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/host-config.h" #define atomic_compare_exchange_n __atomic_compare_exchange_n #define atomic_compare_exchange_w __atomic_compare_exchange_n #define maybe_specialcase_relaxed(x) ((x) == __ATOMIC_RELAXED) # 50 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/host-config.h" #define maybe_specialcase_acqrel(x) ((x) & 0) static inline void __attribute__((always_inline, artificial)) pre_barrier(int model) { if (!((model) == 0)) { if (((model) & 0)) __atomic_thread_fence (4); else __atomic_thread_fence (5); } } static inline void __attribute__((always_inline, artificial)) post_barrier(int model) { pre_barrier(model); } #define pre_post_barrier 1 static inline void __attribute__((always_inline, artificial)) pre_seq_barrier(int model) { } static inline void __attribute__((always_inline, artificial)) post_seq_barrier(int model) { } #define pre_post_seq_barrier 1 # 55 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/config/posix/host-config.h" 2 # 179 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/config/linux/arm/host-config.h" 2 # 4 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/config/arm/host-config.h" 2 # 231 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" 2 # 241 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" #define GEN_SELECTOR(X) extern typeof(C2(libat_,X)) C3(libat_,X,_i1) HIDDEN; static void * C2(select_,X) (void) { if (IFUNC_COND_1) return C3(libat_,X,_i1); return C2(libat_,X); } # 279 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/libatomic_i.h" #define EXPORT_ALIAS(X) GEN_SELECTOR(X) typeof(C2(libat_,X)) C2(ifunc_,X) ASMNAME(C2(__atomic_,X)) __attribute__((ifunc(S(C2(select_,X))))) # 26 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/config/linux/arm/load_n.c" 2 # 49 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/config/linux/arm/load_n.c" # 1 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/config/linux/arm/../../../load_n.c" 1 # 25 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/config/linux/arm/../../../load_n.c" # 1 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/config/linux/arm/../../../libatomic_i.h" 1 # 26 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/config/linux/arm/../../../load_n.c" 2 U_1 libat_load_1 (U_1 *mptr, int smodel) { if (((smodel) == 0)) return __atomic_load_n (mptr, 0); else if (((smodel) & 0)) return __atomic_load_n (mptr, 2); else return __atomic_load_n (mptr, 5); } #define DONE 1 # 115 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/config/linux/arm/../../../load_n.c" extern typeof(libat_load_1) libat_load_1_i1 __attribute__((visibility("hidden"))); static void * select_load_1 (void) { if (libat_have_strexbhd) return libat_load_1_i1; return libat_load_1; } typeof(libat_load_1) ifunc_load_1 __asm__("__atomic_load_1") __attribute__((ifunc("select_load_1"))); # 49 "/home/shivac/build-system-trunk/src/gcc-src/libatomic/config/linux/arm/load_n.c" 2 [-- Attachment #3: test.c --] [-- Type: text/x-csrc, Size: 178 bytes --] struct backtrace_state { int threaded; int lock_alloc; }; void foo (struct backtrace_state *state) { if (state->threaded) __sync_lock_release (&state->lock_alloc); } ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code 2015-06-04 4:51 ` Shiva Chen @ 2015-06-04 8:24 ` Kyrill Tkachov 2015-06-04 8:42 ` Richard Earnshaw 0 siblings, 1 reply; 21+ messages in thread From: Kyrill Tkachov @ 2015-06-04 8:24 UTC (permalink / raw) To: Shiva Chen Cc: Ramana Radhakrishnan, GCC Patches, nickc, Richard Earnshaw, shivac Hi Shiva, On 04/06/15 04:13, Shiva Chen wrote: > Hi, Ramana > > Currently, I work for Marvell and the company have copyright assignment on file. > > Hi, all > > After adding the attribute and rebuild gcc, I got the assembler error message > > load_n.s:39: Error: bad instruction `ldrbeq r0,[r0]' > > When i look into armv8 ISA document, it seems ldrb Encoding A1 have > conditional code field. > > Does it mean we should also patch assembler or I just miss > understanding something ? > > Following command use to generate load_n.s: > > /home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/./gcc/cc1 > -fpreprocessed load_n.i -quiet -dumpbase load_n.c -march=armv8-a > -mfloat-abi=hard -mfpu=fp-armv8 -mtls-dialect=gnu -auxbase-strip > .libs/load_1_.o -g3 -O2 -Wall -Werror -version -fPIC -funwind-tables > -o load_n.s > > > The test.c is a simple test case to reproduce missing conditional code > in mmap.c. > > Any suggestion ? I reproduced the assembler failure with your patch. The reason is that for arm mode we use divided syntax, where the condition field goes in a different place. So, while ldrbeq r0,[r0] is rejected, ldreqb r0, [r0] works. Since we always use divided syntax for arm mode, I think you'll need to put the condition field in the right place depending on arm or thumb mode. Ugh, this is becoming ugly :( Kyrill > > > Shiva > > 2015-06-03 17:29 GMT+08:00 Shiva Chen <shiva0217@gmail.com>: >> Hi, Ramana >> >> I'm not sure what copyright assignment means ? >> >> Does it mean the patch have copyright assignment or not ? >> >> I update the patch to add "predicable" and "predicable_short_it" >> attribute as suggestion. >> >> However, I don't have svn write access yet. >> >> Shiva >> >> 2015-06-03 16:36 GMT+08:00 Kyrill Tkachov <kyrylo.tkachov@arm.com>: >>> On 03/06/15 09:32, Ramana Radhakrishnan wrote: >>>>> This pattern is not predicable though, i.e. it doesn't have the >>>>> "predicable" attribute set to "yes". >>>>> Therefore the compiler should be trying to branch around here rather than >>>>> try to do a cond_exec. >>>>> Why does the generated code above look like it's converted to conditional >>>>> execution? >>>>> Could you produce a self-contained reduced testcase for this? >>>> CCFSM state machine in ARM state. >>>> >>>> arm.c (final_prescan_insn). >>> >>> Ah ok. >>> This patch makes sense then. >>> As Ramana mentioned, please mark the pattern with "predicable" and also set >>> the "predicable_short_it" attribute to "no" so that it will not be >>> conditionalised in Thumb2 mode or when -mrestrict-it is enabled. >>> >>> Thanks, >>> Kyrill >>> >>> >>> >>>> Ramana >>>> >>>>> Thanks, >>>>> Kyrill >>>>> >>>>>> @@ -91,9 +91,9 @@ >>>>>> { >>>>>> enum memmodel model = memmodel_from_int (INTVAL (operands[2])); >>>>>> if (is_mm_relaxed (model) || is_mm_consume (model) || >>>>>> is_mm_acquire (model)) >>>>>> - return \"str<sync_sfx>\t%1, %0\"; >>>>>> + return \"str<sync_sfx>%?\t%1, %0\"; >>>>>> else >>>>>> - return \"stl<sync_sfx>\t%1, %0\"; >>>>>> + return \"stl<sync_sfx>%?\t%1, %0\"; >>>>>> } >>>>>> ) >>>>>> ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code 2015-06-04 8:24 ` Kyrill Tkachov @ 2015-06-04 8:42 ` Richard Earnshaw 2015-06-04 10:01 ` Shiva Chen 0 siblings, 1 reply; 21+ messages in thread From: Richard Earnshaw @ 2015-06-04 8:42 UTC (permalink / raw) To: Kyrill Tkachov, Shiva Chen Cc: Ramana Radhakrishnan, GCC Patches, nickc, shivac On 04/06/15 09:17, Kyrill Tkachov wrote: > Hi Shiva, > > On 04/06/15 04:13, Shiva Chen wrote: >> Hi, Ramana >> >> Currently, I work for Marvell and the company have copyright assignment on file. >> >> Hi, all >> >> After adding the attribute and rebuild gcc, I got the assembler error message >> >> load_n.s:39: Error: bad instruction `ldrbeq r0,[r0]' >> >> When i look into armv8 ISA document, it seems ldrb Encoding A1 have >> conditional code field. >> >> Does it mean we should also patch assembler or I just miss >> understanding something ? >> >> Following command use to generate load_n.s: >> >> /home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/./gcc/cc1 >> -fpreprocessed load_n.i -quiet -dumpbase load_n.c -march=armv8-a >> -mfloat-abi=hard -mfpu=fp-armv8 -mtls-dialect=gnu -auxbase-strip >> .libs/load_1_.o -g3 -O2 -Wall -Werror -version -fPIC -funwind-tables >> -o load_n.s >> >> >> The test.c is a simple test case to reproduce missing conditional code >> in mmap.c. >> >> Any suggestion ? > > I reproduced the assembler failure with your patch. > > The reason is that for arm mode we use divided syntax, where the condition field goes in a > different place. So, while ldrbeq r0,[r0] is rejected, ldreqb r0, [r0] works. > Since we always use divided syntax for arm mode, I think you'll need to put the condition field > in the right place depending on arm or thumb mode. > Ugh, this is becoming ugly :( > Use %(<suffix%) around the bit that changes for unified/divided syntax. The compiler will then put the condition in the correct place. So: + return \"str%(<sync_sfx>%)\t%1, %0\"; R. > Kyrill > >> >> >> Shiva >> >> 2015-06-03 17:29 GMT+08:00 Shiva Chen <shiva0217@gmail.com>: >>> Hi, Ramana >>> >>> I'm not sure what copyright assignment means ? >>> >>> Does it mean the patch have copyright assignment or not ? >>> >>> I update the patch to add "predicable" and "predicable_short_it" >>> attribute as suggestion. >>> >>> However, I don't have svn write access yet. >>> >>> Shiva >>> >>> 2015-06-03 16:36 GMT+08:00 Kyrill Tkachov <kyrylo.tkachov@arm.com>: >>>> On 03/06/15 09:32, Ramana Radhakrishnan wrote: >>>>>> This pattern is not predicable though, i.e. it doesn't have the >>>>>> "predicable" attribute set to "yes". >>>>>> Therefore the compiler should be trying to branch around here rather than >>>>>> try to do a cond_exec. >>>>>> Why does the generated code above look like it's converted to conditional >>>>>> execution? >>>>>> Could you produce a self-contained reduced testcase for this? >>>>> CCFSM state machine in ARM state. >>>>> >>>>> arm.c (final_prescan_insn). >>>> >>>> Ah ok. >>>> This patch makes sense then. >>>> As Ramana mentioned, please mark the pattern with "predicable" and also set >>>> the "predicable_short_it" attribute to "no" so that it will not be >>>> conditionalised in Thumb2 mode or when -mrestrict-it is enabled. >>>> >>>> Thanks, >>>> Kyrill >>>> >>>> >>>> >>>>> Ramana >>>>> >>>>>> Thanks, >>>>>> Kyrill >>>>>> >>>>>>> @@ -91,9 +91,9 @@ >>>>>>> { >>>>>>> enum memmodel model = memmodel_from_int (INTVAL (operands[2])); >>>>>>> if (is_mm_relaxed (model) || is_mm_consume (model) || >>>>>>> is_mm_acquire (model)) >>>>>>> - return \"str<sync_sfx>\t%1, %0\"; >>>>>>> + return \"str<sync_sfx>%?\t%1, %0\"; >>>>>>> else >>>>>>> - return \"stl<sync_sfx>\t%1, %0\"; >>>>>>> + return \"stl<sync_sfx>%?\t%1, %0\"; >>>>>>> } >>>>>>> ) >>>>>>> > ^ permalink raw reply [flat|nested] 21+ messages in thread
* RE: [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code 2015-06-04 8:42 ` Richard Earnshaw @ 2015-06-04 10:01 ` Shiva Chen 2015-06-04 10:04 ` Kyrill Tkachov 0 siblings, 1 reply; 21+ messages in thread From: Shiva Chen @ 2015-06-04 10:01 UTC (permalink / raw) To: Richard Earnshaw, Kyrill Tkachov, Shiva Chen Cc: Ramana Radhakrishnan, GCC Patches, nickc [-- Attachment #1: Type: text/plain, Size: 4859 bytes --] Hi, Kyrill Thanks for the tips of syntax. It seems that correct syntax for ldrb with condition code is ldreqb ldab with condition code is ldabeq So I modified the pattern as follow { enum memmodel model = (enum memmodel) INTVAL (operands[2]); if (model == MEMMODEL_RELAXED || model == MEMMODEL_CONSUME || model == MEMMODEL_RELEASE) return \"ldr%?<sync_sfx>\\t%0, %1\"; else return \"lda<sync_sfx>%?\\t%0, %1\"; } [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no")]) It seems we don't have to worry about thumb mode, Because we already set "predicable" "yes" and predicable_short_it" "no" for the pattern. The new patch could build gcc and run gcc regression test successfully. Please correct me if I still missing something. Thanks, Shiva -----Original Message----- From: Richard Earnshaw [mailto:Richard.Earnshaw@foss.arm.com] Sent: Thursday, June 04, 2015 4:42 PM To: Kyrill Tkachov; Shiva Chen Cc: Ramana Radhakrishnan; GCC Patches; nickc@redhat.com; Shiva Chen Subject: Re: [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code On 04/06/15 09:17, Kyrill Tkachov wrote: > Hi Shiva, > > On 04/06/15 04:13, Shiva Chen wrote: >> Hi, Ramana >> >> Currently, I work for Marvell and the company have copyright assignment on file. >> >> Hi, all >> >> After adding the attribute and rebuild gcc, I got the assembler error >> message >> >> load_n.s:39: Error: bad instruction `ldrbeq r0,[r0]' >> >> When i look into armv8 ISA document, it seems ldrb Encoding A1 have >> conditional code field. >> >> Does it mean we should also patch assembler or I just miss >> understanding something ? >> >> Following command use to generate load_n.s: >> >> /home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnu >> eabihf-hard/gcc-final/./gcc/cc1 -fpreprocessed load_n.i -quiet >> -dumpbase load_n.c -march=armv8-a -mfloat-abi=hard -mfpu=fp-armv8 >> -mtls-dialect=gnu -auxbase-strip .libs/load_1_.o -g3 -O2 -Wall >> -Werror -version -fPIC -funwind-tables -o load_n.s >> >> >> The test.c is a simple test case to reproduce missing conditional >> code in mmap.c. >> >> Any suggestion ? > > I reproduced the assembler failure with your patch. > > The reason is that for arm mode we use divided syntax, where the > condition field goes in a different place. So, while ldrbeq r0,[r0] is rejected, ldreqb r0, [r0] works. > Since we always use divided syntax for arm mode, I think you'll need > to put the condition field in the right place depending on arm or thumb mode. > Ugh, this is becoming ugly :( > Use %(<suffix%) around the bit that changes for unified/divided syntax. The compiler will then put the condition in the correct place. So: + return \"str%(<sync_sfx>%)\t%1, %0\"; R. > Kyrill > >> >> >> Shiva >> >> 2015-06-03 17:29 GMT+08:00 Shiva Chen <shiva0217@gmail.com>: >>> Hi, Ramana >>> >>> I'm not sure what copyright assignment means ? >>> >>> Does it mean the patch have copyright assignment or not ? >>> >>> I update the patch to add "predicable" and "predicable_short_it" >>> attribute as suggestion. >>> >>> However, I don't have svn write access yet. >>> >>> Shiva >>> >>> 2015-06-03 16:36 GMT+08:00 Kyrill Tkachov <kyrylo.tkachov@arm.com>: >>>> On 03/06/15 09:32, Ramana Radhakrishnan wrote: >>>>>> This pattern is not predicable though, i.e. it doesn't have the >>>>>> "predicable" attribute set to "yes". >>>>>> Therefore the compiler should be trying to branch around here >>>>>> rather than try to do a cond_exec. >>>>>> Why does the generated code above look like it's converted to >>>>>> conditional execution? >>>>>> Could you produce a self-contained reduced testcase for this? >>>>> CCFSM state machine in ARM state. >>>>> >>>>> arm.c (final_prescan_insn). >>>> >>>> Ah ok. >>>> This patch makes sense then. >>>> As Ramana mentioned, please mark the pattern with "predicable" and >>>> also set the "predicable_short_it" attribute to "no" so that it >>>> will not be conditionalised in Thumb2 mode or when -mrestrict-it is enabled. >>>> >>>> Thanks, >>>> Kyrill >>>> >>>> >>>> >>>>> Ramana >>>>> >>>>>> Thanks, >>>>>> Kyrill >>>>>> >>>>>>> @@ -91,9 +91,9 @@ >>>>>>> { >>>>>>> enum memmodel model = memmodel_from_int (INTVAL (operands[2])); >>>>>>> if (is_mm_relaxed (model) || is_mm_consume (model) || >>>>>>> is_mm_acquire (model)) >>>>>>> - return \"str<sync_sfx>\t%1, %0\"; >>>>>>> + return \"str<sync_sfx>%?\t%1, %0\"; >>>>>>> else >>>>>>> - return \"stl<sync_sfx>\t%1, %0\"; >>>>>>> + return \"stl<sync_sfx>%?\t%1, %0\"; >>>>>>> } >>>>>>> ) >>>>>>> > [-- Attachment #2: Fix_slt_lda_missing_conditional_code.diff --] [-- Type: application/octet-stream, Size: 1274 bytes --] diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md index 44cda61..c89978a 100644 --- a/gcc/config/arm/sync.md +++ b/gcc/config/arm/sync.md @@ -75,11 +75,12 @@ { enum memmodel model = memmodel_from_int (INTVAL (operands[2])); if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_release (model)) - return \"ldr<sync_sfx>\\t%0, %1\"; + return \"ldr%?<sync_sfx>\\t%0, %1\"; else - return \"lda<sync_sfx>\\t%0, %1\"; + return \"lda<sync_sfx>%?\\t%0, %1\"; } -) + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no")]) (define_insn "atomic_store<mode>" [(set (match_operand:QHSI 0 "memory_operand" "=Q") @@ -91,11 +92,12 @@ { enum memmodel model = memmodel_from_int (INTVAL (operands[2])); if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_acquire (model)) - return \"str<sync_sfx>\t%1, %0\"; + return \"str%?<sync_sfx>\t%1, %0\"; else - return \"stl<sync_sfx>\t%1, %0\"; + return \"stl<sync_sfx>%?\t%1, %0\"; } -) + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no")]) ;; Note that ldrd and vldr are *not* guaranteed to be single-copy atomic, ;; even for a 64-bit aligned address. Instead we use a ldrexd unparied ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code 2015-06-04 10:01 ` Shiva Chen @ 2015-06-04 10:04 ` Kyrill Tkachov 2015-06-05 8:34 ` Shiva Chen 0 siblings, 1 reply; 21+ messages in thread From: Kyrill Tkachov @ 2015-06-04 10:04 UTC (permalink / raw) To: Shiva Chen, Richard Earnshaw, Shiva Chen Cc: Ramana Radhakrishnan, GCC Patches, nickc Hi Shiva, On 04/06/15 10:57, Shiva Chen wrote: > Hi, Kyrill > > Thanks for the tips of syntax. > > It seems that correct syntax for > > ldrb with condition code is ldreqb > > ldab with condition code is ldabeq > > > So I modified the pattern as follow > > { > enum memmodel model = (enum memmodel) INTVAL (operands[2]); > if (model == MEMMODEL_RELAXED > || model == MEMMODEL_CONSUME > || model == MEMMODEL_RELEASE) > return \"ldr%?<sync_sfx>\\t%0, %1\"; > else > return \"lda<sync_sfx>%?\\t%0, %1\"; > } > [(set_attr "predicable" "yes") > (set_attr "predicable_short_it" "no")]) > > It seems we don't have to worry about thumb mode, I suggest you use Richard's suggestion from: https://gcc.gnu.org/ml/gcc-patches/2015-06/msg00384.html to write this in a clean way. > > > Because we already set "predicable" "yes" and predicable_short_it" "no" for the pattern. That's not quite true. The user may compile for armv8-a with -mno-restrict-it which will turn off this restriction for Thumb and allow the conditional execution of this. In any case, I think Richard's suggestion above should work. Thanks, Kyrill > > The new patch could build gcc and run gcc regression test successfully. > > Please correct me if I still missing something. > > Thanks, > > Shiva > > -----Original Message----- > From: Richard Earnshaw [mailto:Richard.Earnshaw@foss.arm.com] > Sent: Thursday, June 04, 2015 4:42 PM > To: Kyrill Tkachov; Shiva Chen > Cc: Ramana Radhakrishnan; GCC Patches; nickc@redhat.com; Shiva Chen > Subject: Re: [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code > > On 04/06/15 09:17, Kyrill Tkachov wrote: >> Hi Shiva, >> >> On 04/06/15 04:13, Shiva Chen wrote: >>> Hi, Ramana >>> >>> Currently, I work for Marvell and the company have copyright assignment on file. >>> >>> Hi, all >>> >>> After adding the attribute and rebuild gcc, I got the assembler error >>> message >>> >>> load_n.s:39: Error: bad instruction `ldrbeq r0,[r0]' >>> >>> When i look into armv8 ISA document, it seems ldrb Encoding A1 have >>> conditional code field. >>> >>> Does it mean we should also patch assembler or I just miss >>> understanding something ? >>> >>> Following command use to generate load_n.s: >>> >>> /home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnu >>> eabihf-hard/gcc-final/./gcc/cc1 -fpreprocessed load_n.i -quiet >>> -dumpbase load_n.c -march=armv8-a -mfloat-abi=hard -mfpu=fp-armv8 >>> -mtls-dialect=gnu -auxbase-strip .libs/load_1_.o -g3 -O2 -Wall >>> -Werror -version -fPIC -funwind-tables -o load_n.s >>> >>> >>> The test.c is a simple test case to reproduce missing conditional >>> code in mmap.c. >>> >>> Any suggestion ? >> I reproduced the assembler failure with your patch. >> >> The reason is that for arm mode we use divided syntax, where the >> condition field goes in a different place. So, while ldrbeq r0,[r0] is rejected, ldreqb r0, [r0] works. >> Since we always use divided syntax for arm mode, I think you'll need >> to put the condition field in the right place depending on arm or thumb mode. >> Ugh, this is becoming ugly :( >> > Use %(<suffix%) around the bit that changes for unified/divided syntax. > The compiler will then put the condition in the correct place. > > So: > > + return \"str%(<sync_sfx>%)\t%1, %0\"; > > R. > >> Kyrill >> >>> >>> Shiva >>> >>> 2015-06-03 17:29 GMT+08:00 Shiva Chen <shiva0217@gmail.com>: >>>> Hi, Ramana >>>> >>>> I'm not sure what copyright assignment means ? >>>> >>>> Does it mean the patch have copyright assignment or not ? >>>> >>>> I update the patch to add "predicable" and "predicable_short_it" >>>> attribute as suggestion. >>>> >>>> However, I don't have svn write access yet. >>>> >>>> Shiva >>>> >>>> 2015-06-03 16:36 GMT+08:00 Kyrill Tkachov <kyrylo.tkachov@arm.com>: >>>>> On 03/06/15 09:32, Ramana Radhakrishnan wrote: >>>>>>> This pattern is not predicable though, i.e. it doesn't have the >>>>>>> "predicable" attribute set to "yes". >>>>>>> Therefore the compiler should be trying to branch around here >>>>>>> rather than try to do a cond_exec. >>>>>>> Why does the generated code above look like it's converted to >>>>>>> conditional execution? >>>>>>> Could you produce a self-contained reduced testcase for this? >>>>>> CCFSM state machine in ARM state. >>>>>> >>>>>> arm.c (final_prescan_insn). >>>>> Ah ok. >>>>> This patch makes sense then. >>>>> As Ramana mentioned, please mark the pattern with "predicable" and >>>>> also set the "predicable_short_it" attribute to "no" so that it >>>>> will not be conditionalised in Thumb2 mode or when -mrestrict-it is enabled. >>>>> >>>>> Thanks, >>>>> Kyrill >>>>> >>>>> >>>>> >>>>>> Ramana >>>>>> >>>>>>> Thanks, >>>>>>> Kyrill >>>>>>> >>>>>>>> @@ -91,9 +91,9 @@ >>>>>>>> { >>>>>>>> enum memmodel model = memmodel_from_int (INTVAL (operands[2])); >>>>>>>> if (is_mm_relaxed (model) || is_mm_consume (model) || >>>>>>>> is_mm_acquire (model)) >>>>>>>> - return \"str<sync_sfx>\t%1, %0\"; >>>>>>>> + return \"str<sync_sfx>%?\t%1, %0\"; >>>>>>>> else >>>>>>>> - return \"stl<sync_sfx>\t%1, %0\"; >>>>>>>> + return \"stl<sync_sfx>%?\t%1, %0\"; >>>>>>>> } >>>>>>>> ) >>>>>>>> ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code 2015-06-04 10:04 ` Kyrill Tkachov @ 2015-06-05 8:34 ` Shiva Chen 2015-06-05 8:35 ` Kyrill Tkachov 0 siblings, 1 reply; 21+ messages in thread From: Shiva Chen @ 2015-06-05 8:34 UTC (permalink / raw) To: Kyrill Tkachov Cc: Shiva Chen, Richard Earnshaw, Ramana Radhakrishnan, GCC Patches, nickc [-- Attachment #1: Type: text/plain, Size: 6759 bytes --] Hi, Kyrill I update the patch as Richard's suggestion. - return \"str<sync_sfx>\t%1, %0\"; + return \"str%(<sync_sfx>%)\t%1, %0\"; else - return \"stl<sync_sfx>\t%1, %0\"; + return \"stl<sync_sfx>%?\t%1, %0\"; } -) + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no")]) + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no")]) Let me sum up. We add predicable attribute to allow gcc do if-conversion in ce1/ce2/ce3 not only in final phase by final_prescan_insn finite state machine. We set predicalble_short_it to "no" to restrict conditional code generation on armv8 with thumb mode. However, we could use the flags -mno-restrict-it to force generating conditional code on thumb mode. Therefore, we have to consider the assembly output format for strb with condition code on arm/thumb mode. Because arm/thumb mode use different syntax for strb, we output the assembly as str%(<sync_sfx>%) which will put the condition code in the right place according to TARGET_UNIFIED_ASM. Is there still missing something ? Thanks, Shiva 2015-06-04 18:00 GMT+08:00 Kyrill Tkachov <kyrylo.tkachov@foss.arm.com>: > Hi Shiva, > > On 04/06/15 10:57, Shiva Chen wrote: >> >> Hi, Kyrill >> >> Thanks for the tips of syntax. >> >> It seems that correct syntax for >> >> ldrb with condition code is ldreqb >> >> ldab with condition code is ldabeq >> >> >> So I modified the pattern as follow >> >> { >> enum memmodel model = (enum memmodel) INTVAL (operands[2]); >> if (model == MEMMODEL_RELAXED >> || model == MEMMODEL_CONSUME >> || model == MEMMODEL_RELEASE) >> return \"ldr%?<sync_sfx>\\t%0, %1\"; >> else >> return \"lda<sync_sfx>%?\\t%0, %1\"; >> } >> [(set_attr "predicable" "yes") >> (set_attr "predicable_short_it" "no")]) >> >> It seems we don't have to worry about thumb mode, > > > I suggest you use Richard's suggestion from: > https://gcc.gnu.org/ml/gcc-patches/2015-06/msg00384.html > to write this in a clean way. > >> >> Because we already set "predicable" "yes" and predicable_short_it" "no" >> for the pattern. > > > That's not quite true. The user may compile for armv8-a with > -mno-restrict-it which will turn off this > restriction for Thumb and allow the conditional execution of this. > In any case, I think Richard's suggestion above should work. > > Thanks, > Kyrill > > >> >> The new patch could build gcc and run gcc regression test successfully. >> >> Please correct me if I still missing something. >> >> Thanks, >> >> Shiva >> >> -----Original Message----- >> From: Richard Earnshaw [mailto:Richard.Earnshaw@foss.arm.com] >> Sent: Thursday, June 04, 2015 4:42 PM >> To: Kyrill Tkachov; Shiva Chen >> Cc: Ramana Radhakrishnan; GCC Patches; nickc@redhat.com; Shiva Chen >> Subject: Re: [GCC, ARM] armv8 linux toolchain asan testcase fail due to >> stl missing conditional code >> >> On 04/06/15 09:17, Kyrill Tkachov wrote: >>> >>> Hi Shiva, >>> >>> On 04/06/15 04:13, Shiva Chen wrote: >>>> >>>> Hi, Ramana >>>> >>>> Currently, I work for Marvell and the company have copyright assignment >>>> on file. >>>> >>>> Hi, all >>>> >>>> After adding the attribute and rebuild gcc, I got the assembler error >>>> message >>>> >>>> load_n.s:39: Error: bad instruction `ldrbeq r0,[r0]' >>>> >>>> When i look into armv8 ISA document, it seems ldrb Encoding A1 have >>>> conditional code field. >>>> >>>> Does it mean we should also patch assembler or I just miss >>>> understanding something ? >>>> >>>> Following command use to generate load_n.s: >>>> >>>> /home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnu >>>> eabihf-hard/gcc-final/./gcc/cc1 -fpreprocessed load_n.i -quiet >>>> -dumpbase load_n.c -march=armv8-a -mfloat-abi=hard -mfpu=fp-armv8 >>>> -mtls-dialect=gnu -auxbase-strip .libs/load_1_.o -g3 -O2 -Wall >>>> -Werror -version -fPIC -funwind-tables -o load_n.s >>>> >>>> >>>> The test.c is a simple test case to reproduce missing conditional >>>> code in mmap.c. >>>> >>>> Any suggestion ? >>> >>> I reproduced the assembler failure with your patch. >>> >>> The reason is that for arm mode we use divided syntax, where the >>> condition field goes in a different place. So, while ldrbeq r0,[r0] is >>> rejected, ldreqb r0, [r0] works. >>> Since we always use divided syntax for arm mode, I think you'll need >>> to put the condition field in the right place depending on arm or thumb >>> mode. >>> Ugh, this is becoming ugly :( >>> >> Use %(<suffix%) around the bit that changes for unified/divided syntax. >> The compiler will then put the condition in the correct place. >> >> So: >> >> + return \"str%(<sync_sfx>%)\t%1, %0\"; >> >> R. >> >>> Kyrill >>> >>>> >>>> Shiva >>>> >>>> 2015-06-03 17:29 GMT+08:00 Shiva Chen <shiva0217@gmail.com>: >>>>> >>>>> Hi, Ramana >>>>> >>>>> I'm not sure what copyright assignment means ? >>>>> >>>>> Does it mean the patch have copyright assignment or not ? >>>>> >>>>> I update the patch to add "predicable" and "predicable_short_it" >>>>> attribute as suggestion. >>>>> >>>>> However, I don't have svn write access yet. >>>>> >>>>> Shiva >>>>> >>>>> 2015-06-03 16:36 GMT+08:00 Kyrill Tkachov <kyrylo.tkachov@arm.com>: >>>>>> >>>>>> On 03/06/15 09:32, Ramana Radhakrishnan wrote: >>>>>>>> >>>>>>>> This pattern is not predicable though, i.e. it doesn't have the >>>>>>>> "predicable" attribute set to "yes". >>>>>>>> Therefore the compiler should be trying to branch around here >>>>>>>> rather than try to do a cond_exec. >>>>>>>> Why does the generated code above look like it's converted to >>>>>>>> conditional execution? >>>>>>>> Could you produce a self-contained reduced testcase for this? >>>>>>> >>>>>>> CCFSM state machine in ARM state. >>>>>>> >>>>>>> arm.c (final_prescan_insn). >>>>>> >>>>>> Ah ok. >>>>>> This patch makes sense then. >>>>>> As Ramana mentioned, please mark the pattern with "predicable" and >>>>>> also set the "predicable_short_it" attribute to "no" so that it >>>>>> will not be conditionalised in Thumb2 mode or when -mrestrict-it is >>>>>> enabled. >>>>>> >>>>>> Thanks, >>>>>> Kyrill >>>>>> >>>>>> >>>>>> >>>>>>> Ramana >>>>>>> >>>>>>>> Thanks, >>>>>>>> Kyrill >>>>>>>> >>>>>>>>> @@ -91,9 +91,9 @@ >>>>>>>>> { >>>>>>>>> enum memmodel model = memmodel_from_int (INTVAL >>>>>>>>> (operands[2])); >>>>>>>>> if (is_mm_relaxed (model) || is_mm_consume (model) || >>>>>>>>> is_mm_acquire (model)) >>>>>>>>> - return \"str<sync_sfx>\t%1, %0\"; >>>>>>>>> + return \"str<sync_sfx>%?\t%1, %0\"; >>>>>>>>> else >>>>>>>>> - return \"stl<sync_sfx>\t%1, %0\"; >>>>>>>>> + return \"stl<sync_sfx>%?\t%1, %0\"; >>>>>>>>> } >>>>>>>>> ) >>>>>>>>> > [-- Attachment #2: Fix_slt_lda_missing_conditional_code.diff --] [-- Type: text/plain, Size: 1278 bytes --] diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md index 44cda61..75dd52e 100644 --- a/gcc/config/arm/sync.md +++ b/gcc/config/arm/sync.md @@ -75,11 +75,12 @@ { enum memmodel model = memmodel_from_int (INTVAL (operands[2])); if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_release (model)) - return \"ldr<sync_sfx>\\t%0, %1\"; + return \"ldr%(<sync_sfx>%)\\t%0, %1\"; else - return \"lda<sync_sfx>\\t%0, %1\"; + return \"lda<sync_sfx>%?\\t%0, %1\"; } -) + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no")]) (define_insn "atomic_store<mode>" [(set (match_operand:QHSI 0 "memory_operand" "=Q") @@ -91,11 +92,12 @@ { enum memmodel model = memmodel_from_int (INTVAL (operands[2])); if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_acquire (model)) - return \"str<sync_sfx>\t%1, %0\"; + return \"str%(<sync_sfx>%)\t%1, %0\"; else - return \"stl<sync_sfx>\t%1, %0\"; + return \"stl<sync_sfx>%?\t%1, %0\"; } -) + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no")]) ;; Note that ldrd and vldr are *not* guaranteed to be single-copy atomic, ;; even for a 64-bit aligned address. Instead we use a ldrexd unparied ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code 2015-06-05 8:34 ` Shiva Chen @ 2015-06-05 8:35 ` Kyrill Tkachov 2015-06-05 10:59 ` Shiva Chen 0 siblings, 1 reply; 21+ messages in thread From: Kyrill Tkachov @ 2015-06-05 8:35 UTC (permalink / raw) To: Shiva Chen Cc: Shiva Chen, Richard Earnshaw, Ramana Radhakrishnan, GCC Patches, nickc Hi Shiva, On 05/06/15 09:29, Shiva Chen wrote: > Hi, Kyrill > > I update the patch as Richard's suggestion. > > - return \"str<sync_sfx>\t%1, %0\"; > + return \"str%(<sync_sfx>%)\t%1, %0\"; > else > - return \"stl<sync_sfx>\t%1, %0\"; > + return \"stl<sync_sfx>%?\t%1, %0\"; > } > -) > + [(set_attr "predicable" "yes") > + (set_attr "predicable_short_it" "no")]) > + [(set_attr "predicable" "yes") > + (set_attr "predicable_short_it" "no")]) > > > Let me sum up. > > We add predicable attribute to allow gcc do if-conversion in > ce1/ce2/ce3 not only in final phase by final_prescan_insn finite state > machine. > > We set predicalble_short_it to "no" to restrict conditional code > generation on armv8 with thumb mode. > > However, we could use the flags -mno-restrict-it to force generating > conditional code on thumb mode. > > Therefore, we have to consider the assembly output format for strb > with condition code on arm/thumb mode. > > Because arm/thumb mode use different syntax for strb, > we output the assembly as str%(<sync_sfx>%) > which will put the condition code in the right place according to > TARGET_UNIFIED_ASM. > > Is there still missing something ? That's all correct, and well summarised :) The patch looks good to me, but please include the testcase (test.c from earlier) appropriately marked up for the testsuite. I think to the level of dg-assemble, just so we know everything is wired up properly. Thanks for dealing with this. Kyrill > > Thanks, > > Shiva > > 2015-06-04 18:00 GMT+08:00 Kyrill Tkachov <kyrylo.tkachov@foss.arm.com>: >> Hi Shiva, >> >> On 04/06/15 10:57, Shiva Chen wrote: >>> Hi, Kyrill >>> >>> Thanks for the tips of syntax. >>> >>> It seems that correct syntax for >>> >>> ldrb with condition code is ldreqb >>> >>> ldab with condition code is ldabeq >>> >>> >>> So I modified the pattern as follow >>> >>> { >>> enum memmodel model = (enum memmodel) INTVAL (operands[2]); >>> if (model == MEMMODEL_RELAXED >>> || model == MEMMODEL_CONSUME >>> || model == MEMMODEL_RELEASE) >>> return \"ldr%?<sync_sfx>\\t%0, %1\"; >>> else >>> return \"lda<sync_sfx>%?\\t%0, %1\"; >>> } >>> [(set_attr "predicable" "yes") >>> (set_attr "predicable_short_it" "no")]) >>> >>> It seems we don't have to worry about thumb mode, >> >> I suggest you use Richard's suggestion from: >> https://gcc.gnu.org/ml/gcc-patches/2015-06/msg00384.html >> to write this in a clean way. >> >>> Because we already set "predicable" "yes" and predicable_short_it" "no" >>> for the pattern. >> >> That's not quite true. The user may compile for armv8-a with >> -mno-restrict-it which will turn off this >> restriction for Thumb and allow the conditional execution of this. >> In any case, I think Richard's suggestion above should work. >> >> Thanks, >> Kyrill >> >> >>> The new patch could build gcc and run gcc regression test successfully. >>> >>> Please correct me if I still missing something. >>> >>> Thanks, >>> >>> Shiva >>> >>> -----Original Message----- >>> From: Richard Earnshaw [mailto:Richard.Earnshaw@foss.arm.com] >>> Sent: Thursday, June 04, 2015 4:42 PM >>> To: Kyrill Tkachov; Shiva Chen >>> Cc: Ramana Radhakrishnan; GCC Patches; nickc@redhat.com; Shiva Chen >>> Subject: Re: [GCC, ARM] armv8 linux toolchain asan testcase fail due to >>> stl missing conditional code >>> >>> On 04/06/15 09:17, Kyrill Tkachov wrote: >>>> Hi Shiva, >>>> >>>> On 04/06/15 04:13, Shiva Chen wrote: >>>>> Hi, Ramana >>>>> >>>>> Currently, I work for Marvell and the company have copyright assignment >>>>> on file. >>>>> >>>>> Hi, all >>>>> >>>>> After adding the attribute and rebuild gcc, I got the assembler error >>>>> message >>>>> >>>>> load_n.s:39: Error: bad instruction `ldrbeq r0,[r0]' >>>>> >>>>> When i look into armv8 ISA document, it seems ldrb Encoding A1 have >>>>> conditional code field. >>>>> >>>>> Does it mean we should also patch assembler or I just miss >>>>> understanding something ? >>>>> >>>>> Following command use to generate load_n.s: >>>>> >>>>> /home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnu >>>>> eabihf-hard/gcc-final/./gcc/cc1 -fpreprocessed load_n.i -quiet >>>>> -dumpbase load_n.c -march=armv8-a -mfloat-abi=hard -mfpu=fp-armv8 >>>>> -mtls-dialect=gnu -auxbase-strip .libs/load_1_.o -g3 -O2 -Wall >>>>> -Werror -version -fPIC -funwind-tables -o load_n.s >>>>> >>>>> >>>>> The test.c is a simple test case to reproduce missing conditional >>>>> code in mmap.c. >>>>> >>>>> Any suggestion ? >>>> I reproduced the assembler failure with your patch. >>>> >>>> The reason is that for arm mode we use divided syntax, where the >>>> condition field goes in a different place. So, while ldrbeq r0,[r0] is >>>> rejected, ldreqb r0, [r0] works. >>>> Since we always use divided syntax for arm mode, I think you'll need >>>> to put the condition field in the right place depending on arm or thumb >>>> mode. >>>> Ugh, this is becoming ugly :( >>>> >>> Use %(<suffix%) around the bit that changes for unified/divided syntax. >>> The compiler will then put the condition in the correct place. >>> >>> So: >>> >>> + return \"str%(<sync_sfx>%)\t%1, %0\"; >>> >>> R. >>> >>>> Kyrill >>>> >>>>> Shiva >>>>> >>>>> 2015-06-03 17:29 GMT+08:00 Shiva Chen <shiva0217@gmail.com>: >>>>>> Hi, Ramana >>>>>> >>>>>> I'm not sure what copyright assignment means ? >>>>>> >>>>>> Does it mean the patch have copyright assignment or not ? >>>>>> >>>>>> I update the patch to add "predicable" and "predicable_short_it" >>>>>> attribute as suggestion. >>>>>> >>>>>> However, I don't have svn write access yet. >>>>>> >>>>>> Shiva >>>>>> >>>>>> 2015-06-03 16:36 GMT+08:00 Kyrill Tkachov <kyrylo.tkachov@arm.com>: >>>>>>> On 03/06/15 09:32, Ramana Radhakrishnan wrote: >>>>>>>>> This pattern is not predicable though, i.e. it doesn't have the >>>>>>>>> "predicable" attribute set to "yes". >>>>>>>>> Therefore the compiler should be trying to branch around here >>>>>>>>> rather than try to do a cond_exec. >>>>>>>>> Why does the generated code above look like it's converted to >>>>>>>>> conditional execution? >>>>>>>>> Could you produce a self-contained reduced testcase for this? >>>>>>>> CCFSM state machine in ARM state. >>>>>>>> >>>>>>>> arm.c (final_prescan_insn). >>>>>>> Ah ok. >>>>>>> This patch makes sense then. >>>>>>> As Ramana mentioned, please mark the pattern with "predicable" and >>>>>>> also set the "predicable_short_it" attribute to "no" so that it >>>>>>> will not be conditionalised in Thumb2 mode or when -mrestrict-it is >>>>>>> enabled. >>>>>>> >>>>>>> Thanks, >>>>>>> Kyrill >>>>>>> >>>>>>> >>>>>>> >>>>>>>> Ramana >>>>>>>> >>>>>>>>> Thanks, >>>>>>>>> Kyrill >>>>>>>>> >>>>>>>>>> @@ -91,9 +91,9 @@ >>>>>>>>>> { >>>>>>>>>> enum memmodel model = memmodel_from_int (INTVAL >>>>>>>>>> (operands[2])); >>>>>>>>>> if (is_mm_relaxed (model) || is_mm_consume (model) || >>>>>>>>>> is_mm_acquire (model)) >>>>>>>>>> - return \"str<sync_sfx>\t%1, %0\"; >>>>>>>>>> + return \"str<sync_sfx>%?\t%1, %0\"; >>>>>>>>>> else >>>>>>>>>> - return \"stl<sync_sfx>\t%1, %0\"; >>>>>>>>>> + return \"stl<sync_sfx>%?\t%1, %0\"; >>>>>>>>>> } >>>>>>>>>> ) >>>>>>>>>> ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code 2015-06-05 8:35 ` Kyrill Tkachov @ 2015-06-05 10:59 ` Shiva Chen 2015-06-05 13:11 ` Kyrill Tkachov 0 siblings, 1 reply; 21+ messages in thread From: Shiva Chen @ 2015-06-05 10:59 UTC (permalink / raw) To: Kyrill Tkachov Cc: Shiva Chen, Richard Earnshaw, Ramana Radhakrishnan, GCC Patches, nickc [-- Attachment #1: Type: text/plain, Size: 7875 bytes --] Hi, Kyrill I add the testcase as stl-cond.c. Could you help to check the testcase ? If it's OK, Could you help me to apply the patch ? Thanks, Shiva 2015-06-05 16:34 GMT+08:00 Kyrill Tkachov <kyrylo.tkachov@foss.arm.com>: > Hi Shiva, > > On 05/06/15 09:29, Shiva Chen wrote: >> >> Hi, Kyrill >> >> I update the patch as Richard's suggestion. >> >> - return \"str<sync_sfx>\t%1, %0\"; >> + return \"str%(<sync_sfx>%)\t%1, %0\"; >> else >> - return \"stl<sync_sfx>\t%1, %0\"; >> + return \"stl<sync_sfx>%?\t%1, %0\"; >> } >> -) >> + [(set_attr "predicable" "yes") >> + (set_attr "predicable_short_it" "no")]) >> + [(set_attr "predicable" "yes") >> + (set_attr "predicable_short_it" "no")]) >> >> >> Let me sum up. >> >> We add predicable attribute to allow gcc do if-conversion in >> ce1/ce2/ce3 not only in final phase by final_prescan_insn finite state >> machine. >> >> We set predicalble_short_it to "no" to restrict conditional code >> generation on armv8 with thumb mode. >> >> However, we could use the flags -mno-restrict-it to force generating >> conditional code on thumb mode. >> >> Therefore, we have to consider the assembly output format for strb >> with condition code on arm/thumb mode. >> >> Because arm/thumb mode use different syntax for strb, >> we output the assembly as str%(<sync_sfx>%) >> which will put the condition code in the right place according to >> TARGET_UNIFIED_ASM. >> >> Is there still missing something ? > > > That's all correct, and well summarised :) > The patch looks good to me, but please include the testcase > (test.c from earlier) appropriately marked up for the testsuite. > I think to the level of dg-assemble, just so we know everything is > wired up properly. > > Thanks for dealing with this. > Kyrill > > >> >> Thanks, >> >> Shiva >> >> 2015-06-04 18:00 GMT+08:00 Kyrill Tkachov <kyrylo.tkachov@foss.arm.com>: >>> >>> Hi Shiva, >>> >>> On 04/06/15 10:57, Shiva Chen wrote: >>>> >>>> Hi, Kyrill >>>> >>>> Thanks for the tips of syntax. >>>> >>>> It seems that correct syntax for >>>> >>>> ldrb with condition code is ldreqb >>>> >>>> ldab with condition code is ldabeq >>>> >>>> >>>> So I modified the pattern as follow >>>> >>>> { >>>> enum memmodel model = (enum memmodel) INTVAL (operands[2]); >>>> if (model == MEMMODEL_RELAXED >>>> || model == MEMMODEL_CONSUME >>>> || model == MEMMODEL_RELEASE) >>>> return \"ldr%?<sync_sfx>\\t%0, %1\"; >>>> else >>>> return \"lda<sync_sfx>%?\\t%0, %1\"; >>>> } >>>> [(set_attr "predicable" "yes") >>>> (set_attr "predicable_short_it" "no")]) >>>> >>>> It seems we don't have to worry about thumb mode, >>> >>> >>> I suggest you use Richard's suggestion from: >>> https://gcc.gnu.org/ml/gcc-patches/2015-06/msg00384.html >>> to write this in a clean way. >>> >>>> Because we already set "predicable" "yes" and predicable_short_it" "no" >>>> for the pattern. >>> >>> >>> That's not quite true. The user may compile for armv8-a with >>> -mno-restrict-it which will turn off this >>> restriction for Thumb and allow the conditional execution of this. >>> In any case, I think Richard's suggestion above should work. >>> >>> Thanks, >>> Kyrill >>> >>> >>>> The new patch could build gcc and run gcc regression test successfully. >>>> >>>> Please correct me if I still missing something. >>>> >>>> Thanks, >>>> >>>> Shiva >>>> >>>> -----Original Message----- >>>> From: Richard Earnshaw [mailto:Richard.Earnshaw@foss.arm.com] >>>> Sent: Thursday, June 04, 2015 4:42 PM >>>> To: Kyrill Tkachov; Shiva Chen >>>> Cc: Ramana Radhakrishnan; GCC Patches; nickc@redhat.com; Shiva Chen >>>> Subject: Re: [GCC, ARM] armv8 linux toolchain asan testcase fail due to >>>> stl missing conditional code >>>> >>>> On 04/06/15 09:17, Kyrill Tkachov wrote: >>>>> >>>>> Hi Shiva, >>>>> >>>>> On 04/06/15 04:13, Shiva Chen wrote: >>>>>> >>>>>> Hi, Ramana >>>>>> >>>>>> Currently, I work for Marvell and the company have copyright >>>>>> assignment >>>>>> on file. >>>>>> >>>>>> Hi, all >>>>>> >>>>>> After adding the attribute and rebuild gcc, I got the assembler error >>>>>> message >>>>>> >>>>>> load_n.s:39: Error: bad instruction `ldrbeq r0,[r0]' >>>>>> >>>>>> When i look into armv8 ISA document, it seems ldrb Encoding A1 have >>>>>> conditional code field. >>>>>> >>>>>> Does it mean we should also patch assembler or I just miss >>>>>> understanding something ? >>>>>> >>>>>> Following command use to generate load_n.s: >>>>>> >>>>>> /home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnu >>>>>> eabihf-hard/gcc-final/./gcc/cc1 -fpreprocessed load_n.i -quiet >>>>>> -dumpbase load_n.c -march=armv8-a -mfloat-abi=hard -mfpu=fp-armv8 >>>>>> -mtls-dialect=gnu -auxbase-strip .libs/load_1_.o -g3 -O2 -Wall >>>>>> -Werror -version -fPIC -funwind-tables -o load_n.s >>>>>> >>>>>> >>>>>> The test.c is a simple test case to reproduce missing conditional >>>>>> code in mmap.c. >>>>>> >>>>>> Any suggestion ? >>>>> >>>>> I reproduced the assembler failure with your patch. >>>>> >>>>> The reason is that for arm mode we use divided syntax, where the >>>>> condition field goes in a different place. So, while ldrbeq r0,[r0] is >>>>> rejected, ldreqb r0, [r0] works. >>>>> Since we always use divided syntax for arm mode, I think you'll need >>>>> to put the condition field in the right place depending on arm or thumb >>>>> mode. >>>>> Ugh, this is becoming ugly :( >>>>> >>>> Use %(<suffix%) around the bit that changes for unified/divided syntax. >>>> The compiler will then put the condition in the correct place. >>>> >>>> So: >>>> >>>> + return \"str%(<sync_sfx>%)\t%1, %0\"; >>>> >>>> R. >>>> >>>>> Kyrill >>>>> >>>>>> Shiva >>>>>> >>>>>> 2015-06-03 17:29 GMT+08:00 Shiva Chen <shiva0217@gmail.com>: >>>>>>> >>>>>>> Hi, Ramana >>>>>>> >>>>>>> I'm not sure what copyright assignment means ? >>>>>>> >>>>>>> Does it mean the patch have copyright assignment or not ? >>>>>>> >>>>>>> I update the patch to add "predicable" and "predicable_short_it" >>>>>>> attribute as suggestion. >>>>>>> >>>>>>> However, I don't have svn write access yet. >>>>>>> >>>>>>> Shiva >>>>>>> >>>>>>> 2015-06-03 16:36 GMT+08:00 Kyrill Tkachov <kyrylo.tkachov@arm.com>: >>>>>>>> >>>>>>>> On 03/06/15 09:32, Ramana Radhakrishnan wrote: >>>>>>>>>> >>>>>>>>>> This pattern is not predicable though, i.e. it doesn't have the >>>>>>>>>> "predicable" attribute set to "yes". >>>>>>>>>> Therefore the compiler should be trying to branch around here >>>>>>>>>> rather than try to do a cond_exec. >>>>>>>>>> Why does the generated code above look like it's converted to >>>>>>>>>> conditional execution? >>>>>>>>>> Could you produce a self-contained reduced testcase for this? >>>>>>>>> >>>>>>>>> CCFSM state machine in ARM state. >>>>>>>>> >>>>>>>>> arm.c (final_prescan_insn). >>>>>>>> >>>>>>>> Ah ok. >>>>>>>> This patch makes sense then. >>>>>>>> As Ramana mentioned, please mark the pattern with "predicable" and >>>>>>>> also set the "predicable_short_it" attribute to "no" so that it >>>>>>>> will not be conditionalised in Thumb2 mode or when -mrestrict-it is >>>>>>>> enabled. >>>>>>>> >>>>>>>> Thanks, >>>>>>>> Kyrill >>>>>>>> >>>>>>>> >>>>>>>> >>>>>>>>> Ramana >>>>>>>>> >>>>>>>>>> Thanks, >>>>>>>>>> Kyrill >>>>>>>>>> >>>>>>>>>>> @@ -91,9 +91,9 @@ >>>>>>>>>>> { >>>>>>>>>>> enum memmodel model = memmodel_from_int (INTVAL >>>>>>>>>>> (operands[2])); >>>>>>>>>>> if (is_mm_relaxed (model) || is_mm_consume (model) || >>>>>>>>>>> is_mm_acquire (model)) >>>>>>>>>>> - return \"str<sync_sfx>\t%1, %0\"; >>>>>>>>>>> + return \"str<sync_sfx>%?\t%1, %0\"; >>>>>>>>>>> else >>>>>>>>>>> - return \"stl<sync_sfx>\t%1, %0\"; >>>>>>>>>>> + return \"stl<sync_sfx>%?\t%1, %0\"; >>>>>>>>>>> } >>>>>>>>>>> ) >>>>>>>>>>> > [-- Attachment #2: Fix_slt_lda_missing_conditional_code.diff --] [-- Type: text/plain, Size: 1880 bytes --] diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md index 44cda61..75dd52e 100644 --- a/gcc/config/arm/sync.md +++ b/gcc/config/arm/sync.md @@ -75,11 +75,12 @@ { enum memmodel model = memmodel_from_int (INTVAL (operands[2])); if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_release (model)) - return \"ldr<sync_sfx>\\t%0, %1\"; + return \"ldr%(<sync_sfx>%)\\t%0, %1\"; else - return \"lda<sync_sfx>\\t%0, %1\"; + return \"lda<sync_sfx>%?\\t%0, %1\"; } -) + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no")]) (define_insn "atomic_store<mode>" [(set (match_operand:QHSI 0 "memory_operand" "=Q") @@ -91,11 +92,12 @@ { enum memmodel model = memmodel_from_int (INTVAL (operands[2])); if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_acquire (model)) - return \"str<sync_sfx>\t%1, %0\"; + return \"str%(<sync_sfx>%)\t%1, %0\"; else - return \"stl<sync_sfx>\t%1, %0\"; + return \"stl<sync_sfx>%?\t%1, %0\"; } -) + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no")]) ;; Note that ldrd and vldr are *not* guaranteed to be single-copy atomic, ;; even for a 64-bit aligned address. Instead we use a ldrexd unparied diff --git a/gcc/testsuite/gcc.target/arm/stl-cond.c b/gcc/testsuite/gcc.target/arm/stl-cond.c new file mode 100755 index 0000000..44c6249 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/stl-cond.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +struct backtrace_state +{ + int threaded; + int lock_alloc; +}; + +void foo (struct backtrace_state *state) +{ + if (state->threaded) + __sync_lock_release (&state->lock_alloc); +} + +/* { dg-final { scan-assembler "stlne" } } */ [-- Attachment #3: ChangeLog.fix_slt_lda_missing_conditional_code --] [-- Type: application/octet-stream, Size: 181 bytes --] 2015-06-05 Shiva Chen <shiva0217@gmail.com> * config/arm/sync.md (atomic_load<mode>,(atomic_store<mode>): Add condition code for arm load acquire/store release instructions ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code 2015-06-05 10:59 ` Shiva Chen @ 2015-06-05 13:11 ` Kyrill Tkachov 2015-06-05 13:14 ` Richard Earnshaw 0 siblings, 1 reply; 21+ messages in thread From: Kyrill Tkachov @ 2015-06-05 13:11 UTC (permalink / raw) To: Shiva Chen Cc: Shiva Chen, Richard Earnshaw, Ramana Radhakrishnan, GCC Patches, nickc Hi Shiva, On 05/06/15 10:42, Shiva Chen wrote: > Hi, Kyrill > > I add the testcase as stl-cond.c. > > Could you help to check the testcase ? > > If it's OK, Could you help me to apply the patch ? > This looks ok to me. One nit on the testcase: diff --git a/gcc/testsuite/gcc.target/arm/stl-cond.c b/gcc/testsuite/gcc.target/arm/stl-cond.c new file mode 100755 index 0000000..44c6249 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/stl-cond.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-options "-O2" } */ This should also have -marm as the problem exhibited itself in arm state. I'll commit this patch with this change in 24 hours on your behalf if no one objects. Ramana, Richard, we need to backport it to GCC 5 as well, right? Thanks, Kyrill > Thanks, > > Shiva > > 2015-06-05 16:34 GMT+08:00 Kyrill Tkachov <kyrylo.tkachov@foss.arm.com>: >> Hi Shiva, >> >> On 05/06/15 09:29, Shiva Chen wrote: >>> Hi, Kyrill >>> >>> I update the patch as Richard's suggestion. >>> >>> - return \"str<sync_sfx>\t%1, %0\"; >>> + return \"str%(<sync_sfx>%)\t%1, %0\"; >>> else >>> - return \"stl<sync_sfx>\t%1, %0\"; >>> + return \"stl<sync_sfx>%?\t%1, %0\"; >>> } >>> -) >>> + [(set_attr "predicable" "yes") >>> + (set_attr "predicable_short_it" "no")]) >>> + [(set_attr "predicable" "yes") >>> + (set_attr "predicable_short_it" "no")]) >>> >>> >>> Let me sum up. >>> >>> We add predicable attribute to allow gcc do if-conversion in >>> ce1/ce2/ce3 not only in final phase by final_prescan_insn finite state >>> machine. >>> >>> We set predicalble_short_it to "no" to restrict conditional code >>> generation on armv8 with thumb mode. >>> >>> However, we could use the flags -mno-restrict-it to force generating >>> conditional code on thumb mode. >>> >>> Therefore, we have to consider the assembly output format for strb >>> with condition code on arm/thumb mode. >>> >>> Because arm/thumb mode use different syntax for strb, >>> we output the assembly as str%(<sync_sfx>%) >>> which will put the condition code in the right place according to >>> TARGET_UNIFIED_ASM. >>> >>> Is there still missing something ? >> >> That's all correct, and well summarised :) >> The patch looks good to me, but please include the testcase >> (test.c from earlier) appropriately marked up for the testsuite. >> I think to the level of dg-assemble, just so we know everything is >> wired up properly. >> >> Thanks for dealing with this. >> Kyrill >> >> >>> Thanks, >>> >>> Shiva >>> >>> 2015-06-04 18:00 GMT+08:00 Kyrill Tkachov <kyrylo.tkachov@foss.arm.com>: >>>> Hi Shiva, >>>> >>>> On 04/06/15 10:57, Shiva Chen wrote: >>>>> Hi, Kyrill >>>>> >>>>> Thanks for the tips of syntax. >>>>> >>>>> It seems that correct syntax for >>>>> >>>>> ldrb with condition code is ldreqb >>>>> >>>>> ldab with condition code is ldabeq >>>>> >>>>> >>>>> So I modified the pattern as follow >>>>> >>>>> { >>>>> enum memmodel model = (enum memmodel) INTVAL (operands[2]); >>>>> if (model == MEMMODEL_RELAXED >>>>> || model == MEMMODEL_CONSUME >>>>> || model == MEMMODEL_RELEASE) >>>>> return \"ldr%?<sync_sfx>\\t%0, %1\"; >>>>> else >>>>> return \"lda<sync_sfx>%?\\t%0, %1\"; >>>>> } >>>>> [(set_attr "predicable" "yes") >>>>> (set_attr "predicable_short_it" "no")]) >>>>> >>>>> It seems we don't have to worry about thumb mode, >>>> >>>> I suggest you use Richard's suggestion from: >>>> https://gcc.gnu.org/ml/gcc-patches/2015-06/msg00384.html >>>> to write this in a clean way. >>>> >>>>> Because we already set "predicable" "yes" and predicable_short_it" "no" >>>>> for the pattern. >>>> >>>> That's not quite true. The user may compile for armv8-a with >>>> -mno-restrict-it which will turn off this >>>> restriction for Thumb and allow the conditional execution of this. >>>> In any case, I think Richard's suggestion above should work. >>>> >>>> Thanks, >>>> Kyrill >>>> >>>> >>>>> The new patch could build gcc and run gcc regression test successfully. >>>>> >>>>> Please correct me if I still missing something. >>>>> >>>>> Thanks, >>>>> >>>>> Shiva >>>>> >>>>> -----Original Message----- >>>>> From: Richard Earnshaw [mailto:Richard.Earnshaw@foss.arm.com] >>>>> Sent: Thursday, June 04, 2015 4:42 PM >>>>> To: Kyrill Tkachov; Shiva Chen >>>>> Cc: Ramana Radhakrishnan; GCC Patches; nickc@redhat.com; Shiva Chen >>>>> Subject: Re: [GCC, ARM] armv8 linux toolchain asan testcase fail due to >>>>> stl missing conditional code >>>>> >>>>> On 04/06/15 09:17, Kyrill Tkachov wrote: >>>>>> Hi Shiva, >>>>>> >>>>>> On 04/06/15 04:13, Shiva Chen wrote: >>>>>>> Hi, Ramana >>>>>>> >>>>>>> Currently, I work for Marvell and the company have copyright >>>>>>> assignment >>>>>>> on file. >>>>>>> >>>>>>> Hi, all >>>>>>> >>>>>>> After adding the attribute and rebuild gcc, I got the assembler error >>>>>>> message >>>>>>> >>>>>>> load_n.s:39: Error: bad instruction `ldrbeq r0,[r0]' >>>>>>> >>>>>>> When i look into armv8 ISA document, it seems ldrb Encoding A1 have >>>>>>> conditional code field. >>>>>>> >>>>>>> Does it mean we should also patch assembler or I just miss >>>>>>> understanding something ? >>>>>>> >>>>>>> Following command use to generate load_n.s: >>>>>>> >>>>>>> /home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnu >>>>>>> eabihf-hard/gcc-final/./gcc/cc1 -fpreprocessed load_n.i -quiet >>>>>>> -dumpbase load_n.c -march=armv8-a -mfloat-abi=hard -mfpu=fp-armv8 >>>>>>> -mtls-dialect=gnu -auxbase-strip .libs/load_1_.o -g3 -O2 -Wall >>>>>>> -Werror -version -fPIC -funwind-tables -o load_n.s >>>>>>> >>>>>>> >>>>>>> The test.c is a simple test case to reproduce missing conditional >>>>>>> code in mmap.c. >>>>>>> >>>>>>> Any suggestion ? >>>>>> I reproduced the assembler failure with your patch. >>>>>> >>>>>> The reason is that for arm mode we use divided syntax, where the >>>>>> condition field goes in a different place. So, while ldrbeq r0,[r0] is >>>>>> rejected, ldreqb r0, [r0] works. >>>>>> Since we always use divided syntax for arm mode, I think you'll need >>>>>> to put the condition field in the right place depending on arm or thumb >>>>>> mode. >>>>>> Ugh, this is becoming ugly :( >>>>>> >>>>> Use %(<suffix%) around the bit that changes for unified/divided syntax. >>>>> The compiler will then put the condition in the correct place. >>>>> >>>>> So: >>>>> >>>>> + return \"str%(<sync_sfx>%)\t%1, %0\"; >>>>> >>>>> R. >>>>> >>>>>> Kyrill >>>>>> >>>>>>> Shiva >>>>>>> >>>>>>> 2015-06-03 17:29 GMT+08:00 Shiva Chen <shiva0217@gmail.com>: >>>>>>>> Hi, Ramana >>>>>>>> >>>>>>>> I'm not sure what copyright assignment means ? >>>>>>>> >>>>>>>> Does it mean the patch have copyright assignment or not ? >>>>>>>> >>>>>>>> I update the patch to add "predicable" and "predicable_short_it" >>>>>>>> attribute as suggestion. >>>>>>>> >>>>>>>> However, I don't have svn write access yet. >>>>>>>> >>>>>>>> Shiva >>>>>>>> >>>>>>>> 2015-06-03 16:36 GMT+08:00 Kyrill Tkachov <kyrylo.tkachov@arm.com>: >>>>>>>>> On 03/06/15 09:32, Ramana Radhakrishnan wrote: >>>>>>>>>>> This pattern is not predicable though, i.e. it doesn't have the >>>>>>>>>>> "predicable" attribute set to "yes". >>>>>>>>>>> Therefore the compiler should be trying to branch around here >>>>>>>>>>> rather than try to do a cond_exec. >>>>>>>>>>> Why does the generated code above look like it's converted to >>>>>>>>>>> conditional execution? >>>>>>>>>>> Could you produce a self-contained reduced testcase for this? >>>>>>>>>> CCFSM state machine in ARM state. >>>>>>>>>> >>>>>>>>>> arm.c (final_prescan_insn). >>>>>>>>> Ah ok. >>>>>>>>> This patch makes sense then. >>>>>>>>> As Ramana mentioned, please mark the pattern with "predicable" and >>>>>>>>> also set the "predicable_short_it" attribute to "no" so that it >>>>>>>>> will not be conditionalised in Thumb2 mode or when -mrestrict-it is >>>>>>>>> enabled. >>>>>>>>> >>>>>>>>> Thanks, >>>>>>>>> Kyrill >>>>>>>>> >>>>>>>>> >>>>>>>>> >>>>>>>>>> Ramana >>>>>>>>>> >>>>>>>>>>> Thanks, >>>>>>>>>>> Kyrill >>>>>>>>>>> >>>>>>>>>>>> @@ -91,9 +91,9 @@ >>>>>>>>>>>> { >>>>>>>>>>>> enum memmodel model = memmodel_from_int (INTVAL >>>>>>>>>>>> (operands[2])); >>>>>>>>>>>> if (is_mm_relaxed (model) || is_mm_consume (model) || >>>>>>>>>>>> is_mm_acquire (model)) >>>>>>>>>>>> - return \"str<sync_sfx>\t%1, %0\"; >>>>>>>>>>>> + return \"str<sync_sfx>%?\t%1, %0\"; >>>>>>>>>>>> else >>>>>>>>>>>> - return \"stl<sync_sfx>\t%1, %0\"; >>>>>>>>>>>> + return \"stl<sync_sfx>%?\t%1, %0\"; >>>>>>>>>>>> } >>>>>>>>>>>> ) >>>>>>>>>>>> ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code 2015-06-05 13:11 ` Kyrill Tkachov @ 2015-06-05 13:14 ` Richard Earnshaw 2015-06-05 14:02 ` Kyrill Tkachov 0 siblings, 1 reply; 21+ messages in thread From: Richard Earnshaw @ 2015-06-05 13:14 UTC (permalink / raw) To: Kyrill Tkachov, Shiva Chen Cc: Shiva Chen, Ramana Radhakrishnan, GCC Patches, nickc On 05/06/15 14:08, Kyrill Tkachov wrote: > Hi Shiva, > > On 05/06/15 10:42, Shiva Chen wrote: >> Hi, Kyrill >> >> I add the testcase as stl-cond.c. >> >> Could you help to check the testcase ? >> >> If it's OK, Could you help me to apply the patch ? >> > > This looks ok to me. > One nit on the testcase: > > diff --git a/gcc/testsuite/gcc.target/arm/stl-cond.c > b/gcc/testsuite/gcc.target/arm/stl-cond.c > new file mode 100755 > index 0000000..44c6249 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/stl-cond.c > @@ -0,0 +1,18 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target arm_arch_v8a_ok } */ > +/* { dg-options "-O2" } */ > > This should also have -marm as the problem exhibited itself in arm state. > I'll commit this patch with this change in 24 hours on your behalf if no > one > objects. > Explicit use of -marm will break multi-lib testing. I've forgotten the correct hook, but there's most-likely something that will give you the right behaviour, even if it means that thumb-only multi-lib testing skips this test. R. > Ramana, Richard, we need to backport it to GCC 5 as well, right? > > Thanks, > Kyrill > > >> Thanks, >> >> Shiva >> >> 2015-06-05 16:34 GMT+08:00 Kyrill Tkachov <kyrylo.tkachov@foss.arm.com>: >>> Hi Shiva, >>> >>> On 05/06/15 09:29, Shiva Chen wrote: >>>> Hi, Kyrill >>>> >>>> I update the patch as Richard's suggestion. >>>> >>>> - return \"str<sync_sfx>\t%1, %0\"; >>>> + return \"str%(<sync_sfx>%)\t%1, %0\"; >>>> else >>>> - return \"stl<sync_sfx>\t%1, %0\"; >>>> + return \"stl<sync_sfx>%?\t%1, %0\"; >>>> } >>>> -) >>>> + [(set_attr "predicable" "yes") >>>> + (set_attr "predicable_short_it" "no")]) >>>> + [(set_attr "predicable" "yes") >>>> + (set_attr "predicable_short_it" "no")]) >>>> >>>> >>>> Let me sum up. >>>> >>>> We add predicable attribute to allow gcc do if-conversion in >>>> ce1/ce2/ce3 not only in final phase by final_prescan_insn finite state >>>> machine. >>>> >>>> We set predicalble_short_it to "no" to restrict conditional code >>>> generation on armv8 with thumb mode. >>>> >>>> However, we could use the flags -mno-restrict-it to force generating >>>> conditional code on thumb mode. >>>> >>>> Therefore, we have to consider the assembly output format for strb >>>> with condition code on arm/thumb mode. >>>> >>>> Because arm/thumb mode use different syntax for strb, >>>> we output the assembly as str%(<sync_sfx>%) >>>> which will put the condition code in the right place according to >>>> TARGET_UNIFIED_ASM. >>>> >>>> Is there still missing something ? >>> >>> That's all correct, and well summarised :) >>> The patch looks good to me, but please include the testcase >>> (test.c from earlier) appropriately marked up for the testsuite. >>> I think to the level of dg-assemble, just so we know everything is >>> wired up properly. >>> >>> Thanks for dealing with this. >>> Kyrill >>> >>> >>>> Thanks, >>>> >>>> Shiva >>>> >>>> 2015-06-04 18:00 GMT+08:00 Kyrill Tkachov >>>> <kyrylo.tkachov@foss.arm.com>: >>>>> Hi Shiva, >>>>> >>>>> On 04/06/15 10:57, Shiva Chen wrote: >>>>>> Hi, Kyrill >>>>>> >>>>>> Thanks for the tips of syntax. >>>>>> >>>>>> It seems that correct syntax for >>>>>> >>>>>> ldrb with condition code is ldreqb >>>>>> >>>>>> ldab with condition code is ldabeq >>>>>> >>>>>> >>>>>> So I modified the pattern as follow >>>>>> >>>>>> { >>>>>> enum memmodel model = (enum memmodel) INTVAL (operands[2]); >>>>>> if (model == MEMMODEL_RELAXED >>>>>> || model == MEMMODEL_CONSUME >>>>>> || model == MEMMODEL_RELEASE) >>>>>> return \"ldr%?<sync_sfx>\\t%0, %1\"; >>>>>> else >>>>>> return \"lda<sync_sfx>%?\\t%0, %1\"; >>>>>> } >>>>>> [(set_attr "predicable" "yes") >>>>>> (set_attr "predicable_short_it" "no")]) >>>>>> >>>>>> It seems we don't have to worry about thumb mode, >>>>> >>>>> I suggest you use Richard's suggestion from: >>>>> https://gcc.gnu.org/ml/gcc-patches/2015-06/msg00384.html >>>>> to write this in a clean way. >>>>> >>>>>> Because we already set "predicable" "yes" and predicable_short_it" >>>>>> "no" >>>>>> for the pattern. >>>>> >>>>> That's not quite true. The user may compile for armv8-a with >>>>> -mno-restrict-it which will turn off this >>>>> restriction for Thumb and allow the conditional execution of this. >>>>> In any case, I think Richard's suggestion above should work. >>>>> >>>>> Thanks, >>>>> Kyrill >>>>> >>>>> >>>>>> The new patch could build gcc and run gcc regression test >>>>>> successfully. >>>>>> >>>>>> Please correct me if I still missing something. >>>>>> >>>>>> Thanks, >>>>>> >>>>>> Shiva >>>>>> >>>>>> -----Original Message----- >>>>>> From: Richard Earnshaw [mailto:Richard.Earnshaw@foss.arm.com] >>>>>> Sent: Thursday, June 04, 2015 4:42 PM >>>>>> To: Kyrill Tkachov; Shiva Chen >>>>>> Cc: Ramana Radhakrishnan; GCC Patches; nickc@redhat.com; Shiva Chen >>>>>> Subject: Re: [GCC, ARM] armv8 linux toolchain asan testcase fail >>>>>> due to >>>>>> stl missing conditional code >>>>>> >>>>>> On 04/06/15 09:17, Kyrill Tkachov wrote: >>>>>>> Hi Shiva, >>>>>>> >>>>>>> On 04/06/15 04:13, Shiva Chen wrote: >>>>>>>> Hi, Ramana >>>>>>>> >>>>>>>> Currently, I work for Marvell and the company have copyright >>>>>>>> assignment >>>>>>>> on file. >>>>>>>> >>>>>>>> Hi, all >>>>>>>> >>>>>>>> After adding the attribute and rebuild gcc, I got the assembler >>>>>>>> error >>>>>>>> message >>>>>>>> >>>>>>>> load_n.s:39: Error: bad instruction `ldrbeq r0,[r0]' >>>>>>>> >>>>>>>> When i look into armv8 ISA document, it seems ldrb Encoding A1 have >>>>>>>> conditional code field. >>>>>>>> >>>>>>>> Does it mean we should also patch assembler or I just miss >>>>>>>> understanding something ? >>>>>>>> >>>>>>>> Following command use to generate load_n.s: >>>>>>>> >>>>>>>> /home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnu >>>>>>>> >>>>>>>> eabihf-hard/gcc-final/./gcc/cc1 -fpreprocessed load_n.i -quiet >>>>>>>> -dumpbase load_n.c -march=armv8-a -mfloat-abi=hard -mfpu=fp-armv8 >>>>>>>> -mtls-dialect=gnu -auxbase-strip .libs/load_1_.o -g3 -O2 -Wall >>>>>>>> -Werror -version -fPIC -funwind-tables -o load_n.s >>>>>>>> >>>>>>>> >>>>>>>> The test.c is a simple test case to reproduce missing conditional >>>>>>>> code in mmap.c. >>>>>>>> >>>>>>>> Any suggestion ? >>>>>>> I reproduced the assembler failure with your patch. >>>>>>> >>>>>>> The reason is that for arm mode we use divided syntax, where the >>>>>>> condition field goes in a different place. So, while ldrbeq >>>>>>> r0,[r0] is >>>>>>> rejected, ldreqb r0, [r0] works. >>>>>>> Since we always use divided syntax for arm mode, I think you'll need >>>>>>> to put the condition field in the right place depending on arm or >>>>>>> thumb >>>>>>> mode. >>>>>>> Ugh, this is becoming ugly :( >>>>>>> >>>>>> Use %(<suffix%) around the bit that changes for unified/divided >>>>>> syntax. >>>>>> The compiler will then put the condition in the correct place. >>>>>> >>>>>> So: >>>>>> >>>>>> + return \"str%(<sync_sfx>%)\t%1, %0\"; >>>>>> >>>>>> R. >>>>>> >>>>>>> Kyrill >>>>>>> >>>>>>>> Shiva >>>>>>>> >>>>>>>> 2015-06-03 17:29 GMT+08:00 Shiva Chen <shiva0217@gmail.com>: >>>>>>>>> Hi, Ramana >>>>>>>>> >>>>>>>>> I'm not sure what copyright assignment means ? >>>>>>>>> >>>>>>>>> Does it mean the patch have copyright assignment or not ? >>>>>>>>> >>>>>>>>> I update the patch to add "predicable" and "predicable_short_it" >>>>>>>>> attribute as suggestion. >>>>>>>>> >>>>>>>>> However, I don't have svn write access yet. >>>>>>>>> >>>>>>>>> Shiva >>>>>>>>> >>>>>>>>> 2015-06-03 16:36 GMT+08:00 Kyrill Tkachov >>>>>>>>> <kyrylo.tkachov@arm.com>: >>>>>>>>>> On 03/06/15 09:32, Ramana Radhakrishnan wrote: >>>>>>>>>>>> This pattern is not predicable though, i.e. it doesn't have the >>>>>>>>>>>> "predicable" attribute set to "yes". >>>>>>>>>>>> Therefore the compiler should be trying to branch around here >>>>>>>>>>>> rather than try to do a cond_exec. >>>>>>>>>>>> Why does the generated code above look like it's converted to >>>>>>>>>>>> conditional execution? >>>>>>>>>>>> Could you produce a self-contained reduced testcase for this? >>>>>>>>>>> CCFSM state machine in ARM state. >>>>>>>>>>> >>>>>>>>>>> arm.c (final_prescan_insn). >>>>>>>>>> Ah ok. >>>>>>>>>> This patch makes sense then. >>>>>>>>>> As Ramana mentioned, please mark the pattern with "predicable" >>>>>>>>>> and >>>>>>>>>> also set the "predicable_short_it" attribute to "no" so that it >>>>>>>>>> will not be conditionalised in Thumb2 mode or when >>>>>>>>>> -mrestrict-it is >>>>>>>>>> enabled. >>>>>>>>>> >>>>>>>>>> Thanks, >>>>>>>>>> Kyrill >>>>>>>>>> >>>>>>>>>> >>>>>>>>>> >>>>>>>>>>> Ramana >>>>>>>>>>> >>>>>>>>>>>> Thanks, >>>>>>>>>>>> Kyrill >>>>>>>>>>>> >>>>>>>>>>>>> @@ -91,9 +91,9 @@ >>>>>>>>>>>>> { >>>>>>>>>>>>> enum memmodel model = memmodel_from_int (INTVAL >>>>>>>>>>>>> (operands[2])); >>>>>>>>>>>>> if (is_mm_relaxed (model) || is_mm_consume >>>>>>>>>>>>> (model) || >>>>>>>>>>>>> is_mm_acquire (model)) >>>>>>>>>>>>> - return \"str<sync_sfx>\t%1, %0\"; >>>>>>>>>>>>> + return \"str<sync_sfx>%?\t%1, %0\"; >>>>>>>>>>>>> else >>>>>>>>>>>>> - return \"stl<sync_sfx>\t%1, %0\"; >>>>>>>>>>>>> + return \"stl<sync_sfx>%?\t%1, %0\"; >>>>>>>>>>>>> } >>>>>>>>>>>>> ) >>>>>>>>>>>>> > ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code 2015-06-05 13:14 ` Richard Earnshaw @ 2015-06-05 14:02 ` Kyrill Tkachov 2015-06-09 8:44 ` Kyrill Tkachov 0 siblings, 1 reply; 21+ messages in thread From: Kyrill Tkachov @ 2015-06-05 14:02 UTC (permalink / raw) To: Richard Earnshaw, Shiva Chen Cc: Shiva Chen, Ramana Radhakrishnan, GCC Patches, nickc On 05/06/15 14:11, Richard Earnshaw wrote: > On 05/06/15 14:08, Kyrill Tkachov wrote: >> Hi Shiva, >> >> On 05/06/15 10:42, Shiva Chen wrote: >>> Hi, Kyrill >>> >>> I add the testcase as stl-cond.c. >>> >>> Could you help to check the testcase ? >>> >>> If it's OK, Could you help me to apply the patch ? >>> >> This looks ok to me. >> One nit on the testcase: >> >> diff --git a/gcc/testsuite/gcc.target/arm/stl-cond.c >> b/gcc/testsuite/gcc.target/arm/stl-cond.c >> new file mode 100755 >> index 0000000..44c6249 >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/arm/stl-cond.c >> @@ -0,0 +1,18 @@ >> +/* { dg-do compile } */ >> +/* { dg-require-effective-target arm_arch_v8a_ok } */ >> +/* { dg-options "-O2" } */ >> >> This should also have -marm as the problem exhibited itself in arm state. >> I'll commit this patch with this change in 24 hours on your behalf if no >> one >> objects. >> > Explicit use of -marm will break multi-lib testing. I've forgotten the > correct hook, but there's most-likely something that will give you the > right behaviour, even if it means that thumb-only multi-lib testing > skips this test. So I think what we want is: dg-require-effective-target arm_arm_ok The comment in target-supports.exp is: # Return 1 if this is an ARM target where -marm causes ARM to be # used (not Thumb) Kyrill > R. > >> Ramana, Richard, we need to backport it to GCC 5 as well, right? >> >> Thanks, >> Kyrill >> >> >>> Thanks, >>> >>> Shiva >>> >>> 2015-06-05 16:34 GMT+08:00 Kyrill Tkachov <kyrylo.tkachov@foss.arm.com>: >>>> Hi Shiva, >>>> >>>> On 05/06/15 09:29, Shiva Chen wrote: >>>>> Hi, Kyrill >>>>> >>>>> I update the patch as Richard's suggestion. >>>>> >>>>> - return \"str<sync_sfx>\t%1, %0\"; >>>>> + return \"str%(<sync_sfx>%)\t%1, %0\"; >>>>> else >>>>> - return \"stl<sync_sfx>\t%1, %0\"; >>>>> + return \"stl<sync_sfx>%?\t%1, %0\"; >>>>> } >>>>> -) >>>>> + [(set_attr "predicable" "yes") >>>>> + (set_attr "predicable_short_it" "no")]) >>>>> + [(set_attr "predicable" "yes") >>>>> + (set_attr "predicable_short_it" "no")]) >>>>> >>>>> >>>>> Let me sum up. >>>>> >>>>> We add predicable attribute to allow gcc do if-conversion in >>>>> ce1/ce2/ce3 not only in final phase by final_prescan_insn finite state >>>>> machine. >>>>> >>>>> We set predicalble_short_it to "no" to restrict conditional code >>>>> generation on armv8 with thumb mode. >>>>> >>>>> However, we could use the flags -mno-restrict-it to force generating >>>>> conditional code on thumb mode. >>>>> >>>>> Therefore, we have to consider the assembly output format for strb >>>>> with condition code on arm/thumb mode. >>>>> >>>>> Because arm/thumb mode use different syntax for strb, >>>>> we output the assembly as str%(<sync_sfx>%) >>>>> which will put the condition code in the right place according to >>>>> TARGET_UNIFIED_ASM. >>>>> >>>>> Is there still missing something ? >>>> That's all correct, and well summarised :) >>>> The patch looks good to me, but please include the testcase >>>> (test.c from earlier) appropriately marked up for the testsuite. >>>> I think to the level of dg-assemble, just so we know everything is >>>> wired up properly. >>>> >>>> Thanks for dealing with this. >>>> Kyrill >>>> >>>> >>>>> Thanks, >>>>> >>>>> Shiva >>>>> >>>>> 2015-06-04 18:00 GMT+08:00 Kyrill Tkachov >>>>> <kyrylo.tkachov@foss.arm.com>: >>>>>> Hi Shiva, >>>>>> >>>>>> On 04/06/15 10:57, Shiva Chen wrote: >>>>>>> Hi, Kyrill >>>>>>> >>>>>>> Thanks for the tips of syntax. >>>>>>> >>>>>>> It seems that correct syntax for >>>>>>> >>>>>>> ldrb with condition code is ldreqb >>>>>>> >>>>>>> ldab with condition code is ldabeq >>>>>>> >>>>>>> >>>>>>> So I modified the pattern as follow >>>>>>> >>>>>>> { >>>>>>> enum memmodel model = (enum memmodel) INTVAL (operands[2]); >>>>>>> if (model == MEMMODEL_RELAXED >>>>>>> || model == MEMMODEL_CONSUME >>>>>>> || model == MEMMODEL_RELEASE) >>>>>>> return \"ldr%?<sync_sfx>\\t%0, %1\"; >>>>>>> else >>>>>>> return \"lda<sync_sfx>%?\\t%0, %1\"; >>>>>>> } >>>>>>> [(set_attr "predicable" "yes") >>>>>>> (set_attr "predicable_short_it" "no")]) >>>>>>> >>>>>>> It seems we don't have to worry about thumb mode, >>>>>> I suggest you use Richard's suggestion from: >>>>>> https://gcc.gnu.org/ml/gcc-patches/2015-06/msg00384.html >>>>>> to write this in a clean way. >>>>>> >>>>>>> Because we already set "predicable" "yes" and predicable_short_it" >>>>>>> "no" >>>>>>> for the pattern. >>>>>> That's not quite true. The user may compile for armv8-a with >>>>>> -mno-restrict-it which will turn off this >>>>>> restriction for Thumb and allow the conditional execution of this. >>>>>> In any case, I think Richard's suggestion above should work. >>>>>> >>>>>> Thanks, >>>>>> Kyrill >>>>>> >>>>>> >>>>>>> The new patch could build gcc and run gcc regression test >>>>>>> successfully. >>>>>>> >>>>>>> Please correct me if I still missing something. >>>>>>> >>>>>>> Thanks, >>>>>>> >>>>>>> Shiva >>>>>>> >>>>>>> -----Original Message----- >>>>>>> From: Richard Earnshaw [mailto:Richard.Earnshaw@foss.arm.com] >>>>>>> Sent: Thursday, June 04, 2015 4:42 PM >>>>>>> To: Kyrill Tkachov; Shiva Chen >>>>>>> Cc: Ramana Radhakrishnan; GCC Patches; nickc@redhat.com; Shiva Chen >>>>>>> Subject: Re: [GCC, ARM] armv8 linux toolchain asan testcase fail >>>>>>> due to >>>>>>> stl missing conditional code >>>>>>> >>>>>>> On 04/06/15 09:17, Kyrill Tkachov wrote: >>>>>>>> Hi Shiva, >>>>>>>> >>>>>>>> On 04/06/15 04:13, Shiva Chen wrote: >>>>>>>>> Hi, Ramana >>>>>>>>> >>>>>>>>> Currently, I work for Marvell and the company have copyright >>>>>>>>> assignment >>>>>>>>> on file. >>>>>>>>> >>>>>>>>> Hi, all >>>>>>>>> >>>>>>>>> After adding the attribute and rebuild gcc, I got the assembler >>>>>>>>> error >>>>>>>>> message >>>>>>>>> >>>>>>>>> load_n.s:39: Error: bad instruction `ldrbeq r0,[r0]' >>>>>>>>> >>>>>>>>> When i look into armv8 ISA document, it seems ldrb Encoding A1 have >>>>>>>>> conditional code field. >>>>>>>>> >>>>>>>>> Does it mean we should also patch assembler or I just miss >>>>>>>>> understanding something ? >>>>>>>>> >>>>>>>>> Following command use to generate load_n.s: >>>>>>>>> >>>>>>>>> /home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnu >>>>>>>>> >>>>>>>>> eabihf-hard/gcc-final/./gcc/cc1 -fpreprocessed load_n.i -quiet >>>>>>>>> -dumpbase load_n.c -march=armv8-a -mfloat-abi=hard -mfpu=fp-armv8 >>>>>>>>> -mtls-dialect=gnu -auxbase-strip .libs/load_1_.o -g3 -O2 -Wall >>>>>>>>> -Werror -version -fPIC -funwind-tables -o load_n.s >>>>>>>>> >>>>>>>>> >>>>>>>>> The test.c is a simple test case to reproduce missing conditional >>>>>>>>> code in mmap.c. >>>>>>>>> >>>>>>>>> Any suggestion ? >>>>>>>> I reproduced the assembler failure with your patch. >>>>>>>> >>>>>>>> The reason is that for arm mode we use divided syntax, where the >>>>>>>> condition field goes in a different place. So, while ldrbeq >>>>>>>> r0,[r0] is >>>>>>>> rejected, ldreqb r0, [r0] works. >>>>>>>> Since we always use divided syntax for arm mode, I think you'll need >>>>>>>> to put the condition field in the right place depending on arm or >>>>>>>> thumb >>>>>>>> mode. >>>>>>>> Ugh, this is becoming ugly :( >>>>>>>> >>>>>>> Use %(<suffix%) around the bit that changes for unified/divided >>>>>>> syntax. >>>>>>> The compiler will then put the condition in the correct place. >>>>>>> >>>>>>> So: >>>>>>> >>>>>>> + return \"str%(<sync_sfx>%)\t%1, %0\"; >>>>>>> >>>>>>> R. >>>>>>> >>>>>>>> Kyrill >>>>>>>> >>>>>>>>> Shiva >>>>>>>>> >>>>>>>>> 2015-06-03 17:29 GMT+08:00 Shiva Chen <shiva0217@gmail.com>: >>>>>>>>>> Hi, Ramana >>>>>>>>>> >>>>>>>>>> I'm not sure what copyright assignment means ? >>>>>>>>>> >>>>>>>>>> Does it mean the patch have copyright assignment or not ? >>>>>>>>>> >>>>>>>>>> I update the patch to add "predicable" and "predicable_short_it" >>>>>>>>>> attribute as suggestion. >>>>>>>>>> >>>>>>>>>> However, I don't have svn write access yet. >>>>>>>>>> >>>>>>>>>> Shiva >>>>>>>>>> >>>>>>>>>> 2015-06-03 16:36 GMT+08:00 Kyrill Tkachov >>>>>>>>>> <kyrylo.tkachov@arm.com>: >>>>>>>>>>> On 03/06/15 09:32, Ramana Radhakrishnan wrote: >>>>>>>>>>>>> This pattern is not predicable though, i.e. it doesn't have the >>>>>>>>>>>>> "predicable" attribute set to "yes". >>>>>>>>>>>>> Therefore the compiler should be trying to branch around here >>>>>>>>>>>>> rather than try to do a cond_exec. >>>>>>>>>>>>> Why does the generated code above look like it's converted to >>>>>>>>>>>>> conditional execution? >>>>>>>>>>>>> Could you produce a self-contained reduced testcase for this? >>>>>>>>>>>> CCFSM state machine in ARM state. >>>>>>>>>>>> >>>>>>>>>>>> arm.c (final_prescan_insn). >>>>>>>>>>> Ah ok. >>>>>>>>>>> This patch makes sense then. >>>>>>>>>>> As Ramana mentioned, please mark the pattern with "predicable" >>>>>>>>>>> and >>>>>>>>>>> also set the "predicable_short_it" attribute to "no" so that it >>>>>>>>>>> will not be conditionalised in Thumb2 mode or when >>>>>>>>>>> -mrestrict-it is >>>>>>>>>>> enabled. >>>>>>>>>>> >>>>>>>>>>> Thanks, >>>>>>>>>>> Kyrill >>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>>> Ramana >>>>>>>>>>>> >>>>>>>>>>>>> Thanks, >>>>>>>>>>>>> Kyrill >>>>>>>>>>>>> >>>>>>>>>>>>>> @@ -91,9 +91,9 @@ >>>>>>>>>>>>>> { >>>>>>>>>>>>>> enum memmodel model = memmodel_from_int (INTVAL >>>>>>>>>>>>>> (operands[2])); >>>>>>>>>>>>>> if (is_mm_relaxed (model) || is_mm_consume >>>>>>>>>>>>>> (model) || >>>>>>>>>>>>>> is_mm_acquire (model)) >>>>>>>>>>>>>> - return \"str<sync_sfx>\t%1, %0\"; >>>>>>>>>>>>>> + return \"str<sync_sfx>%?\t%1, %0\"; >>>>>>>>>>>>>> else >>>>>>>>>>>>>> - return \"stl<sync_sfx>\t%1, %0\"; >>>>>>>>>>>>>> + return \"stl<sync_sfx>%?\t%1, %0\"; >>>>>>>>>>>>>> } >>>>>>>>>>>>>> ) >>>>>>>>>>>>>> ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code 2015-06-05 14:02 ` Kyrill Tkachov @ 2015-06-09 8:44 ` Kyrill Tkachov 2015-09-30 17:10 ` Kyrill Tkachov 0 siblings, 1 reply; 21+ messages in thread From: Kyrill Tkachov @ 2015-06-09 8:44 UTC (permalink / raw) To: Richard Earnshaw, Shiva Chen Cc: Shiva Chen, Ramana Radhakrishnan, GCC Patches, nickc [-- Attachment #1: Type: text/plain, Size: 10754 bytes --] On 05/06/15 14:14, Kyrill Tkachov wrote: > > On 05/06/15 14:11, Richard Earnshaw wrote: >> On 05/06/15 14:08, Kyrill Tkachov wrote: >>> Hi Shiva, >>> >>> On 05/06/15 10:42, Shiva Chen wrote: >>>> Hi, Kyrill >>>> >>>> I add the testcase as stl-cond.c. >>>> >>>> Could you help to check the testcase ? >>>> >>>> If it's OK, Could you help me to apply the patch ? >>>> >>> This looks ok to me. >>> One nit on the testcase: >>> >>> diff --git a/gcc/testsuite/gcc.target/arm/stl-cond.c >>> b/gcc/testsuite/gcc.target/arm/stl-cond.c >>> new file mode 100755 >>> index 0000000..44c6249 >>> --- /dev/null >>> +++ b/gcc/testsuite/gcc.target/arm/stl-cond.c >>> @@ -0,0 +1,18 @@ >>> +/* { dg-do compile } */ >>> +/* { dg-require-effective-target arm_arch_v8a_ok } */ >>> +/* { dg-options "-O2" } */ >>> >>> This should also have -marm as the problem exhibited itself in arm state. >>> I'll commit this patch with this change in 24 hours on your behalf if no >>> one >>> objects. >>> >> Explicit use of -marm will break multi-lib testing. I've forgotten the >> correct hook, but there's most-likely something that will give you the >> right behaviour, even if it means that thumb-only multi-lib testing >> skips this test. > > So I think what we want is: > > dg-require-effective-target arm_arm_ok > > The comment in target-supports.exp is: > # Return 1 if this is an ARM target where -marm causes ARM to be > # used (not Thumb) > I've committed the attached patch to trunk on Shiva's behalf with r224269. It gates the test on arm_arm_ok and adds -marm, like other similar tests. The ChangeLog I used is below: 2015-06-09 Shiva Chen <shiva0217@gmail.com> * sync.md (atomic_load<mode>): Add conditional code for lda/ldr (atomic_store<mode>): Likewise. 2015-06-09 Shiva Chen <shiva0217@gmail.com> * gcc.target/arm/stl-cond.c: New test. Thanks, Kyrill > Kyrill > > >> R. >> >>> Ramana, Richard, we need to backport it to GCC 5 as well, right? >>> >>> Thanks, >>> Kyrill >>> >>> >>>> Thanks, >>>> >>>> Shiva >>>> >>>> 2015-06-05 16:34 GMT+08:00 Kyrill Tkachov <kyrylo.tkachov@foss.arm.com>: >>>>> Hi Shiva, >>>>> >>>>> On 05/06/15 09:29, Shiva Chen wrote: >>>>>> Hi, Kyrill >>>>>> >>>>>> I update the patch as Richard's suggestion. >>>>>> >>>>>> - return \"str<sync_sfx>\t%1, %0\"; >>>>>> + return \"str%(<sync_sfx>%)\t%1, %0\"; >>>>>> else >>>>>> - return \"stl<sync_sfx>\t%1, %0\"; >>>>>> + return \"stl<sync_sfx>%?\t%1, %0\"; >>>>>> } >>>>>> -) >>>>>> + [(set_attr "predicable" "yes") >>>>>> + (set_attr "predicable_short_it" "no")]) >>>>>> + [(set_attr "predicable" "yes") >>>>>> + (set_attr "predicable_short_it" "no")]) >>>>>> >>>>>> >>>>>> Let me sum up. >>>>>> >>>>>> We add predicable attribute to allow gcc do if-conversion in >>>>>> ce1/ce2/ce3 not only in final phase by final_prescan_insn finite state >>>>>> machine. >>>>>> >>>>>> We set predicalble_short_it to "no" to restrict conditional code >>>>>> generation on armv8 with thumb mode. >>>>>> >>>>>> However, we could use the flags -mno-restrict-it to force generating >>>>>> conditional code on thumb mode. >>>>>> >>>>>> Therefore, we have to consider the assembly output format for strb >>>>>> with condition code on arm/thumb mode. >>>>>> >>>>>> Because arm/thumb mode use different syntax for strb, >>>>>> we output the assembly as str%(<sync_sfx>%) >>>>>> which will put the condition code in the right place according to >>>>>> TARGET_UNIFIED_ASM. >>>>>> >>>>>> Is there still missing something ? >>>>> That's all correct, and well summarised :) >>>>> The patch looks good to me, but please include the testcase >>>>> (test.c from earlier) appropriately marked up for the testsuite. >>>>> I think to the level of dg-assemble, just so we know everything is >>>>> wired up properly. >>>>> >>>>> Thanks for dealing with this. >>>>> Kyrill >>>>> >>>>> >>>>>> Thanks, >>>>>> >>>>>> Shiva >>>>>> >>>>>> 2015-06-04 18:00 GMT+08:00 Kyrill Tkachov >>>>>> <kyrylo.tkachov@foss.arm.com>: >>>>>>> Hi Shiva, >>>>>>> >>>>>>> On 04/06/15 10:57, Shiva Chen wrote: >>>>>>>> Hi, Kyrill >>>>>>>> >>>>>>>> Thanks for the tips of syntax. >>>>>>>> >>>>>>>> It seems that correct syntax for >>>>>>>> >>>>>>>> ldrb with condition code is ldreqb >>>>>>>> >>>>>>>> ldab with condition code is ldabeq >>>>>>>> >>>>>>>> >>>>>>>> So I modified the pattern as follow >>>>>>>> >>>>>>>> { >>>>>>>> enum memmodel model = (enum memmodel) INTVAL (operands[2]); >>>>>>>> if (model == MEMMODEL_RELAXED >>>>>>>> || model == MEMMODEL_CONSUME >>>>>>>> || model == MEMMODEL_RELEASE) >>>>>>>> return \"ldr%?<sync_sfx>\\t%0, %1\"; >>>>>>>> else >>>>>>>> return \"lda<sync_sfx>%?\\t%0, %1\"; >>>>>>>> } >>>>>>>> [(set_attr "predicable" "yes") >>>>>>>> (set_attr "predicable_short_it" "no")]) >>>>>>>> >>>>>>>> It seems we don't have to worry about thumb mode, >>>>>>> I suggest you use Richard's suggestion from: >>>>>>> https://gcc.gnu.org/ml/gcc-patches/2015-06/msg00384.html >>>>>>> to write this in a clean way. >>>>>>> >>>>>>>> Because we already set "predicable" "yes" and predicable_short_it" >>>>>>>> "no" >>>>>>>> for the pattern. >>>>>>> That's not quite true. The user may compile for armv8-a with >>>>>>> -mno-restrict-it which will turn off this >>>>>>> restriction for Thumb and allow the conditional execution of this. >>>>>>> In any case, I think Richard's suggestion above should work. >>>>>>> >>>>>>> Thanks, >>>>>>> Kyrill >>>>>>> >>>>>>> >>>>>>>> The new patch could build gcc and run gcc regression test >>>>>>>> successfully. >>>>>>>> >>>>>>>> Please correct me if I still missing something. >>>>>>>> >>>>>>>> Thanks, >>>>>>>> >>>>>>>> Shiva >>>>>>>> >>>>>>>> -----Original Message----- >>>>>>>> From: Richard Earnshaw [mailto:Richard.Earnshaw@foss.arm.com] >>>>>>>> Sent: Thursday, June 04, 2015 4:42 PM >>>>>>>> To: Kyrill Tkachov; Shiva Chen >>>>>>>> Cc: Ramana Radhakrishnan; GCC Patches; nickc@redhat.com; Shiva Chen >>>>>>>> Subject: Re: [GCC, ARM] armv8 linux toolchain asan testcase fail >>>>>>>> due to >>>>>>>> stl missing conditional code >>>>>>>> >>>>>>>> On 04/06/15 09:17, Kyrill Tkachov wrote: >>>>>>>>> Hi Shiva, >>>>>>>>> >>>>>>>>> On 04/06/15 04:13, Shiva Chen wrote: >>>>>>>>>> Hi, Ramana >>>>>>>>>> >>>>>>>>>> Currently, I work for Marvell and the company have copyright >>>>>>>>>> assignment >>>>>>>>>> on file. >>>>>>>>>> >>>>>>>>>> Hi, all >>>>>>>>>> >>>>>>>>>> After adding the attribute and rebuild gcc, I got the assembler >>>>>>>>>> error >>>>>>>>>> message >>>>>>>>>> >>>>>>>>>> load_n.s:39: Error: bad instruction `ldrbeq r0,[r0]' >>>>>>>>>> >>>>>>>>>> When i look into armv8 ISA document, it seems ldrb Encoding A1 have >>>>>>>>>> conditional code field. >>>>>>>>>> >>>>>>>>>> Does it mean we should also patch assembler or I just miss >>>>>>>>>> understanding something ? >>>>>>>>>> >>>>>>>>>> Following command use to generate load_n.s: >>>>>>>>>> >>>>>>>>>> /home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnu >>>>>>>>>> >>>>>>>>>> eabihf-hard/gcc-final/./gcc/cc1 -fpreprocessed load_n.i -quiet >>>>>>>>>> -dumpbase load_n.c -march=armv8-a -mfloat-abi=hard -mfpu=fp-armv8 >>>>>>>>>> -mtls-dialect=gnu -auxbase-strip .libs/load_1_.o -g3 -O2 -Wall >>>>>>>>>> -Werror -version -fPIC -funwind-tables -o load_n.s >>>>>>>>>> >>>>>>>>>> >>>>>>>>>> The test.c is a simple test case to reproduce missing conditional >>>>>>>>>> code in mmap.c. >>>>>>>>>> >>>>>>>>>> Any suggestion ? >>>>>>>>> I reproduced the assembler failure with your patch. >>>>>>>>> >>>>>>>>> The reason is that for arm mode we use divided syntax, where the >>>>>>>>> condition field goes in a different place. So, while ldrbeq >>>>>>>>> r0,[r0] is >>>>>>>>> rejected, ldreqb r0, [r0] works. >>>>>>>>> Since we always use divided syntax for arm mode, I think you'll need >>>>>>>>> to put the condition field in the right place depending on arm or >>>>>>>>> thumb >>>>>>>>> mode. >>>>>>>>> Ugh, this is becoming ugly :( >>>>>>>>> >>>>>>>> Use %(<suffix%) around the bit that changes for unified/divided >>>>>>>> syntax. >>>>>>>> The compiler will then put the condition in the correct place. >>>>>>>> >>>>>>>> So: >>>>>>>> >>>>>>>> + return \"str%(<sync_sfx>%)\t%1, %0\"; >>>>>>>> >>>>>>>> R. >>>>>>>> >>>>>>>>> Kyrill >>>>>>>>> >>>>>>>>>> Shiva >>>>>>>>>> >>>>>>>>>> 2015-06-03 17:29 GMT+08:00 Shiva Chen <shiva0217@gmail.com>: >>>>>>>>>>> Hi, Ramana >>>>>>>>>>> >>>>>>>>>>> I'm not sure what copyright assignment means ? >>>>>>>>>>> >>>>>>>>>>> Does it mean the patch have copyright assignment or not ? >>>>>>>>>>> >>>>>>>>>>> I update the patch to add "predicable" and "predicable_short_it" >>>>>>>>>>> attribute as suggestion. >>>>>>>>>>> >>>>>>>>>>> However, I don't have svn write access yet. >>>>>>>>>>> >>>>>>>>>>> Shiva >>>>>>>>>>> >>>>>>>>>>> 2015-06-03 16:36 GMT+08:00 Kyrill Tkachov >>>>>>>>>>> <kyrylo.tkachov@arm.com>: >>>>>>>>>>>> On 03/06/15 09:32, Ramana Radhakrishnan wrote: >>>>>>>>>>>>>> This pattern is not predicable though, i.e. it doesn't have the >>>>>>>>>>>>>> "predicable" attribute set to "yes". >>>>>>>>>>>>>> Therefore the compiler should be trying to branch around here >>>>>>>>>>>>>> rather than try to do a cond_exec. >>>>>>>>>>>>>> Why does the generated code above look like it's converted to >>>>>>>>>>>>>> conditional execution? >>>>>>>>>>>>>> Could you produce a self-contained reduced testcase for this? >>>>>>>>>>>>> CCFSM state machine in ARM state. >>>>>>>>>>>>> >>>>>>>>>>>>> arm.c (final_prescan_insn). >>>>>>>>>>>> Ah ok. >>>>>>>>>>>> This patch makes sense then. >>>>>>>>>>>> As Ramana mentioned, please mark the pattern with "predicable" >>>>>>>>>>>> and >>>>>>>>>>>> also set the "predicable_short_it" attribute to "no" so that it >>>>>>>>>>>> will not be conditionalised in Thumb2 mode or when >>>>>>>>>>>> -mrestrict-it is >>>>>>>>>>>> enabled. >>>>>>>>>>>> >>>>>>>>>>>> Thanks, >>>>>>>>>>>> Kyrill >>>>>>>>>>>> >>>>>>>>>>>> >>>>>>>>>>>> >>>>>>>>>>>>> Ramana >>>>>>>>>>>>> >>>>>>>>>>>>>> Thanks, >>>>>>>>>>>>>> Kyrill >>>>>>>>>>>>>> >>>>>>>>>>>>>>> @@ -91,9 +91,9 @@ >>>>>>>>>>>>>>> { >>>>>>>>>>>>>>> enum memmodel model = memmodel_from_int (INTVAL >>>>>>>>>>>>>>> (operands[2])); >>>>>>>>>>>>>>> if (is_mm_relaxed (model) || is_mm_consume >>>>>>>>>>>>>>> (model) || >>>>>>>>>>>>>>> is_mm_acquire (model)) >>>>>>>>>>>>>>> - return \"str<sync_sfx>\t%1, %0\"; >>>>>>>>>>>>>>> + return \"str<sync_sfx>%?\t%1, %0\"; >>>>>>>>>>>>>>> else >>>>>>>>>>>>>>> - return \"stl<sync_sfx>\t%1, %0\"; >>>>>>>>>>>>>>> + return \"stl<sync_sfx>%?\t%1, %0\"; >>>>>>>>>>>>>>> } >>>>>>>>>>>>>>> ) >>>>>>>>>>>>>>> > [-- Attachment #2: Fix_slt_lda_missing_conditional_code.diff --] [-- Type: text/x-patch, Size: 2004 bytes --] diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md index 44cda61..75dd52e 100644 --- a/gcc/config/arm/sync.md +++ b/gcc/config/arm/sync.md @@ -75,11 +75,12 @@ (define_insn "atomic_load<mode>" { enum memmodel model = memmodel_from_int (INTVAL (operands[2])); if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_release (model)) - return \"ldr<sync_sfx>\\t%0, %1\"; + return \"ldr%(<sync_sfx>%)\\t%0, %1\"; else - return \"lda<sync_sfx>\\t%0, %1\"; + return \"lda<sync_sfx>%?\\t%0, %1\"; } -) + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no")]) (define_insn "atomic_store<mode>" [(set (match_operand:QHSI 0 "memory_operand" "=Q") @@ -91,11 +92,12 @@ (define_insn "atomic_store<mode>" { enum memmodel model = memmodel_from_int (INTVAL (operands[2])); if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_acquire (model)) - return \"str<sync_sfx>\t%1, %0\"; + return \"str%(<sync_sfx>%)\t%1, %0\"; else - return \"stl<sync_sfx>\t%1, %0\"; + return \"stl<sync_sfx>%?\t%1, %0\"; } -) + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no")]) ;; Note that ldrd and vldr are *not* guaranteed to be single-copy atomic, ;; even for a 64-bit aligned address. Instead we use a ldrexd unparied diff --git a/gcc/testsuite/gcc.target/arm/stl-cond.c b/gcc/testsuite/gcc.target/arm/stl-cond.c new file mode 100644 index 0000000..de14bb5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/stl-cond.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arm_ok } */ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-options "-O2 -marm" } */ +/* { dg-add-options arm_arch_v8a } */ + +struct backtrace_state +{ + int threaded; + int lock_alloc; +}; + +void foo (struct backtrace_state *state) +{ + if (state->threaded) + __sync_lock_release (&state->lock_alloc); +} + +/* { dg-final { scan-assembler "stlne" } } */ ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code 2015-06-09 8:44 ` Kyrill Tkachov @ 2015-09-30 17:10 ` Kyrill Tkachov 2015-10-01 9:10 ` Kyrill Tkachov 0 siblings, 1 reply; 21+ messages in thread From: Kyrill Tkachov @ 2015-09-30 17:10 UTC (permalink / raw) To: Richard Earnshaw, Shiva Chen Cc: Shiva Chen, Ramana Radhakrishnan, GCC Patches, nickc [-- Attachment #1: Type: text/plain, Size: 12199 bytes --] On 09/06/15 09:17, Kyrill Tkachov wrote: > On 05/06/15 14:14, Kyrill Tkachov wrote: >> On 05/06/15 14:11, Richard Earnshaw wrote: >>> On 05/06/15 14:08, Kyrill Tkachov wrote: >>>> Hi Shiva, >>>> >>>> On 05/06/15 10:42, Shiva Chen wrote: >>>>> Hi, Kyrill >>>>> >>>>> I add the testcase as stl-cond.c. >>>>> >>>>> Could you help to check the testcase ? >>>>> >>>>> If it's OK, Could you help me to apply the patch ? >>>>> >>>> This looks ok to me. >>>> One nit on the testcase: >>>> >>>> diff --git a/gcc/testsuite/gcc.target/arm/stl-cond.c >>>> b/gcc/testsuite/gcc.target/arm/stl-cond.c >>>> new file mode 100755 >>>> index 0000000..44c6249 >>>> --- /dev/null >>>> +++ b/gcc/testsuite/gcc.target/arm/stl-cond.c >>>> @@ -0,0 +1,18 @@ >>>> +/* { dg-do compile } */ >>>> +/* { dg-require-effective-target arm_arch_v8a_ok } */ >>>> +/* { dg-options "-O2" } */ >>>> >>>> This should also have -marm as the problem exhibited itself in arm state. >>>> I'll commit this patch with this change in 24 hours on your behalf if no >>>> one >>>> objects. >>>> >>> Explicit use of -marm will break multi-lib testing. I've forgotten the >>> correct hook, but there's most-likely something that will give you the >>> right behaviour, even if it means that thumb-only multi-lib testing >>> skips this test. >> So I think what we want is: >> >> dg-require-effective-target arm_arm_ok >> >> The comment in target-supports.exp is: >> # Return 1 if this is an ARM target where -marm causes ARM to be >> # used (not Thumb) >> > I've committed the attached patch to trunk on Shiva's behalf with r224269. > It gates the test on arm_arm_ok and adds -marm, like other similar tests. > The ChangeLog I used is below: I'd like to backport this to GCC 5 and 4.9 The patch applies and tests cleanly on GCC 5. On 4.9 it needs some minor changes, which I'm attaching here. I've bootstrapped and tested this patch on 4.9 and the Shiva's original patch on GCC 5. 2015-09-30 Kyrylo Tkachov <kyrylo.tkachov@arm> Backport from mainline 2015-06-09 Shiva Chen <shiva0217@gmail.com> * sync.md (atomic_load<mode>): Add conditional code for lda/ldr (atomic_store<mode>): Likewise. 2015-09-30 Kyrylo Tkachov <kyrylo.tkachov@arm> Backport from mainline 2015-06-09 Shiva Chen <shiva0217@gmail.com> * gcc.target/arm/stl-cond.c: New test. I'll commit them tomorrow. Thanks, Kyrill > > 2015-06-09 Shiva Chen <shiva0217@gmail.com> > > * sync.md (atomic_load<mode>): Add conditional code for lda/ldr > (atomic_store<mode>): Likewise. > > 2015-06-09 Shiva Chen <shiva0217@gmail.com> > > * gcc.target/arm/stl-cond.c: New test. > > > Thanks, > Kyrill > >> Kyrill >> >> >>> R. >>> >>>> Ramana, Richard, we need to backport it to GCC 5 as well, right? >>>> >>>> Thanks, >>>> Kyrill >>>> >>>> >>>>> Thanks, >>>>> >>>>> Shiva >>>>> >>>>> 2015-06-05 16:34 GMT+08:00 Kyrill Tkachov <kyrylo.tkachov@foss.arm.com>: >>>>>> Hi Shiva, >>>>>> >>>>>> On 05/06/15 09:29, Shiva Chen wrote: >>>>>>> Hi, Kyrill >>>>>>> >>>>>>> I update the patch as Richard's suggestion. >>>>>>> >>>>>>> - return \"str<sync_sfx>\t%1, %0\"; >>>>>>> + return \"str%(<sync_sfx>%)\t%1, %0\"; >>>>>>> else >>>>>>> - return \"stl<sync_sfx>\t%1, %0\"; >>>>>>> + return \"stl<sync_sfx>%?\t%1, %0\"; >>>>>>> } >>>>>>> -) >>>>>>> + [(set_attr "predicable" "yes") >>>>>>> + (set_attr "predicable_short_it" "no")]) >>>>>>> + [(set_attr "predicable" "yes") >>>>>>> + (set_attr "predicable_short_it" "no")]) >>>>>>> >>>>>>> >>>>>>> Let me sum up. >>>>>>> >>>>>>> We add predicable attribute to allow gcc do if-conversion in >>>>>>> ce1/ce2/ce3 not only in final phase by final_prescan_insn finite state >>>>>>> machine. >>>>>>> >>>>>>> We set predicalble_short_it to "no" to restrict conditional code >>>>>>> generation on armv8 with thumb mode. >>>>>>> >>>>>>> However, we could use the flags -mno-restrict-it to force generating >>>>>>> conditional code on thumb mode. >>>>>>> >>>>>>> Therefore, we have to consider the assembly output format for strb >>>>>>> with condition code on arm/thumb mode. >>>>>>> >>>>>>> Because arm/thumb mode use different syntax for strb, >>>>>>> we output the assembly as str%(<sync_sfx>%) >>>>>>> which will put the condition code in the right place according to >>>>>>> TARGET_UNIFIED_ASM. >>>>>>> >>>>>>> Is there still missing something ? >>>>>> That's all correct, and well summarised :) >>>>>> The patch looks good to me, but please include the testcase >>>>>> (test.c from earlier) appropriately marked up for the testsuite. >>>>>> I think to the level of dg-assemble, just so we know everything is >>>>>> wired up properly. >>>>>> >>>>>> Thanks for dealing with this. >>>>>> Kyrill >>>>>> >>>>>> >>>>>>> Thanks, >>>>>>> >>>>>>> Shiva >>>>>>> >>>>>>> 2015-06-04 18:00 GMT+08:00 Kyrill Tkachov >>>>>>> <kyrylo.tkachov@foss.arm.com>: >>>>>>>> Hi Shiva, >>>>>>>> >>>>>>>> On 04/06/15 10:57, Shiva Chen wrote: >>>>>>>>> Hi, Kyrill >>>>>>>>> >>>>>>>>> Thanks for the tips of syntax. >>>>>>>>> >>>>>>>>> It seems that correct syntax for >>>>>>>>> >>>>>>>>> ldrb with condition code is ldreqb >>>>>>>>> >>>>>>>>> ldab with condition code is ldabeq >>>>>>>>> >>>>>>>>> >>>>>>>>> So I modified the pattern as follow >>>>>>>>> >>>>>>>>> { >>>>>>>>> enum memmodel model = (enum memmodel) INTVAL (operands[2]); >>>>>>>>> if (model == MEMMODEL_RELAXED >>>>>>>>> || model == MEMMODEL_CONSUME >>>>>>>>> || model == MEMMODEL_RELEASE) >>>>>>>>> return \"ldr%?<sync_sfx>\\t%0, %1\"; >>>>>>>>> else >>>>>>>>> return \"lda<sync_sfx>%?\\t%0, %1\"; >>>>>>>>> } >>>>>>>>> [(set_attr "predicable" "yes") >>>>>>>>> (set_attr "predicable_short_it" "no")]) >>>>>>>>> >>>>>>>>> It seems we don't have to worry about thumb mode, >>>>>>>> I suggest you use Richard's suggestion from: >>>>>>>> https://gcc.gnu.org/ml/gcc-patches/2015-06/msg00384.html >>>>>>>> to write this in a clean way. >>>>>>>> >>>>>>>>> Because we already set "predicable" "yes" and predicable_short_it" >>>>>>>>> "no" >>>>>>>>> for the pattern. >>>>>>>> That's not quite true. The user may compile for armv8-a with >>>>>>>> -mno-restrict-it which will turn off this >>>>>>>> restriction for Thumb and allow the conditional execution of this. >>>>>>>> In any case, I think Richard's suggestion above should work. >>>>>>>> >>>>>>>> Thanks, >>>>>>>> Kyrill >>>>>>>> >>>>>>>> >>>>>>>>> The new patch could build gcc and run gcc regression test >>>>>>>>> successfully. >>>>>>>>> >>>>>>>>> Please correct me if I still missing something. >>>>>>>>> >>>>>>>>> Thanks, >>>>>>>>> >>>>>>>>> Shiva >>>>>>>>> >>>>>>>>> -----Original Message----- >>>>>>>>> From: Richard Earnshaw [mailto:Richard.Earnshaw@foss.arm.com] >>>>>>>>> Sent: Thursday, June 04, 2015 4:42 PM >>>>>>>>> To: Kyrill Tkachov; Shiva Chen >>>>>>>>> Cc: Ramana Radhakrishnan; GCC Patches; nickc@redhat.com; Shiva Chen >>>>>>>>> Subject: Re: [GCC, ARM] armv8 linux toolchain asan testcase fail >>>>>>>>> due to >>>>>>>>> stl missing conditional code >>>>>>>>> >>>>>>>>> On 04/06/15 09:17, Kyrill Tkachov wrote: >>>>>>>>>> Hi Shiva, >>>>>>>>>> >>>>>>>>>> On 04/06/15 04:13, Shiva Chen wrote: >>>>>>>>>>> Hi, Ramana >>>>>>>>>>> >>>>>>>>>>> Currently, I work for Marvell and the company have copyright >>>>>>>>>>> assignment >>>>>>>>>>> on file. >>>>>>>>>>> >>>>>>>>>>> Hi, all >>>>>>>>>>> >>>>>>>>>>> After adding the attribute and rebuild gcc, I got the assembler >>>>>>>>>>> error >>>>>>>>>>> message >>>>>>>>>>> >>>>>>>>>>> load_n.s:39: Error: bad instruction `ldrbeq r0,[r0]' >>>>>>>>>>> >>>>>>>>>>> When i look into armv8 ISA document, it seems ldrb Encoding A1 have >>>>>>>>>>> conditional code field. >>>>>>>>>>> >>>>>>>>>>> Does it mean we should also patch assembler or I just miss >>>>>>>>>>> understanding something ? >>>>>>>>>>> >>>>>>>>>>> Following command use to generate load_n.s: >>>>>>>>>>> >>>>>>>>>>> /home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnu >>>>>>>>>>> >>>>>>>>>>> eabihf-hard/gcc-final/./gcc/cc1 -fpreprocessed load_n.i -quiet >>>>>>>>>>> -dumpbase load_n.c -march=armv8-a -mfloat-abi=hard -mfpu=fp-armv8 >>>>>>>>>>> -mtls-dialect=gnu -auxbase-strip .libs/load_1_.o -g3 -O2 -Wall >>>>>>>>>>> -Werror -version -fPIC -funwind-tables -o load_n.s >>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> The test.c is a simple test case to reproduce missing conditional >>>>>>>>>>> code in mmap.c. >>>>>>>>>>> >>>>>>>>>>> Any suggestion ? >>>>>>>>>> I reproduced the assembler failure with your patch. >>>>>>>>>> >>>>>>>>>> The reason is that for arm mode we use divided syntax, where the >>>>>>>>>> condition field goes in a different place. So, while ldrbeq >>>>>>>>>> r0,[r0] is >>>>>>>>>> rejected, ldreqb r0, [r0] works. >>>>>>>>>> Since we always use divided syntax for arm mode, I think you'll need >>>>>>>>>> to put the condition field in the right place depending on arm or >>>>>>>>>> thumb >>>>>>>>>> mode. >>>>>>>>>> Ugh, this is becoming ugly :( >>>>>>>>>> >>>>>>>>> Use %(<suffix%) around the bit that changes for unified/divided >>>>>>>>> syntax. >>>>>>>>> The compiler will then put the condition in the correct place. >>>>>>>>> >>>>>>>>> So: >>>>>>>>> >>>>>>>>> + return \"str%(<sync_sfx>%)\t%1, %0\"; >>>>>>>>> >>>>>>>>> R. >>>>>>>>> >>>>>>>>>> Kyrill >>>>>>>>>> >>>>>>>>>>> Shiva >>>>>>>>>>> >>>>>>>>>>> 2015-06-03 17:29 GMT+08:00 Shiva Chen <shiva0217@gmail.com>: >>>>>>>>>>>> Hi, Ramana >>>>>>>>>>>> >>>>>>>>>>>> I'm not sure what copyright assignment means ? >>>>>>>>>>>> >>>>>>>>>>>> Does it mean the patch have copyright assignment or not ? >>>>>>>>>>>> >>>>>>>>>>>> I update the patch to add "predicable" and "predicable_short_it" >>>>>>>>>>>> attribute as suggestion. >>>>>>>>>>>> >>>>>>>>>>>> However, I don't have svn write access yet. >>>>>>>>>>>> >>>>>>>>>>>> Shiva >>>>>>>>>>>> >>>>>>>>>>>> 2015-06-03 16:36 GMT+08:00 Kyrill Tkachov >>>>>>>>>>>> <kyrylo.tkachov@arm.com>: >>>>>>>>>>>>> On 03/06/15 09:32, Ramana Radhakrishnan wrote: >>>>>>>>>>>>>>> This pattern is not predicable though, i.e. it doesn't have the >>>>>>>>>>>>>>> "predicable" attribute set to "yes". >>>>>>>>>>>>>>> Therefore the compiler should be trying to branch around here >>>>>>>>>>>>>>> rather than try to do a cond_exec. >>>>>>>>>>>>>>> Why does the generated code above look like it's converted to >>>>>>>>>>>>>>> conditional execution? >>>>>>>>>>>>>>> Could you produce a self-contained reduced testcase for this? >>>>>>>>>>>>>> CCFSM state machine in ARM state. >>>>>>>>>>>>>> >>>>>>>>>>>>>> arm.c (final_prescan_insn). >>>>>>>>>>>>> Ah ok. >>>>>>>>>>>>> This patch makes sense then. >>>>>>>>>>>>> As Ramana mentioned, please mark the pattern with "predicable" >>>>>>>>>>>>> and >>>>>>>>>>>>> also set the "predicable_short_it" attribute to "no" so that it >>>>>>>>>>>>> will not be conditionalised in Thumb2 mode or when >>>>>>>>>>>>> -mrestrict-it is >>>>>>>>>>>>> enabled. >>>>>>>>>>>>> >>>>>>>>>>>>> Thanks, >>>>>>>>>>>>> Kyrill >>>>>>>>>>>>> >>>>>>>>>>>>> >>>>>>>>>>>>> >>>>>>>>>>>>>> Ramana >>>>>>>>>>>>>> >>>>>>>>>>>>>>> Thanks, >>>>>>>>>>>>>>> Kyrill >>>>>>>>>>>>>>> >>>>>>>>>>>>>>>> @@ -91,9 +91,9 @@ >>>>>>>>>>>>>>>> { >>>>>>>>>>>>>>>> enum memmodel model = memmodel_from_int (INTVAL >>>>>>>>>>>>>>>> (operands[2])); >>>>>>>>>>>>>>>> if (is_mm_relaxed (model) || is_mm_consume >>>>>>>>>>>>>>>> (model) || >>>>>>>>>>>>>>>> is_mm_acquire (model)) >>>>>>>>>>>>>>>> - return \"str<sync_sfx>\t%1, %0\"; >>>>>>>>>>>>>>>> + return \"str<sync_sfx>%?\t%1, %0\"; >>>>>>>>>>>>>>>> else >>>>>>>>>>>>>>>> - return \"stl<sync_sfx>\t%1, %0\"; >>>>>>>>>>>>>>>> + return \"stl<sync_sfx>%?\t%1, %0\"; >>>>>>>>>>>>>>>> } >>>>>>>>>>>>>>>> ) >>>>>>>>>>>>>>>> [-- Warning: decoded text below may be mangled, UTF-8 assumed --] [-- Attachment #2: shiva-4.9.patch --] [-- Type: text/x-patch; name=shiva-4.9.patch, Size: 2158 bytes --] commit 685d5dfdfab129bff5892053f420ed48fd40737b Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com> Date: Wed Sep 30 14:11:01 2015 +0100 [Backport: GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md index aa8e9ab..747fc7e 100644 --- a/gcc/config/arm/sync.md +++ b/gcc/config/arm/sync.md @@ -77,11 +77,12 @@ if (model == MEMMODEL_RELAXED || model == MEMMODEL_CONSUME || model == MEMMODEL_RELEASE) - return \"ldr<sync_sfx>\\t%0, %1\"; + return \"ldr%(<sync_sfx>%)\\t%0, %1\"; else - return \"lda<sync_sfx>\\t%0, %1\"; + return \"lda%(<sync_sfx>%)\\t%0, %1\"; } -) + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no")]) (define_insn "atomic_store<mode>" [(set (match_operand:QHSI 0 "memory_operand" "=Q") @@ -95,11 +96,12 @@ if (model == MEMMODEL_RELAXED || model == MEMMODEL_CONSUME || model == MEMMODEL_ACQUIRE) - return \"str<sync_sfx>\t%1, %0\"; + return \"str%(<sync_sfx>%)\t%1, %0\"; else - return \"stl<sync_sfx>\t%1, %0\"; + return \"stl%(<sync_sfx>%)\t%1, %0\"; } -) + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no")]) ;; Note that ldrd and vldr are *not* guaranteed to be single-copy atomic, ;; even for a 64-bit aligned address. Instead we use a ldrexd unparied diff --git a/gcc/testsuite/gcc.target/arm/stl-cond.c b/gcc/testsuite/gcc.target/arm/stl-cond.c new file mode 100644 index 0000000..de14bb5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/stl-cond.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arm_ok } */ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-options "-O2 -marm" } */ +/* { dg-add-options arm_arch_v8a } */ + +struct backtrace_state +{ + int threaded; + int lock_alloc; +}; + +void foo (struct backtrace_state *state) +{ + if (state->threaded) + __sync_lock_release (&state->lock_alloc); +} + +/* { dg-final { scan-assembler "stlne" } } */ ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code 2015-09-30 17:10 ` Kyrill Tkachov @ 2015-10-01 9:10 ` Kyrill Tkachov 2015-10-01 20:21 ` Christophe Lyon 0 siblings, 1 reply; 21+ messages in thread From: Kyrill Tkachov @ 2015-10-01 9:10 UTC (permalink / raw) To: Richard Earnshaw, Shiva Chen Cc: Shiva Chen, Ramana Radhakrishnan, GCC Patches, nickc On 30/09/15 17:39, Kyrill Tkachov wrote: > On 09/06/15 09:17, Kyrill Tkachov wrote: >> On 05/06/15 14:14, Kyrill Tkachov wrote: >>> On 05/06/15 14:11, Richard Earnshaw wrote: >>>> On 05/06/15 14:08, Kyrill Tkachov wrote: >>>>> Hi Shiva, >>>>> >>>>> On 05/06/15 10:42, Shiva Chen wrote: >>>>>> Hi, Kyrill >>>>>> >>>>>> I add the testcase as stl-cond.c. >>>>>> >>>>>> Could you help to check the testcase ? >>>>>> >>>>>> If it's OK, Could you help me to apply the patch ? >>>>>> >>>>> This looks ok to me. >>>>> One nit on the testcase: >>>>> >>>>> diff --git a/gcc/testsuite/gcc.target/arm/stl-cond.c >>>>> b/gcc/testsuite/gcc.target/arm/stl-cond.c >>>>> new file mode 100755 >>>>> index 0000000..44c6249 >>>>> --- /dev/null >>>>> +++ b/gcc/testsuite/gcc.target/arm/stl-cond.c >>>>> @@ -0,0 +1,18 @@ >>>>> +/* { dg-do compile } */ >>>>> +/* { dg-require-effective-target arm_arch_v8a_ok } */ >>>>> +/* { dg-options "-O2" } */ >>>>> >>>>> This should also have -marm as the problem exhibited itself in arm state. >>>>> I'll commit this patch with this change in 24 hours on your behalf if no >>>>> one >>>>> objects. >>>>> >>>> Explicit use of -marm will break multi-lib testing. I've forgotten the >>>> correct hook, but there's most-likely something that will give you the >>>> right behaviour, even if it means that thumb-only multi-lib testing >>>> skips this test. >>> So I think what we want is: >>> >>> dg-require-effective-target arm_arm_ok >>> >>> The comment in target-supports.exp is: >>> # Return 1 if this is an ARM target where -marm causes ARM to be >>> # used (not Thumb) >>> >> I've committed the attached patch to trunk on Shiva's behalf with r224269. >> It gates the test on arm_arm_ok and adds -marm, like other similar tests. >> The ChangeLog I used is below: > I'd like to backport this to GCC 5 and 4.9 > The patch applies and tests cleanly on GCC 5. > On 4.9 it needs some minor changes, which I'm attaching here. > I've bootstrapped and tested this patch on 4.9 and the Shiva's > original patch on GCC 5. > > 2015-09-30 Kyrylo Tkachov <kyrylo.tkachov@arm> > > Backport from mainline > 2015-06-09 Shiva Chen <shiva0217@gmail.com> > > * sync.md (atomic_load<mode>): Add conditional code for lda/ldr > (atomic_store<mode>): Likewise. > > 2015-09-30 Kyrylo Tkachov <kyrylo.tkachov@arm> > > Backport from mainline > 2015-06-09 Shiva Chen <shiva0217@gmail.com> > > * gcc.target/arm/stl-cond.c: New test. > > > I'll commit them tomorrow. I've now backported the patch to GCC 5 with r228322 and 4.9 with r228323. Kyrill > Thanks, > Kyrill > > > >> 2015-06-09 Shiva Chen <shiva0217@gmail.com> >> >> * sync.md (atomic_load<mode>): Add conditional code for lda/ldr >> (atomic_store<mode>): Likewise. >> >> 2015-06-09 Shiva Chen <shiva0217@gmail.com> >> >> * gcc.target/arm/stl-cond.c: New test. >> >> >> Thanks, >> Kyrill >> >>> Kyrill >>> >>> >>>> R. >>>> >>>>> Ramana, Richard, we need to backport it to GCC 5 as well, right? >>>>> >>>>> Thanks, >>>>> Kyrill >>>>> >>>>> >>>>>> Thanks, >>>>>> >>>>>> Shiva >>>>>> >>>>>> 2015-06-05 16:34 GMT+08:00 Kyrill Tkachov <kyrylo.tkachov@foss.arm.com>: >>>>>>> Hi Shiva, >>>>>>> >>>>>>> On 05/06/15 09:29, Shiva Chen wrote: >>>>>>>> Hi, Kyrill >>>>>>>> >>>>>>>> I update the patch as Richard's suggestion. >>>>>>>> >>>>>>>> - return \"str<sync_sfx>\t%1, %0\"; >>>>>>>> + return \"str%(<sync_sfx>%)\t%1, %0\"; >>>>>>>> else >>>>>>>> - return \"stl<sync_sfx>\t%1, %0\"; >>>>>>>> + return \"stl<sync_sfx>%?\t%1, %0\"; >>>>>>>> } >>>>>>>> -) >>>>>>>> + [(set_attr "predicable" "yes") >>>>>>>> + (set_attr "predicable_short_it" "no")]) >>>>>>>> + [(set_attr "predicable" "yes") >>>>>>>> + (set_attr "predicable_short_it" "no")]) >>>>>>>> >>>>>>>> >>>>>>>> Let me sum up. >>>>>>>> >>>>>>>> We add predicable attribute to allow gcc do if-conversion in >>>>>>>> ce1/ce2/ce3 not only in final phase by final_prescan_insn finite state >>>>>>>> machine. >>>>>>>> >>>>>>>> We set predicalble_short_it to "no" to restrict conditional code >>>>>>>> generation on armv8 with thumb mode. >>>>>>>> >>>>>>>> However, we could use the flags -mno-restrict-it to force generating >>>>>>>> conditional code on thumb mode. >>>>>>>> >>>>>>>> Therefore, we have to consider the assembly output format for strb >>>>>>>> with condition code on arm/thumb mode. >>>>>>>> >>>>>>>> Because arm/thumb mode use different syntax for strb, >>>>>>>> we output the assembly as str%(<sync_sfx>%) >>>>>>>> which will put the condition code in the right place according to >>>>>>>> TARGET_UNIFIED_ASM. >>>>>>>> >>>>>>>> Is there still missing something ? >>>>>>> That's all correct, and well summarised :) >>>>>>> The patch looks good to me, but please include the testcase >>>>>>> (test.c from earlier) appropriately marked up for the testsuite. >>>>>>> I think to the level of dg-assemble, just so we know everything is >>>>>>> wired up properly. >>>>>>> >>>>>>> Thanks for dealing with this. >>>>>>> Kyrill >>>>>>> >>>>>>> >>>>>>>> Thanks, >>>>>>>> >>>>>>>> Shiva >>>>>>>> >>>>>>>> 2015-06-04 18:00 GMT+08:00 Kyrill Tkachov >>>>>>>> <kyrylo.tkachov@foss.arm.com>: >>>>>>>>> Hi Shiva, >>>>>>>>> >>>>>>>>> On 04/06/15 10:57, Shiva Chen wrote: >>>>>>>>>> Hi, Kyrill >>>>>>>>>> >>>>>>>>>> Thanks for the tips of syntax. >>>>>>>>>> >>>>>>>>>> It seems that correct syntax for >>>>>>>>>> >>>>>>>>>> ldrb with condition code is ldreqb >>>>>>>>>> >>>>>>>>>> ldab with condition code is ldabeq >>>>>>>>>> >>>>>>>>>> >>>>>>>>>> So I modified the pattern as follow >>>>>>>>>> >>>>>>>>>> { >>>>>>>>>> enum memmodel model = (enum memmodel) INTVAL (operands[2]); >>>>>>>>>> if (model == MEMMODEL_RELAXED >>>>>>>>>> || model == MEMMODEL_CONSUME >>>>>>>>>> || model == MEMMODEL_RELEASE) >>>>>>>>>> return \"ldr%?<sync_sfx>\\t%0, %1\"; >>>>>>>>>> else >>>>>>>>>> return \"lda<sync_sfx>%?\\t%0, %1\"; >>>>>>>>>> } >>>>>>>>>> [(set_attr "predicable" "yes") >>>>>>>>>> (set_attr "predicable_short_it" "no")]) >>>>>>>>>> >>>>>>>>>> It seems we don't have to worry about thumb mode, >>>>>>>>> I suggest you use Richard's suggestion from: >>>>>>>>> https://gcc.gnu.org/ml/gcc-patches/2015-06/msg00384.html >>>>>>>>> to write this in a clean way. >>>>>>>>> >>>>>>>>>> Because we already set "predicable" "yes" and predicable_short_it" >>>>>>>>>> "no" >>>>>>>>>> for the pattern. >>>>>>>>> That's not quite true. The user may compile for armv8-a with >>>>>>>>> -mno-restrict-it which will turn off this >>>>>>>>> restriction for Thumb and allow the conditional execution of this. >>>>>>>>> In any case, I think Richard's suggestion above should work. >>>>>>>>> >>>>>>>>> Thanks, >>>>>>>>> Kyrill >>>>>>>>> >>>>>>>>> >>>>>>>>>> The new patch could build gcc and run gcc regression test >>>>>>>>>> successfully. >>>>>>>>>> >>>>>>>>>> Please correct me if I still missing something. >>>>>>>>>> >>>>>>>>>> Thanks, >>>>>>>>>> >>>>>>>>>> Shiva >>>>>>>>>> >>>>>>>>>> -----Original Message----- >>>>>>>>>> From: Richard Earnshaw [mailto:Richard.Earnshaw@foss.arm.com] >>>>>>>>>> Sent: Thursday, June 04, 2015 4:42 PM >>>>>>>>>> To: Kyrill Tkachov; Shiva Chen >>>>>>>>>> Cc: Ramana Radhakrishnan; GCC Patches; nickc@redhat.com; Shiva Chen >>>>>>>>>> Subject: Re: [GCC, ARM] armv8 linux toolchain asan testcase fail >>>>>>>>>> due to >>>>>>>>>> stl missing conditional code >>>>>>>>>> >>>>>>>>>> On 04/06/15 09:17, Kyrill Tkachov wrote: >>>>>>>>>>> Hi Shiva, >>>>>>>>>>> >>>>>>>>>>> On 04/06/15 04:13, Shiva Chen wrote: >>>>>>>>>>>> Hi, Ramana >>>>>>>>>>>> >>>>>>>>>>>> Currently, I work for Marvell and the company have copyright >>>>>>>>>>>> assignment >>>>>>>>>>>> on file. >>>>>>>>>>>> >>>>>>>>>>>> Hi, all >>>>>>>>>>>> >>>>>>>>>>>> After adding the attribute and rebuild gcc, I got the assembler >>>>>>>>>>>> error >>>>>>>>>>>> message >>>>>>>>>>>> >>>>>>>>>>>> load_n.s:39: Error: bad instruction `ldrbeq r0,[r0]' >>>>>>>>>>>> >>>>>>>>>>>> When i look into armv8 ISA document, it seems ldrb Encoding A1 have >>>>>>>>>>>> conditional code field. >>>>>>>>>>>> >>>>>>>>>>>> Does it mean we should also patch assembler or I just miss >>>>>>>>>>>> understanding something ? >>>>>>>>>>>> >>>>>>>>>>>> Following command use to generate load_n.s: >>>>>>>>>>>> >>>>>>>>>>>> /home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnu >>>>>>>>>>>> >>>>>>>>>>>> eabihf-hard/gcc-final/./gcc/cc1 -fpreprocessed load_n.i -quiet >>>>>>>>>>>> -dumpbase load_n.c -march=armv8-a -mfloat-abi=hard -mfpu=fp-armv8 >>>>>>>>>>>> -mtls-dialect=gnu -auxbase-strip .libs/load_1_.o -g3 -O2 -Wall >>>>>>>>>>>> -Werror -version -fPIC -funwind-tables -o load_n.s >>>>>>>>>>>> >>>>>>>>>>>> >>>>>>>>>>>> The test.c is a simple test case to reproduce missing conditional >>>>>>>>>>>> code in mmap.c. >>>>>>>>>>>> >>>>>>>>>>>> Any suggestion ? >>>>>>>>>>> I reproduced the assembler failure with your patch. >>>>>>>>>>> >>>>>>>>>>> The reason is that for arm mode we use divided syntax, where the >>>>>>>>>>> condition field goes in a different place. So, while ldrbeq >>>>>>>>>>> r0,[r0] is >>>>>>>>>>> rejected, ldreqb r0, [r0] works. >>>>>>>>>>> Since we always use divided syntax for arm mode, I think you'll need >>>>>>>>>>> to put the condition field in the right place depending on arm or >>>>>>>>>>> thumb >>>>>>>>>>> mode. >>>>>>>>>>> Ugh, this is becoming ugly :( >>>>>>>>>>> >>>>>>>>>> Use %(<suffix%) around the bit that changes for unified/divided >>>>>>>>>> syntax. >>>>>>>>>> The compiler will then put the condition in the correct place. >>>>>>>>>> >>>>>>>>>> So: >>>>>>>>>> >>>>>>>>>> + return \"str%(<sync_sfx>%)\t%1, %0\"; >>>>>>>>>> >>>>>>>>>> R. >>>>>>>>>> >>>>>>>>>>> Kyrill >>>>>>>>>>> >>>>>>>>>>>> Shiva >>>>>>>>>>>> >>>>>>>>>>>> 2015-06-03 17:29 GMT+08:00 Shiva Chen <shiva0217@gmail.com>: >>>>>>>>>>>>> Hi, Ramana >>>>>>>>>>>>> >>>>>>>>>>>>> I'm not sure what copyright assignment means ? >>>>>>>>>>>>> >>>>>>>>>>>>> Does it mean the patch have copyright assignment or not ? >>>>>>>>>>>>> >>>>>>>>>>>>> I update the patch to add "predicable" and "predicable_short_it" >>>>>>>>>>>>> attribute as suggestion. >>>>>>>>>>>>> >>>>>>>>>>>>> However, I don't have svn write access yet. >>>>>>>>>>>>> >>>>>>>>>>>>> Shiva >>>>>>>>>>>>> >>>>>>>>>>>>> 2015-06-03 16:36 GMT+08:00 Kyrill Tkachov >>>>>>>>>>>>> <kyrylo.tkachov@arm.com>: >>>>>>>>>>>>>> On 03/06/15 09:32, Ramana Radhakrishnan wrote: >>>>>>>>>>>>>>>> This pattern is not predicable though, i.e. it doesn't have the >>>>>>>>>>>>>>>> "predicable" attribute set to "yes". >>>>>>>>>>>>>>>> Therefore the compiler should be trying to branch around here >>>>>>>>>>>>>>>> rather than try to do a cond_exec. >>>>>>>>>>>>>>>> Why does the generated code above look like it's converted to >>>>>>>>>>>>>>>> conditional execution? >>>>>>>>>>>>>>>> Could you produce a self-contained reduced testcase for this? >>>>>>>>>>>>>>> CCFSM state machine in ARM state. >>>>>>>>>>>>>>> >>>>>>>>>>>>>>> arm.c (final_prescan_insn). >>>>>>>>>>>>>> Ah ok. >>>>>>>>>>>>>> This patch makes sense then. >>>>>>>>>>>>>> As Ramana mentioned, please mark the pattern with "predicable" >>>>>>>>>>>>>> and >>>>>>>>>>>>>> also set the "predicable_short_it" attribute to "no" so that it >>>>>>>>>>>>>> will not be conditionalised in Thumb2 mode or when >>>>>>>>>>>>>> -mrestrict-it is >>>>>>>>>>>>>> enabled. >>>>>>>>>>>>>> >>>>>>>>>>>>>> Thanks, >>>>>>>>>>>>>> Kyrill >>>>>>>>>>>>>> >>>>>>>>>>>>>> >>>>>>>>>>>>>> >>>>>>>>>>>>>>> Ramana >>>>>>>>>>>>>>> >>>>>>>>>>>>>>>> Thanks, >>>>>>>>>>>>>>>> Kyrill >>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>>> @@ -91,9 +91,9 @@ >>>>>>>>>>>>>>>>> { >>>>>>>>>>>>>>>>> enum memmodel model = memmodel_from_int (INTVAL >>>>>>>>>>>>>>>>> (operands[2])); >>>>>>>>>>>>>>>>> if (is_mm_relaxed (model) || is_mm_consume >>>>>>>>>>>>>>>>> (model) || >>>>>>>>>>>>>>>>> is_mm_acquire (model)) >>>>>>>>>>>>>>>>> - return \"str<sync_sfx>\t%1, %0\"; >>>>>>>>>>>>>>>>> + return \"str<sync_sfx>%?\t%1, %0\"; >>>>>>>>>>>>>>>>> else >>>>>>>>>>>>>>>>> - return \"stl<sync_sfx>\t%1, %0\"; >>>>>>>>>>>>>>>>> + return \"stl<sync_sfx>%?\t%1, %0\"; >>>>>>>>>>>>>>>>> } >>>>>>>>>>>>>>>>> ) >>>>>>>>>>>>>>>>> ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code 2015-10-01 9:10 ` Kyrill Tkachov @ 2015-10-01 20:21 ` Christophe Lyon 2015-10-02 12:57 ` Kyrill Tkachov 0 siblings, 1 reply; 21+ messages in thread From: Christophe Lyon @ 2015-10-01 20:21 UTC (permalink / raw) To: Kyrill Tkachov Cc: Richard Earnshaw, Shiva Chen, Shiva Chen, Ramana Radhakrishnan, GCC Patches, nickc On 1 October 2015 at 11:10, Kyrill Tkachov <kyrylo.tkachov@arm.com> wrote: > > On 30/09/15 17:39, Kyrill Tkachov wrote: >> >> On 09/06/15 09:17, Kyrill Tkachov wrote: >>> >>> On 05/06/15 14:14, Kyrill Tkachov wrote: >>>> >>>> On 05/06/15 14:11, Richard Earnshaw wrote: >>>>> >>>>> On 05/06/15 14:08, Kyrill Tkachov wrote: >>>>>> >>>>>> Hi Shiva, >>>>>> >>>>>> On 05/06/15 10:42, Shiva Chen wrote: >>>>>>> >>>>>>> Hi, Kyrill >>>>>>> >>>>>>> I add the testcase as stl-cond.c. >>>>>>> >>>>>>> Could you help to check the testcase ? >>>>>>> >>>>>>> If it's OK, Could you help me to apply the patch ? >>>>>>> >>>>>> This looks ok to me. >>>>>> One nit on the testcase: >>>>>> >>>>>> diff --git a/gcc/testsuite/gcc.target/arm/stl-cond.c >>>>>> b/gcc/testsuite/gcc.target/arm/stl-cond.c >>>>>> new file mode 100755 >>>>>> index 0000000..44c6249 >>>>>> --- /dev/null >>>>>> +++ b/gcc/testsuite/gcc.target/arm/stl-cond.c >>>>>> @@ -0,0 +1,18 @@ >>>>>> +/* { dg-do compile } */ >>>>>> +/* { dg-require-effective-target arm_arch_v8a_ok } */ >>>>>> +/* { dg-options "-O2" } */ >>>>>> >>>>>> This should also have -marm as the problem exhibited itself in arm >>>>>> state. >>>>>> I'll commit this patch with this change in 24 hours on your behalf if >>>>>> no >>>>>> one >>>>>> objects. >>>>>> >>>>> Explicit use of -marm will break multi-lib testing. I've forgotten the >>>>> correct hook, but there's most-likely something that will give you the >>>>> right behaviour, even if it means that thumb-only multi-lib testing >>>>> skips this test. >>>> >>>> So I think what we want is: >>>> >>>> dg-require-effective-target arm_arm_ok >>>> >>>> The comment in target-supports.exp is: >>>> # Return 1 if this is an ARM target where -marm causes ARM to be >>>> # used (not Thumb) >>>> >>> I've committed the attached patch to trunk on Shiva's behalf with >>> r224269. >>> It gates the test on arm_arm_ok and adds -marm, like other similar tests. >>> The ChangeLog I used is below: >> >> I'd like to backport this to GCC 5 and 4.9 >> The patch applies and tests cleanly on GCC 5. >> On 4.9 it needs some minor changes, which I'm attaching here. >> I've bootstrapped and tested this patch on 4.9 and the Shiva's >> original patch on GCC 5. >> >> 2015-09-30 Kyrylo Tkachov <kyrylo.tkachov@arm> >> >> Backport from mainline >> 2015-06-09 Shiva Chen <shiva0217@gmail.com> >> >> * sync.md (atomic_load<mode>): Add conditional code for lda/ldr >> (atomic_store<mode>): Likewise. >> >> 2015-09-30 Kyrylo Tkachov <kyrylo.tkachov@arm> >> >> Backport from mainline >> 2015-06-09 Shiva Chen <shiva0217@gmail.com> >> >> * gcc.target/arm/stl-cond.c: New test. >> >> >> I'll commit them tomorrow. > > > I've now backported the patch to GCC 5 with r228322 > and 4.9 with r228323. > Hi Kyrill, The backport in 4.9 causes build failures in libatomic when GCC is configured as: --with-cpu=cortex-a57 --with-fpu=crypto-neon-fp-armv8 --with-mode=arm --target=arm-none-linux-gnueabihf For instance when building store_1_.lo: /tmp/6529147_22.tmpdir/cceUjViw.s:36: Error: bad instruction `stlneb r1,[r0]' when building load_1_.lo: /tmp/6529147_22.tmpdir/cchhKmHw.s:37: Error: bad instruction `ldaneb r0,[r0]' Christophe. > Kyrill > > >> Thanks, >> Kyrill >> >> >> >>> 2015-06-09 Shiva Chen <shiva0217@gmail.com> >>> >>> * sync.md (atomic_load<mode>): Add conditional code for lda/ldr >>> (atomic_store<mode>): Likewise. >>> >>> 2015-06-09 Shiva Chen <shiva0217@gmail.com> >>> >>> * gcc.target/arm/stl-cond.c: New test. >>> >>> >>> Thanks, >>> Kyrill >>> >>>> Kyrill >>>> >>>> >>>>> R. >>>>> >>>>>> Ramana, Richard, we need to backport it to GCC 5 as well, right? >>>>>> >>>>>> Thanks, >>>>>> Kyrill >>>>>> >>>>>> >>>>>>> Thanks, >>>>>>> >>>>>>> Shiva >>>>>>> >>>>>>> 2015-06-05 16:34 GMT+08:00 Kyrill Tkachov >>>>>>> <kyrylo.tkachov@foss.arm.com>: >>>>>>>> >>>>>>>> Hi Shiva, >>>>>>>> >>>>>>>> On 05/06/15 09:29, Shiva Chen wrote: >>>>>>>>> >>>>>>>>> Hi, Kyrill >>>>>>>>> >>>>>>>>> I update the patch as Richard's suggestion. >>>>>>>>> >>>>>>>>> - return \"str<sync_sfx>\t%1, %0\"; >>>>>>>>> + return \"str%(<sync_sfx>%)\t%1, %0\"; >>>>>>>>> else >>>>>>>>> - return \"stl<sync_sfx>\t%1, %0\"; >>>>>>>>> + return \"stl<sync_sfx>%?\t%1, %0\"; >>>>>>>>> } >>>>>>>>> -) >>>>>>>>> + [(set_attr "predicable" "yes") >>>>>>>>> + (set_attr "predicable_short_it" "no")]) >>>>>>>>> + [(set_attr "predicable" "yes") >>>>>>>>> + (set_attr "predicable_short_it" "no")]) >>>>>>>>> >>>>>>>>> >>>>>>>>> Let me sum up. >>>>>>>>> >>>>>>>>> We add predicable attribute to allow gcc do if-conversion in >>>>>>>>> ce1/ce2/ce3 not only in final phase by final_prescan_insn finite >>>>>>>>> state >>>>>>>>> machine. >>>>>>>>> >>>>>>>>> We set predicalble_short_it to "no" to restrict conditional code >>>>>>>>> generation on armv8 with thumb mode. >>>>>>>>> >>>>>>>>> However, we could use the flags -mno-restrict-it to force >>>>>>>>> generating >>>>>>>>> conditional code on thumb mode. >>>>>>>>> >>>>>>>>> Therefore, we have to consider the assembly output format for strb >>>>>>>>> with condition code on arm/thumb mode. >>>>>>>>> >>>>>>>>> Because arm/thumb mode use different syntax for strb, >>>>>>>>> we output the assembly as str%(<sync_sfx>%) >>>>>>>>> which will put the condition code in the right place according to >>>>>>>>> TARGET_UNIFIED_ASM. >>>>>>>>> >>>>>>>>> Is there still missing something ? >>>>>>>> >>>>>>>> That's all correct, and well summarised :) >>>>>>>> The patch looks good to me, but please include the testcase >>>>>>>> (test.c from earlier) appropriately marked up for the testsuite. >>>>>>>> I think to the level of dg-assemble, just so we know everything is >>>>>>>> wired up properly. >>>>>>>> >>>>>>>> Thanks for dealing with this. >>>>>>>> Kyrill >>>>>>>> >>>>>>>> >>>>>>>>> Thanks, >>>>>>>>> >>>>>>>>> Shiva >>>>>>>>> >>>>>>>>> 2015-06-04 18:00 GMT+08:00 Kyrill Tkachov >>>>>>>>> <kyrylo.tkachov@foss.arm.com>: >>>>>>>>>> >>>>>>>>>> Hi Shiva, >>>>>>>>>> >>>>>>>>>> On 04/06/15 10:57, Shiva Chen wrote: >>>>>>>>>>> >>>>>>>>>>> Hi, Kyrill >>>>>>>>>>> >>>>>>>>>>> Thanks for the tips of syntax. >>>>>>>>>>> >>>>>>>>>>> It seems that correct syntax for >>>>>>>>>>> >>>>>>>>>>> ldrb with condition code is ldreqb >>>>>>>>>>> >>>>>>>>>>> ldab with condition code is ldabeq >>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> So I modified the pattern as follow >>>>>>>>>>> >>>>>>>>>>> { >>>>>>>>>>> enum memmodel model = (enum memmodel) INTVAL >>>>>>>>>>> (operands[2]); >>>>>>>>>>> if (model == MEMMODEL_RELAXED >>>>>>>>>>> || model == MEMMODEL_CONSUME >>>>>>>>>>> || model == MEMMODEL_RELEASE) >>>>>>>>>>> return \"ldr%?<sync_sfx>\\t%0, %1\"; >>>>>>>>>>> else >>>>>>>>>>> return \"lda<sync_sfx>%?\\t%0, %1\"; >>>>>>>>>>> } >>>>>>>>>>> [(set_attr "predicable" "yes") >>>>>>>>>>> (set_attr "predicable_short_it" "no")]) >>>>>>>>>>> >>>>>>>>>>> It seems we don't have to worry about thumb mode, >>>>>>>>>> >>>>>>>>>> I suggest you use Richard's suggestion from: >>>>>>>>>> https://gcc.gnu.org/ml/gcc-patches/2015-06/msg00384.html >>>>>>>>>> to write this in a clean way. >>>>>>>>>> >>>>>>>>>>> Because we already set "predicable" "yes" and >>>>>>>>>>> predicable_short_it" >>>>>>>>>>> "no" >>>>>>>>>>> for the pattern. >>>>>>>>>> >>>>>>>>>> That's not quite true. The user may compile for armv8-a with >>>>>>>>>> -mno-restrict-it which will turn off this >>>>>>>>>> restriction for Thumb and allow the conditional execution of this. >>>>>>>>>> In any case, I think Richard's suggestion above should work. >>>>>>>>>> >>>>>>>>>> Thanks, >>>>>>>>>> Kyrill >>>>>>>>>> >>>>>>>>>> >>>>>>>>>>> The new patch could build gcc and run gcc regression test >>>>>>>>>>> successfully. >>>>>>>>>>> >>>>>>>>>>> Please correct me if I still missing something. >>>>>>>>>>> >>>>>>>>>>> Thanks, >>>>>>>>>>> >>>>>>>>>>> Shiva >>>>>>>>>>> >>>>>>>>>>> -----Original Message----- >>>>>>>>>>> From: Richard Earnshaw [mailto:Richard.Earnshaw@foss.arm.com] >>>>>>>>>>> Sent: Thursday, June 04, 2015 4:42 PM >>>>>>>>>>> To: Kyrill Tkachov; Shiva Chen >>>>>>>>>>> Cc: Ramana Radhakrishnan; GCC Patches; nickc@redhat.com; Shiva >>>>>>>>>>> Chen >>>>>>>>>>> Subject: Re: [GCC, ARM] armv8 linux toolchain asan testcase fail >>>>>>>>>>> due to >>>>>>>>>>> stl missing conditional code >>>>>>>>>>> >>>>>>>>>>> On 04/06/15 09:17, Kyrill Tkachov wrote: >>>>>>>>>>>> >>>>>>>>>>>> Hi Shiva, >>>>>>>>>>>> >>>>>>>>>>>> On 04/06/15 04:13, Shiva Chen wrote: >>>>>>>>>>>>> >>>>>>>>>>>>> Hi, Ramana >>>>>>>>>>>>> >>>>>>>>>>>>> Currently, I work for Marvell and the company have copyright >>>>>>>>>>>>> assignment >>>>>>>>>>>>> on file. >>>>>>>>>>>>> >>>>>>>>>>>>> Hi, all >>>>>>>>>>>>> >>>>>>>>>>>>> After adding the attribute and rebuild gcc, I got the assembler >>>>>>>>>>>>> error >>>>>>>>>>>>> message >>>>>>>>>>>>> >>>>>>>>>>>>> load_n.s:39: Error: bad instruction `ldrbeq r0,[r0]' >>>>>>>>>>>>> >>>>>>>>>>>>> When i look into armv8 ISA document, it seems ldrb Encoding A1 >>>>>>>>>>>>> have >>>>>>>>>>>>> conditional code field. >>>>>>>>>>>>> >>>>>>>>>>>>> Does it mean we should also patch assembler or I just miss >>>>>>>>>>>>> understanding something ? >>>>>>>>>>>>> >>>>>>>>>>>>> Following command use to generate load_n.s: >>>>>>>>>>>>> >>>>>>>>>>>>> >>>>>>>>>>>>> /home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnu >>>>>>>>>>>>> >>>>>>>>>>>>> eabihf-hard/gcc-final/./gcc/cc1 -fpreprocessed load_n.i -quiet >>>>>>>>>>>>> -dumpbase load_n.c -march=armv8-a -mfloat-abi=hard >>>>>>>>>>>>> -mfpu=fp-armv8 >>>>>>>>>>>>> -mtls-dialect=gnu -auxbase-strip .libs/load_1_.o -g3 -O2 -Wall >>>>>>>>>>>>> -Werror -version -fPIC -funwind-tables -o load_n.s >>>>>>>>>>>>> >>>>>>>>>>>>> >>>>>>>>>>>>> The test.c is a simple test case to reproduce missing >>>>>>>>>>>>> conditional >>>>>>>>>>>>> code in mmap.c. >>>>>>>>>>>>> >>>>>>>>>>>>> Any suggestion ? >>>>>>>>>>>> >>>>>>>>>>>> I reproduced the assembler failure with your patch. >>>>>>>>>>>> >>>>>>>>>>>> The reason is that for arm mode we use divided syntax, where the >>>>>>>>>>>> condition field goes in a different place. So, while ldrbeq >>>>>>>>>>>> r0,[r0] is >>>>>>>>>>>> rejected, ldreqb r0, [r0] works. >>>>>>>>>>>> Since we always use divided syntax for arm mode, I think you'll >>>>>>>>>>>> need >>>>>>>>>>>> to put the condition field in the right place depending on arm >>>>>>>>>>>> or >>>>>>>>>>>> thumb >>>>>>>>>>>> mode. >>>>>>>>>>>> Ugh, this is becoming ugly :( >>>>>>>>>>>> >>>>>>>>>>> Use %(<suffix%) around the bit that changes for unified/divided >>>>>>>>>>> syntax. >>>>>>>>>>> The compiler will then put the condition in the correct >>>>>>>>>>> place. >>>>>>>>>>> >>>>>>>>>>> So: >>>>>>>>>>> >>>>>>>>>>> + return \"str%(<sync_sfx>%)\t%1, %0\"; >>>>>>>>>>> >>>>>>>>>>> R. >>>>>>>>>>> >>>>>>>>>>>> Kyrill >>>>>>>>>>>> >>>>>>>>>>>>> Shiva >>>>>>>>>>>>> >>>>>>>>>>>>> 2015-06-03 17:29 GMT+08:00 Shiva Chen <shiva0217@gmail.com>: >>>>>>>>>>>>>> >>>>>>>>>>>>>> Hi, Ramana >>>>>>>>>>>>>> >>>>>>>>>>>>>> I'm not sure what copyright assignment means ? >>>>>>>>>>>>>> >>>>>>>>>>>>>> Does it mean the patch have copyright assignment or not ? >>>>>>>>>>>>>> >>>>>>>>>>>>>> I update the patch to add "predicable" and >>>>>>>>>>>>>> "predicable_short_it" >>>>>>>>>>>>>> attribute as suggestion. >>>>>>>>>>>>>> >>>>>>>>>>>>>> However, I don't have svn write access yet. >>>>>>>>>>>>>> >>>>>>>>>>>>>> Shiva >>>>>>>>>>>>>> >>>>>>>>>>>>>> 2015-06-03 16:36 GMT+08:00 Kyrill Tkachov >>>>>>>>>>>>>> <kyrylo.tkachov@arm.com>: >>>>>>>>>>>>>>> >>>>>>>>>>>>>>> On 03/06/15 09:32, Ramana Radhakrishnan wrote: >>>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>>> This pattern is not predicable though, i.e. it doesn't have >>>>>>>>>>>>>>>>> the >>>>>>>>>>>>>>>>> "predicable" attribute set to "yes". >>>>>>>>>>>>>>>>> Therefore the compiler should be trying to branch around >>>>>>>>>>>>>>>>> here >>>>>>>>>>>>>>>>> rather than try to do a cond_exec. >>>>>>>>>>>>>>>>> Why does the generated code above look like it's converted >>>>>>>>>>>>>>>>> to >>>>>>>>>>>>>>>>> conditional execution? >>>>>>>>>>>>>>>>> Could you produce a self-contained reduced testcase for >>>>>>>>>>>>>>>>> this? >>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>> CCFSM state machine in ARM state. >>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>> arm.c (final_prescan_insn). >>>>>>>>>>>>>>> >>>>>>>>>>>>>>> Ah ok. >>>>>>>>>>>>>>> This patch makes sense then. >>>>>>>>>>>>>>> As Ramana mentioned, please mark the pattern with >>>>>>>>>>>>>>> "predicable" >>>>>>>>>>>>>>> and >>>>>>>>>>>>>>> also set the "predicable_short_it" attribute to "no" so that >>>>>>>>>>>>>>> it >>>>>>>>>>>>>>> will not be conditionalised in Thumb2 mode or when >>>>>>>>>>>>>>> -mrestrict-it is >>>>>>>>>>>>>>> enabled. >>>>>>>>>>>>>>> >>>>>>>>>>>>>>> Thanks, >>>>>>>>>>>>>>> Kyrill >>>>>>>>>>>>>>> >>>>>>>>>>>>>>> >>>>>>>>>>>>>>> >>>>>>>>>>>>>>>> Ramana >>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>>> Thanks, >>>>>>>>>>>>>>>>> Kyrill >>>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>>>> @@ -91,9 +91,9 @@ >>>>>>>>>>>>>>>>>> { >>>>>>>>>>>>>>>>>> enum memmodel model = memmodel_from_int >>>>>>>>>>>>>>>>>> (INTVAL >>>>>>>>>>>>>>>>>> (operands[2])); >>>>>>>>>>>>>>>>>> if (is_mm_relaxed (model) || is_mm_consume >>>>>>>>>>>>>>>>>> (model) || >>>>>>>>>>>>>>>>>> is_mm_acquire (model)) >>>>>>>>>>>>>>>>>> - return \"str<sync_sfx>\t%1, %0\"; >>>>>>>>>>>>>>>>>> + return \"str<sync_sfx>%?\t%1, %0\"; >>>>>>>>>>>>>>>>>> else >>>>>>>>>>>>>>>>>> - return \"stl<sync_sfx>\t%1, %0\"; >>>>>>>>>>>>>>>>>> + return \"stl<sync_sfx>%?\t%1, %0\"; >>>>>>>>>>>>>>>>>> } >>>>>>>>>>>>>>>>>> ) >>>>>>>>>>>>>>>>>> > ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code 2015-10-01 20:21 ` Christophe Lyon @ 2015-10-02 12:57 ` Kyrill Tkachov 0 siblings, 0 replies; 21+ messages in thread From: Kyrill Tkachov @ 2015-10-02 12:57 UTC (permalink / raw) To: Christophe Lyon Cc: Richard Earnshaw, Shiva Chen, Shiva Chen, Ramana Radhakrishnan, GCC Patches, nickc [-- Attachment #1: Type: text/plain, Size: 15020 bytes --] On 01/10/15 21:21, Christophe Lyon wrote: > On 1 October 2015 at 11:10, Kyrill Tkachov <kyrylo.tkachov@arm.com> wrote: >> On 30/09/15 17:39, Kyrill Tkachov wrote: >>> On 09/06/15 09:17, Kyrill Tkachov wrote: >>>> On 05/06/15 14:14, Kyrill Tkachov wrote: >>>>> On 05/06/15 14:11, Richard Earnshaw wrote: >>>>>> On 05/06/15 14:08, Kyrill Tkachov wrote: >>>>>>> Hi Shiva, >>>>>>> >>>>>>> On 05/06/15 10:42, Shiva Chen wrote: >>>>>>>> Hi, Kyrill >>>>>>>> >>>>>>>> I add the testcase as stl-cond.c. >>>>>>>> >>>>>>>> Could you help to check the testcase ? >>>>>>>> >>>>>>>> If it's OK, Could you help me to apply the patch ? >>>>>>>> >>>>>>> This looks ok to me. >>>>>>> One nit on the testcase: >>>>>>> >>>>>>> diff --git a/gcc/testsuite/gcc.target/arm/stl-cond.c >>>>>>> b/gcc/testsuite/gcc.target/arm/stl-cond.c >>>>>>> new file mode 100755 >>>>>>> index 0000000..44c6249 >>>>>>> --- /dev/null >>>>>>> +++ b/gcc/testsuite/gcc.target/arm/stl-cond.c >>>>>>> @@ -0,0 +1,18 @@ >>>>>>> +/* { dg-do compile } */ >>>>>>> +/* { dg-require-effective-target arm_arch_v8a_ok } */ >>>>>>> +/* { dg-options "-O2" } */ >>>>>>> >>>>>>> This should also have -marm as the problem exhibited itself in arm >>>>>>> state. >>>>>>> I'll commit this patch with this change in 24 hours on your behalf if >>>>>>> no >>>>>>> one >>>>>>> objects. >>>>>>> >>>>>> Explicit use of -marm will break multi-lib testing. I've forgotten the >>>>>> correct hook, but there's most-likely something that will give you the >>>>>> right behaviour, even if it means that thumb-only multi-lib testing >>>>>> skips this test. >>>>> So I think what we want is: >>>>> >>>>> dg-require-effective-target arm_arm_ok >>>>> >>>>> The comment in target-supports.exp is: >>>>> # Return 1 if this is an ARM target where -marm causes ARM to be >>>>> # used (not Thumb) >>>>> >>>> I've committed the attached patch to trunk on Shiva's behalf with >>>> r224269. >>>> It gates the test on arm_arm_ok and adds -marm, like other similar tests. >>>> The ChangeLog I used is below: >>> I'd like to backport this to GCC 5 and 4.9 >>> The patch applies and tests cleanly on GCC 5. >>> On 4.9 it needs some minor changes, which I'm attaching here. >>> I've bootstrapped and tested this patch on 4.9 and the Shiva's >>> original patch on GCC 5. >>> >>> 2015-09-30 Kyrylo Tkachov <kyrylo.tkachov@arm> >>> >>> Backport from mainline >>> 2015-06-09 Shiva Chen <shiva0217@gmail.com> >>> >>> * sync.md (atomic_load<mode>): Add conditional code for lda/ldr >>> (atomic_store<mode>): Likewise. >>> >>> 2015-09-30 Kyrylo Tkachov <kyrylo.tkachov@arm> >>> >>> Backport from mainline >>> 2015-06-09 Shiva Chen <shiva0217@gmail.com> >>> >>> * gcc.target/arm/stl-cond.c: New test. >>> >>> >>> I'll commit them tomorrow. >> >> I've now backported the patch to GCC 5 with r228322 >> and 4.9 with r228323. >> > Hi Kyrill, Hi Christophe, > > The backport in 4.9 causes build failures in libatomic when GCC is > configured as: > --with-cpu=cortex-a57 > --with-fpu=crypto-neon-fp-armv8 > --with-mode=arm > --target=arm-none-linux-gnueabihf > > For instance when building store_1_.lo: > /tmp/6529147_22.tmpdir/cceUjViw.s:36: Error: bad instruction `stlneb r1,[r0]' > > when building load_1_.lo: > /tmp/6529147_22.tmpdir/cchhKmHw.s:37: Error: bad instruction `ldaneb r0,[r0]' Huh, sorry for that. I did bootstrap 4.9 configured --with-arch=armv8-a, don't know why the failure didn't flare up. I did reproduce the bad code with a custom testcase. This patch fixes it and brings the code in line with GCC 5 and trunk. Bootstrapped and tested on the 4.9 branch. Committed under the fixes-the-build rule to the 4.9 branch with r228389. Thanks, Kyrill 2015-10-02 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * sync.md (atomic_load<mode>): Fix output modifier for lda. (atomic_store<mode>): Likewise for stl. > Christophe. > >> Kyrill >> >> >>> Thanks, >>> Kyrill >>> >>> >>> >>>> 2015-06-09 Shiva Chen <shiva0217@gmail.com> >>>> >>>> * sync.md (atomic_load<mode>): Add conditional code for lda/ldr >>>> (atomic_store<mode>): Likewise. >>>> >>>> 2015-06-09 Shiva Chen <shiva0217@gmail.com> >>>> >>>> * gcc.target/arm/stl-cond.c: New test. >>>> >>>> >>>> Thanks, >>>> Kyrill >>>> >>>>> Kyrill >>>>> >>>>> >>>>>> R. >>>>>> >>>>>>> Ramana, Richard, we need to backport it to GCC 5 as well, right? >>>>>>> >>>>>>> Thanks, >>>>>>> Kyrill >>>>>>> >>>>>>> >>>>>>>> Thanks, >>>>>>>> >>>>>>>> Shiva >>>>>>>> >>>>>>>> 2015-06-05 16:34 GMT+08:00 Kyrill Tkachov >>>>>>>> <kyrylo.tkachov@foss.arm.com>: >>>>>>>>> Hi Shiva, >>>>>>>>> >>>>>>>>> On 05/06/15 09:29, Shiva Chen wrote: >>>>>>>>>> Hi, Kyrill >>>>>>>>>> >>>>>>>>>> I update the patch as Richard's suggestion. >>>>>>>>>> >>>>>>>>>> - return \"str<sync_sfx>\t%1, %0\"; >>>>>>>>>> + return \"str%(<sync_sfx>%)\t%1, %0\"; >>>>>>>>>> else >>>>>>>>>> - return \"stl<sync_sfx>\t%1, %0\"; >>>>>>>>>> + return \"stl<sync_sfx>%?\t%1, %0\"; >>>>>>>>>> } >>>>>>>>>> -) >>>>>>>>>> + [(set_attr "predicable" "yes") >>>>>>>>>> + (set_attr "predicable_short_it" "no")]) >>>>>>>>>> + [(set_attr "predicable" "yes") >>>>>>>>>> + (set_attr "predicable_short_it" "no")]) >>>>>>>>>> >>>>>>>>>> >>>>>>>>>> Let me sum up. >>>>>>>>>> >>>>>>>>>> We add predicable attribute to allow gcc do if-conversion in >>>>>>>>>> ce1/ce2/ce3 not only in final phase by final_prescan_insn finite >>>>>>>>>> state >>>>>>>>>> machine. >>>>>>>>>> >>>>>>>>>> We set predicalble_short_it to "no" to restrict conditional code >>>>>>>>>> generation on armv8 with thumb mode. >>>>>>>>>> >>>>>>>>>> However, we could use the flags -mno-restrict-it to force >>>>>>>>>> generating >>>>>>>>>> conditional code on thumb mode. >>>>>>>>>> >>>>>>>>>> Therefore, we have to consider the assembly output format for strb >>>>>>>>>> with condition code on arm/thumb mode. >>>>>>>>>> >>>>>>>>>> Because arm/thumb mode use different syntax for strb, >>>>>>>>>> we output the assembly as str%(<sync_sfx>%) >>>>>>>>>> which will put the condition code in the right place according to >>>>>>>>>> TARGET_UNIFIED_ASM. >>>>>>>>>> >>>>>>>>>> Is there still missing something ? >>>>>>>>> That's all correct, and well summarised :) >>>>>>>>> The patch looks good to me, but please include the testcase >>>>>>>>> (test.c from earlier) appropriately marked up for the testsuite. >>>>>>>>> I think to the level of dg-assemble, just so we know everything is >>>>>>>>> wired up properly. >>>>>>>>> >>>>>>>>> Thanks for dealing with this. >>>>>>>>> Kyrill >>>>>>>>> >>>>>>>>> >>>>>>>>>> Thanks, >>>>>>>>>> >>>>>>>>>> Shiva >>>>>>>>>> >>>>>>>>>> 2015-06-04 18:00 GMT+08:00 Kyrill Tkachov >>>>>>>>>> <kyrylo.tkachov@foss.arm.com>: >>>>>>>>>>> Hi Shiva, >>>>>>>>>>> >>>>>>>>>>> On 04/06/15 10:57, Shiva Chen wrote: >>>>>>>>>>>> Hi, Kyrill >>>>>>>>>>>> >>>>>>>>>>>> Thanks for the tips of syntax. >>>>>>>>>>>> >>>>>>>>>>>> It seems that correct syntax for >>>>>>>>>>>> >>>>>>>>>>>> ldrb with condition code is ldreqb >>>>>>>>>>>> >>>>>>>>>>>> ldab with condition code is ldabeq >>>>>>>>>>>> >>>>>>>>>>>> >>>>>>>>>>>> So I modified the pattern as follow >>>>>>>>>>>> >>>>>>>>>>>> { >>>>>>>>>>>> enum memmodel model = (enum memmodel) INTVAL >>>>>>>>>>>> (operands[2]); >>>>>>>>>>>> if (model == MEMMODEL_RELAXED >>>>>>>>>>>> || model == MEMMODEL_CONSUME >>>>>>>>>>>> || model == MEMMODEL_RELEASE) >>>>>>>>>>>> return \"ldr%?<sync_sfx>\\t%0, %1\"; >>>>>>>>>>>> else >>>>>>>>>>>> return \"lda<sync_sfx>%?\\t%0, %1\"; >>>>>>>>>>>> } >>>>>>>>>>>> [(set_attr "predicable" "yes") >>>>>>>>>>>> (set_attr "predicable_short_it" "no")]) >>>>>>>>>>>> >>>>>>>>>>>> It seems we don't have to worry about thumb mode, >>>>>>>>>>> I suggest you use Richard's suggestion from: >>>>>>>>>>> https://gcc.gnu.org/ml/gcc-patches/2015-06/msg00384.html >>>>>>>>>>> to write this in a clean way. >>>>>>>>>>> >>>>>>>>>>>> Because we already set "predicable" "yes" and >>>>>>>>>>>> predicable_short_it" >>>>>>>>>>>> "no" >>>>>>>>>>>> for the pattern. >>>>>>>>>>> That's not quite true. The user may compile for armv8-a with >>>>>>>>>>> -mno-restrict-it which will turn off this >>>>>>>>>>> restriction for Thumb and allow the conditional execution of this. >>>>>>>>>>> In any case, I think Richard's suggestion above should work. >>>>>>>>>>> >>>>>>>>>>> Thanks, >>>>>>>>>>> Kyrill >>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>>> The new patch could build gcc and run gcc regression test >>>>>>>>>>>> successfully. >>>>>>>>>>>> >>>>>>>>>>>> Please correct me if I still missing something. >>>>>>>>>>>> >>>>>>>>>>>> Thanks, >>>>>>>>>>>> >>>>>>>>>>>> Shiva >>>>>>>>>>>> >>>>>>>>>>>> -----Original Message----- >>>>>>>>>>>> From: Richard Earnshaw [mailto:Richard.Earnshaw@foss.arm.com] >>>>>>>>>>>> Sent: Thursday, June 04, 2015 4:42 PM >>>>>>>>>>>> To: Kyrill Tkachov; Shiva Chen >>>>>>>>>>>> Cc: Ramana Radhakrishnan; GCC Patches; nickc@redhat.com; Shiva >>>>>>>>>>>> Chen >>>>>>>>>>>> Subject: Re: [GCC, ARM] armv8 linux toolchain asan testcase fail >>>>>>>>>>>> due to >>>>>>>>>>>> stl missing conditional code >>>>>>>>>>>> >>>>>>>>>>>> On 04/06/15 09:17, Kyrill Tkachov wrote: >>>>>>>>>>>>> Hi Shiva, >>>>>>>>>>>>> >>>>>>>>>>>>> On 04/06/15 04:13, Shiva Chen wrote: >>>>>>>>>>>>>> Hi, Ramana >>>>>>>>>>>>>> >>>>>>>>>>>>>> Currently, I work for Marvell and the company have copyright >>>>>>>>>>>>>> assignment >>>>>>>>>>>>>> on file. >>>>>>>>>>>>>> >>>>>>>>>>>>>> Hi, all >>>>>>>>>>>>>> >>>>>>>>>>>>>> After adding the attribute and rebuild gcc, I got the assembler >>>>>>>>>>>>>> error >>>>>>>>>>>>>> message >>>>>>>>>>>>>> >>>>>>>>>>>>>> load_n.s:39: Error: bad instruction `ldrbeq r0,[r0]' >>>>>>>>>>>>>> >>>>>>>>>>>>>> When i look into armv8 ISA document, it seems ldrb Encoding A1 >>>>>>>>>>>>>> have >>>>>>>>>>>>>> conditional code field. >>>>>>>>>>>>>> >>>>>>>>>>>>>> Does it mean we should also patch assembler or I just miss >>>>>>>>>>>>>> understanding something ? >>>>>>>>>>>>>> >>>>>>>>>>>>>> Following command use to generate load_n.s: >>>>>>>>>>>>>> >>>>>>>>>>>>>> >>>>>>>>>>>>>> /home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnu >>>>>>>>>>>>>> >>>>>>>>>>>>>> eabihf-hard/gcc-final/./gcc/cc1 -fpreprocessed load_n.i -quiet >>>>>>>>>>>>>> -dumpbase load_n.c -march=armv8-a -mfloat-abi=hard >>>>>>>>>>>>>> -mfpu=fp-armv8 >>>>>>>>>>>>>> -mtls-dialect=gnu -auxbase-strip .libs/load_1_.o -g3 -O2 -Wall >>>>>>>>>>>>>> -Werror -version -fPIC -funwind-tables -o load_n.s >>>>>>>>>>>>>> >>>>>>>>>>>>>> >>>>>>>>>>>>>> The test.c is a simple test case to reproduce missing >>>>>>>>>>>>>> conditional >>>>>>>>>>>>>> code in mmap.c. >>>>>>>>>>>>>> >>>>>>>>>>>>>> Any suggestion ? >>>>>>>>>>>>> I reproduced the assembler failure with your patch. >>>>>>>>>>>>> >>>>>>>>>>>>> The reason is that for arm mode we use divided syntax, where the >>>>>>>>>>>>> condition field goes in a different place. So, while ldrbeq >>>>>>>>>>>>> r0,[r0] is >>>>>>>>>>>>> rejected, ldreqb r0, [r0] works. >>>>>>>>>>>>> Since we always use divided syntax for arm mode, I think you'll >>>>>>>>>>>>> need >>>>>>>>>>>>> to put the condition field in the right place depending on arm >>>>>>>>>>>>> or >>>>>>>>>>>>> thumb >>>>>>>>>>>>> mode. >>>>>>>>>>>>> Ugh, this is becoming ugly :( >>>>>>>>>>>>> >>>>>>>>>>>> Use %(<suffix%) around the bit that changes for unified/divided >>>>>>>>>>>> syntax. >>>>>>>>>>>> The compiler will then put the condition in the correct >>>>>>>>>>>> place. >>>>>>>>>>>> >>>>>>>>>>>> So: >>>>>>>>>>>> >>>>>>>>>>>> + return \"str%(<sync_sfx>%)\t%1, %0\"; >>>>>>>>>>>> >>>>>>>>>>>> R. >>>>>>>>>>>> >>>>>>>>>>>>> Kyrill >>>>>>>>>>>>> >>>>>>>>>>>>>> Shiva >>>>>>>>>>>>>> >>>>>>>>>>>>>> 2015-06-03 17:29 GMT+08:00 Shiva Chen <shiva0217@gmail.com>: >>>>>>>>>>>>>>> Hi, Ramana >>>>>>>>>>>>>>> >>>>>>>>>>>>>>> I'm not sure what copyright assignment means ? >>>>>>>>>>>>>>> >>>>>>>>>>>>>>> Does it mean the patch have copyright assignment or not ? >>>>>>>>>>>>>>> >>>>>>>>>>>>>>> I update the patch to add "predicable" and >>>>>>>>>>>>>>> "predicable_short_it" >>>>>>>>>>>>>>> attribute as suggestion. >>>>>>>>>>>>>>> >>>>>>>>>>>>>>> However, I don't have svn write access yet. >>>>>>>>>>>>>>> >>>>>>>>>>>>>>> Shiva >>>>>>>>>>>>>>> >>>>>>>>>>>>>>> 2015-06-03 16:36 GMT+08:00 Kyrill Tkachov >>>>>>>>>>>>>>> <kyrylo.tkachov@arm.com>: >>>>>>>>>>>>>>>> On 03/06/15 09:32, Ramana Radhakrishnan wrote: >>>>>>>>>>>>>>>>>> This pattern is not predicable though, i.e. it doesn't have >>>>>>>>>>>>>>>>>> the >>>>>>>>>>>>>>>>>> "predicable" attribute set to "yes". >>>>>>>>>>>>>>>>>> Therefore the compiler should be trying to branch around >>>>>>>>>>>>>>>>>> here >>>>>>>>>>>>>>>>>> rather than try to do a cond_exec. >>>>>>>>>>>>>>>>>> Why does the generated code above look like it's converted >>>>>>>>>>>>>>>>>> to >>>>>>>>>>>>>>>>>> conditional execution? >>>>>>>>>>>>>>>>>> Could you produce a self-contained reduced testcase for >>>>>>>>>>>>>>>>>> this? >>>>>>>>>>>>>>>>> CCFSM state machine in ARM state. >>>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>>> arm.c (final_prescan_insn). >>>>>>>>>>>>>>>> Ah ok. >>>>>>>>>>>>>>>> This patch makes sense then. >>>>>>>>>>>>>>>> As Ramana mentioned, please mark the pattern with >>>>>>>>>>>>>>>> "predicable" >>>>>>>>>>>>>>>> and >>>>>>>>>>>>>>>> also set the "predicable_short_it" attribute to "no" so that >>>>>>>>>>>>>>>> it >>>>>>>>>>>>>>>> will not be conditionalised in Thumb2 mode or when >>>>>>>>>>>>>>>> -mrestrict-it is >>>>>>>>>>>>>>>> enabled. >>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>> Thanks, >>>>>>>>>>>>>>>> Kyrill >>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>>> Ramana >>>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>>>> Thanks, >>>>>>>>>>>>>>>>>> Kyrill >>>>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>>>>> @@ -91,9 +91,9 @@ >>>>>>>>>>>>>>>>>>> { >>>>>>>>>>>>>>>>>>> enum memmodel model = memmodel_from_int >>>>>>>>>>>>>>>>>>> (INTVAL >>>>>>>>>>>>>>>>>>> (operands[2])); >>>>>>>>>>>>>>>>>>> if (is_mm_relaxed (model) || is_mm_consume >>>>>>>>>>>>>>>>>>> (model) || >>>>>>>>>>>>>>>>>>> is_mm_acquire (model)) >>>>>>>>>>>>>>>>>>> - return \"str<sync_sfx>\t%1, %0\"; >>>>>>>>>>>>>>>>>>> + return \"str<sync_sfx>%?\t%1, %0\"; >>>>>>>>>>>>>>>>>>> else >>>>>>>>>>>>>>>>>>> - return \"stl<sync_sfx>\t%1, %0\"; >>>>>>>>>>>>>>>>>>> + return \"stl<sync_sfx>%?\t%1, %0\"; >>>>>>>>>>>>>>>>>>> } >>>>>>>>>>>>>>>>>>> ) >>>>>>>>>>>>>>>>>>> [-- Warning: decoded text below may be mangled, UTF-8 assumed --] [-- Attachment #2: arm-4.9-stl-suffix.patch --] [-- Type: text/x-patch; name=arm-4.9-stl-suffix.patch, Size: 740 bytes --] diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md index 747fc7e..25ed926 100644 --- a/gcc/config/arm/sync.md +++ b/gcc/config/arm/sync.md @@ -79,7 +79,7 @@ || model == MEMMODEL_RELEASE) return \"ldr%(<sync_sfx>%)\\t%0, %1\"; else - return \"lda%(<sync_sfx>%)\\t%0, %1\"; + return \"lda<sync_sfx>%?\\t%0, %1\"; } [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no")]) @@ -98,7 +98,7 @@ || model == MEMMODEL_ACQUIRE) return \"str%(<sync_sfx>%)\t%1, %0\"; else - return \"stl%(<sync_sfx>%)\t%1, %0\"; + return \"stl<sync_sfx>%?\t%1, %0\"; } [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no")]) ^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2015-10-02 12:57 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-06-03 5:27 [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code Shiva Chen
2015-06-03 8:31 ` Ramana Radhakrishnan
2015-06-03 8:36 ` Kyrill Tkachov
[not found] ` <556EBBAC.2020504@arm.com>
2015-06-03 8:53 ` Kyrill Tkachov
2015-06-03 9:33 ` Shiva Chen
2015-06-04 4:51 ` Shiva Chen
2015-06-04 8:24 ` Kyrill Tkachov
2015-06-04 8:42 ` Richard Earnshaw
2015-06-04 10:01 ` Shiva Chen
2015-06-04 10:04 ` Kyrill Tkachov
2015-06-05 8:34 ` Shiva Chen
2015-06-05 8:35 ` Kyrill Tkachov
2015-06-05 10:59 ` Shiva Chen
2015-06-05 13:11 ` Kyrill Tkachov
2015-06-05 13:14 ` Richard Earnshaw
2015-06-05 14:02 ` Kyrill Tkachov
2015-06-09 8:44 ` Kyrill Tkachov
2015-09-30 17:10 ` Kyrill Tkachov
2015-10-01 9:10 ` Kyrill Tkachov
2015-10-01 20:21 ` Christophe Lyon
2015-10-02 12:57 ` Kyrill Tkachov
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