From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 35964 invoked by alias); 3 Jun 2015 09:30:02 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 35905 invoked by uid 89); 3 Jun 2015 09:30:01 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL,BAYES_00,FREEMAIL_ENVFROM_END_DIGIT,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-wi0-f172.google.com Received: from mail-wi0-f172.google.com (HELO mail-wi0-f172.google.com) (209.85.212.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Wed, 03 Jun 2015 09:30:00 +0000 Received: by wibdt2 with SMTP id dt2so5231381wib.1 for ; Wed, 03 Jun 2015 02:29:57 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.180.105.129 with SMTP id gm1mr38268152wib.51.1433323796964; Wed, 03 Jun 2015 02:29:56 -0700 (PDT) Received: by 10.27.128.196 with HTTP; Wed, 3 Jun 2015 02:29:56 -0700 (PDT) In-Reply-To: <556EBC77.3060601@arm.com> References: <556EBB3F.7090603@arm.com> <556EBBAC.2020504@arm.com> <556EBC77.3060601@arm.com> Date: Wed, 03 Jun 2015 09:33:00 -0000 Message-ID: Subject: Re: [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code From: Shiva Chen To: Kyrill Tkachov Cc: Ramana Radhakrishnan , GCC Patches , "nickc@redhat.com" , Richard Earnshaw Content-Type: multipart/mixed; boundary=f46d04182626c4a6e9051799b3e3 X-SW-Source: 2015-06/txt/msg00291.txt.bz2 --f46d04182626c4a6e9051799b3e3 Content-Type: text/plain; charset=UTF-8 Content-length: 1606 Hi, Ramana I'm not sure what copyright assignment means ? Does it mean the patch have copyright assignment or not ? I update the patch to add "predicable" and "predicable_short_it" attribute as suggestion. However, I don't have svn write access yet. Shiva 2015-06-03 16:36 GMT+08:00 Kyrill Tkachov : > > On 03/06/15 09:32, Ramana Radhakrishnan wrote: >>> >>> This pattern is not predicable though, i.e. it doesn't have the >>> "predicable" attribute set to "yes". >>> Therefore the compiler should be trying to branch around here rather than >>> try to do a cond_exec. >>> Why does the generated code above look like it's converted to conditional >>> execution? >>> Could you produce a self-contained reduced testcase for this? >> >> CCFSM state machine in ARM state. >> >> arm.c (final_prescan_insn). > > > Ah ok. > This patch makes sense then. > As Ramana mentioned, please mark the pattern with "predicable" and also set > the "predicable_short_it" attribute to "no" so that it will not be > conditionalised in Thumb2 mode or when -mrestrict-it is enabled. > > Thanks, > Kyrill > > > >> >> Ramana >> >>> Thanks, >>> Kyrill >>> >>>> @@ -91,9 +91,9 @@ >>>> { >>>> enum memmodel model = memmodel_from_int (INTVAL (operands[2])); >>>> if (is_mm_relaxed (model) || is_mm_consume (model) || >>>> is_mm_acquire (model)) >>>> - return \"str\t%1, %0\"; >>>> + return \"str%?\t%1, %0\"; >>>> else >>>> - return \"stl\t%1, %0\"; >>>> + return \"stl%?\t%1, %0\"; >>>> } >>>> ) >>>> > --f46d04182626c4a6e9051799b3e3 Content-Type: text/plain; charset=US-ASCII; name="Fix_slt_lda_missing_conditional_code.diff" Content-Disposition: attachment; filename="Fix_slt_lda_missing_conditional_code.diff" Content-Transfer-Encoding: base64 X-Attachment-Id: f_iagj6pbk0 Content-length: 1729 ZGlmZiAtLWdpdCBhL2djYy9jb25maWcvYXJtL3N5bmMubWQgYi9nY2MvY29u ZmlnL2FybS9zeW5jLm1kCmluZGV4IDQ0Y2RhNjEuLmNmOGYzYTMgMTAwNjQ0 Ci0tLSBhL2djYy9jb25maWcvYXJtL3N5bmMubWQKKysrIGIvZ2NjL2NvbmZp Zy9hcm0vc3luYy5tZApAQCAtNzUsMTEgKzc1LDEyIEBACiAgIHsKICAgICBl bnVtIG1lbW1vZGVsIG1vZGVsID0gbWVtbW9kZWxfZnJvbV9pbnQgKElOVFZB TCAob3BlcmFuZHNbMl0pKTsKICAgICBpZiAoaXNfbW1fcmVsYXhlZCAobW9k ZWwpIHx8IGlzX21tX2NvbnN1bWUgKG1vZGVsKSB8fCBpc19tbV9yZWxlYXNl IChtb2RlbCkpCi0gICAgICByZXR1cm4gXCJsZHI8c3luY19zZng+XFx0JTAs ICUxXCI7CisgICAgICByZXR1cm4gXCJsZHI8c3luY19zZng+JT9cXHQlMCwg JTFcIjsKICAgICBlbHNlCi0gICAgICByZXR1cm4gXCJsZGE8c3luY19zZng+ XFx0JTAsICUxXCI7CisgICAgICByZXR1cm4gXCJsZGE8c3luY19zZng+JT9c XHQlMCwgJTFcIjsKICAgfQotKQorICBbKHNldF9hdHRyICJwcmVkaWNhYmxl IiAieWVzIikKKyAgIChzZXRfYXR0ciAicHJlZGljYWJsZV9zaG9ydF9pdCIg Im5vIildKQogCiAoZGVmaW5lX2luc24gImF0b21pY19zdG9yZTxtb2RlPiIK ICAgWyhzZXQgKG1hdGNoX29wZXJhbmQ6UUhTSSAwICJtZW1vcnlfb3BlcmFu ZCIgIj1RIikKQEAgLTkxLDExICs5MiwxMiBAQAogICB7CiAgICAgZW51bSBt ZW1tb2RlbCBtb2RlbCA9IG1lbW1vZGVsX2Zyb21faW50IChJTlRWQUwgKG9w ZXJhbmRzWzJdKSk7CiAgICAgaWYgKGlzX21tX3JlbGF4ZWQgKG1vZGVsKSB8 fCBpc19tbV9jb25zdW1lIChtb2RlbCkgfHwgaXNfbW1fYWNxdWlyZSAobW9k ZWwpKQotICAgICAgcmV0dXJuIFwic3RyPHN5bmNfc2Z4Plx0JTEsICUwXCI7 CisgICAgICByZXR1cm4gXCJzdHI8c3luY19zZng+JT9cdCUxLCAlMFwiOwog ICAgIGVsc2UKLSAgICAgIHJldHVybiBcInN0bDxzeW5jX3NmeD5cdCUxLCAl MFwiOworICAgICAgcmV0dXJuIFwic3RsPHN5bmNfc2Z4PiU/XHQlMSwgJTBc IjsKICAgfQotKQorICBbKHNldF9hdHRyICJwcmVkaWNhYmxlIiAieWVzIikK KyAgIChzZXRfYXR0ciAicHJlZGljYWJsZV9zaG9ydF9pdCIgIm5vIildKQog CiA7OyBOb3RlIHRoYXQgbGRyZCBhbmQgdmxkciBhcmUgKm5vdCogZ3VhcmFu dGVlZCB0byBiZSBzaW5nbGUtY29weSBhdG9taWMsCiA7OyBldmVuIGZvciBh IDY0LWJpdCBhbGlnbmVkIGFkZHJlc3MuICBJbnN0ZWFkIHdlIHVzZSBhIGxk cmV4ZCB1bnBhcmllZAo= --f46d04182626c4a6e9051799b3e3--