* [PATCH GCC]Enable vect_cond_mixed for AArch64.
@ 2016-05-17 9:04 Bin Cheng
2016-05-17 20:33 ` Jeff Law
0 siblings, 1 reply; 3+ messages in thread
From: Bin Cheng @ 2016-05-17 9:04 UTC (permalink / raw)
To: gcc-patches; +Cc: nd
[-- Attachment #1: Type: text/plain, Size: 719 bytes --]
Hi,
After supporting all vcond/vcondu patterns in AArch64 backend, now we can vectorize VEC_COND_EXPR with different type in comparison operands and value operands on AArch64. GCC uses vect_cond_mixed to control such test cases, for now, there are below cases affected by it:
pr61194.c
This was failed for all targets, but was just fixed by my previous tree ifcvt patch.
slp-cond-2-big-array.c
slp-cond-2.c
vect-cond-10.c
vect-cond-8.c
vect-cond-9.c
They will start passing after this patch.
Test on AArch64. Is it OK?
Thanks,
bin
gcc/testsuite/ChangeLog
2016-05-12 Bin Cheng <bin.cheng@arm.com>
* lib/target-supports.exp (check_effective_target_vect_cond_mixed):
Add aarch64*-*-*.
[-- Attachment #2: enable-vect_cond_mixed-for-aarch64.txt --]
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diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 04ca176..db6b01e 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -5007,6 +5007,7 @@ proc check_effective_target_vect_cond_mixed { } {
} else {
set et_vect_cond_mixed_saved 0
if { [istarget i?86-*-*] || [istarget x86_64-*-*]
+ || [istarget aarch64*-*-*]
|| [istarget powerpc*-*-*] } {
set et_vect_cond_mixed_saved 1
}
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH GCC]Enable vect_cond_mixed for AArch64.
2016-05-17 9:04 [PATCH GCC]Enable vect_cond_mixed for AArch64 Bin Cheng
@ 2016-05-17 20:33 ` Jeff Law
2016-05-18 7:51 ` Bin.Cheng
0 siblings, 1 reply; 3+ messages in thread
From: Jeff Law @ 2016-05-17 20:33 UTC (permalink / raw)
To: Bin Cheng, gcc-patches; +Cc: nd
On 05/17/2016 03:04 AM, Bin Cheng wrote:
> Hi,
> After supporting all vcond/vcondu patterns in AArch64 backend, now we can vectorize VEC_COND_EXPR with different type in comparison operands and value operands on AArch64. GCC uses vect_cond_mixed to control such test cases, for now, there are below cases affected by it:
>
> pr61194.c
> This was failed for all targets, but was just fixed by my previous tree ifcvt patch.
> slp-cond-2-big-array.c
> slp-cond-2.c
> vect-cond-10.c
> vect-cond-8.c
> vect-cond-9.c
>
> They will start passing after this patch.
>
> Test on AArch64. Is it OK?
>
> Thanks,
> bin
>
> gcc/testsuite/ChangeLog
> 2016-05-12 Bin Cheng <bin.cheng@arm.com>
>
> * lib/target-supports.exp (check_effective_target_vect_cond_mixed):
> Add aarch64*-*-*.
OK.
jeff
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH GCC]Enable vect_cond_mixed for AArch64.
2016-05-17 20:33 ` Jeff Law
@ 2016-05-18 7:51 ` Bin.Cheng
0 siblings, 0 replies; 3+ messages in thread
From: Bin.Cheng @ 2016-05-18 7:51 UTC (permalink / raw)
To: Jeff Law; +Cc: gcc-patches
On Tue, May 17, 2016 at 9:33 PM, Jeff Law <law@redhat.com> wrote:
> On 05/17/2016 03:04 AM, Bin Cheng wrote:
>>
>> Hi,
>> After supporting all vcond/vcondu patterns in AArch64 backend, now we can
>> vectorize VEC_COND_EXPR with different type in comparison operands and value
>> operands on AArch64. GCC uses vect_cond_mixed to control such test cases,
>> for now, there are below cases affected by it:
>>
>> pr61194.c
>> This was failed for all targets, but was just fixed by my previous
>> tree ifcvt patch.
>> slp-cond-2-big-array.c
>> slp-cond-2.c
>> vect-cond-10.c
>> vect-cond-8.c
>> vect-cond-9.c
>>
>> They will start passing after this patch.
>>
>> Test on AArch64. Is it OK?
>>
>> Thanks,
>> bin
>>
>> gcc/testsuite/ChangeLog
>> 2016-05-12 Bin Cheng <bin.cheng@arm.com>
>>
>> * lib/target-supports.exp
>> (check_effective_target_vect_cond_mixed):
>> Add aarch64*-*-*.
>
> OK.
Thanks for approving this, I will apply this after the AArch64's vcond
patch @ https://gcc.gnu.org/ml/gcc-patches/2016-05/msg01182.html.
Thanks,
bin
> jeff
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2016-05-17 20:33 ` Jeff Law
2016-05-18 7:51 ` Bin.Cheng
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