From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pg1-x536.google.com (mail-pg1-x536.google.com [IPv6:2607:f8b0:4864:20::536]) by sourceware.org (Postfix) with ESMTPS id B8AFB3858C2B for ; Tue, 12 Sep 2023 19:09:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B8AFB3858C2B Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-pg1-x536.google.com with SMTP id 41be03b00d2f7-573d52030fbso4146360a12.0 for ; Tue, 12 Sep 2023 12:09:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694545763; x=1695150563; darn=gcc.gnu.org; h=to:subject:message-id:date:from:mime-version:from:to:cc:subject :date:message-id:reply-to; bh=OxdaojPvePga9uU/D1IZKwTmM2sr2/2Q1ILq6d1JUNg=; b=VIJEbOsEyKGeKE5zf/f+eZD45d6Vu7I8j78ueSVHQb+rvh7vICpsN9f0G9v8Z6SibY sHMJ/eK3Atcdi7lVFjtI09L/UGKU2El3+0lff+VyU/HTdKphxEefPgUZnDqn76Byyp1M qVle+D/m+NnQhp/SL8WIDKnJ7llw0dyZc3KogUYqRv24vxLyyrNcksyqQXsZp5xaLhgD ADPBje9uP18OZ5yn2mS3zXN6zhtD5y2h5L2wryLcFkZY0px9QFMBSIdLugALbhg/JQDb BKhy+cGXAyVdRoIrk44qkbB27F8EHj0LMZy7q6ZsG46cWVjQs9ifp0oQrVrInJu4bFTg XbmQ== X-Google-DKIM-Signature: v=1; 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boundary="000000000000465b3c06052e2ef6" X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT,FREEMAIL_FROM,GIT_PATCH_0,HTML_MESSAGE,KAM_LOTSOFHASH,KAM_SHORT,LIKELY_SPAM_BODY,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --000000000000465b3c06052e2ef6 Content-Type: multipart/alternative; boundary="000000000000465b3b06052e2ef4" --000000000000465b3b06052e2ef4 Content-Type: text/plain; charset="UTF-8" In the case when we have C code like this int foo (int a) { return 100 & ~a; } GCC generates the following instruction sequence foo: not a0,a0 andi a0,a0,100 ret This patch replaces that with this sequence foo: li a5,100 andn a0,a5,a0 ret The profitability comes from an out-of-order processor being able to issue the "li a5, 100" at any time after it's fetched while "not a0, a0" has to wait until any prior setter of a0 has reached completion. gcc/ChangeLog: * config/riscv/bitmanip.md (*_not_const): New split pattern. gcc/testsuite/ChangeLog: * gcc.target/riscv/zbb-andn-orn-01.c: New test. * gcc.target/riscv/zbb-andn-orn-02.c: Likewise. -- With the best regards Jivan Hakobyan --000000000000465b3b06052e2ef4-- --000000000000465b3c06052e2ef6 Content-Type: text/x-patch; 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