`This patch tries to prevent generating unnecessary sign extension
after *w instructions like "addiw" or "divw".

The main idea of it is to add SUBREG_PROMOTED fields during expanding.

I have tested on SPEC2017 there is no regression.
Only gcc.dg/pr30957-1.c test failed.
To solve that I did some changes in loop-iv.cc, but not sure that it is
suitable.


gcc/ChangeLog:
        * config/riscv/bitmanip.md (rotrdi3): New pattern.
        (rotrsi3): Likewise.
        (rotlsi3): Likewise.
        * config/riscv/riscv-protos.h (riscv_emit_binary): New function
        declaration
        * config/riscv/riscv.cc (riscv_emit_binary): Removed static
        * config/riscv/riscv.md (addsi3): New pattern
        (subsi3): Likewise.
        (negsi2): Likewise.
        (mulsi3): Likewise.
        (<optab>si3): New pattern for any_div.
        (<optab>si3): New pattern for any_shift.
        * loop-iv.cc (get_biv_step_1):  Process src of extension when it
PLUS

gcc/testsuite/ChangeLog:
        * testsuite/gcc.target/riscv/shift-and-2.c: New test
        * testsuite/gcc.target/riscv/shift-shift-2.c: New test
        * testsuite/gcc.target/riscv/sign-extend.c: New test
        * testsuite/gcc.target/riscv/zbb-rol-ror-03.c: New test


-- 
With the best regards
Jivan Hakobyan