From: Jivan Hakobyan <jivanhakobyan9@gmail.com>
To: gcc-patches@gcc.gnu.org
Subject: RISC-V: Replace unspec with bitreverse in riscv_brev8_<mode> insn
Date: Wed, 26 Jul 2023 11:54:53 +0400 [thread overview]
Message-ID: <CAHso6sP4X5xFOS0295td32=BBvbtbbN2=h+G7SEJkeQ8hWrUKw@mail.gmail.com> (raw)
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This small patch replaces unspec opcode with bitreverse in
riscv_brev8_<mode> insn.
gcc/ChangeLog:
* config/riscv/crypto.md (UNSPEC_BREV8): Remov.
(riscv_brev8_<mode>): Use bitreverse opcode.
--
With the best regards
Jivan Hakobyan
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diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index e4b7f0190df..d40e108b10d 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -19,7 +19,6 @@
(define_c_enum "unspec" [
;; Zbkb unspecs
- UNSPEC_BREV8
UNSPEC_ZIP
UNSPEC_UNZIP
UNSPEC_PACK
@@ -73,8 +72,7 @@
;; ZBKB extension
(define_insn "riscv_brev8_<mode>"
[(set (match_operand:X 0 "register_operand" "=r")
- (unspec:X [(match_operand:X 1 "register_operand" "r")]
- UNSPEC_BREV8))]
+ (bitreverse:X (match_operand:X 1 "register_operand" "r")))]
"TARGET_ZBKB"
"brev8\t%0,%1"
[(set_attr "type" "crypto")])
next reply other threads:[~2023-07-26 7:55 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-26 7:54 Jivan Hakobyan [this message]
2023-07-26 8:21 ` Kito Cheng
2023-07-26 16:23 ` Jeff Law
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