From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oo1-xc35.google.com (mail-oo1-xc35.google.com [IPv6:2607:f8b0:4864:20::c35]) by sourceware.org (Postfix) with ESMTPS id 935EE3846423 for ; Tue, 25 Jun 2024 03:14:49 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 935EE3846423 Authentication-Results: sourceware.org; dmarc=pass (p=quarantine dis=none) header.from=bytedance.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=bytedance.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 935EE3846423 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::c35 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1719285292; cv=none; b=KnHmbdDZQAuQDliHfouyTdJo3RrjrYU9fSZ9qWrFEAaIcshV+oEgIGyz8m9RXDp+46YAdAI1mweRP137NiHEoNNFFJCOyU1OnUXpP9nPxe6LTm7yprW4ci30r236Thunm17S26l6foHi120ojqHAfnZe3vAxGaAhdEFnFROkmVc= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1719285292; c=relaxed/simple; bh=opNpQ4JzTKzYM0OG1DQvOFivmL6ZOQvnonAfIerkwyc=; h=DKIM-Signature:Mime-Version:From:Date:Message-ID:Subject:To; b=NK4F1iXQqbiakcp6fbxfM8rzFCiwfuf2/Vofhzdhf0QMNoS9e5nPqlD2BihYk4GQdZyJQP6rIXze17EvdpPuxEBWZnonVjnWUEI5QgTLbq8kONJL/515mxn5NkPYdJL64qyOVpIoex7N3OcrbykcbE8tnaobX8BG6VnzgJhIRZY= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-oo1-xc35.google.com with SMTP id 006d021491bc7-5baf982f56dso2520012eaf.3 for ; Mon, 24 Jun 2024 20:14:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bytedance.com; s=google; t=1719285289; x=1719890089; darn=gcc.gnu.org; h=cc:to:subject:message-id:date:references:from:mime-version :user-agent:in-reply-to:from:to:cc:subject:date:message-id:reply-to; bh=b5peJIDwYIRkkV/tIlK8D2gz2mVm24uz0ewNqhuFn1A=; b=DeTaQh7mb6k73KR7Jl/ASRljilcyZzF4rS6yIXiy6qMAJAAmaE5QRA2o6NpxALzh7j +fheuFgJgK9NeCD7vGkKaMp1fiWgTH8Nt9JI/WqEDUY6oYhs9WqZ6/YpN1bj9hA/GYWP ygBu4OmXe4h3pyT/KP0vZ7ZWkdlfKpShlJOilnl6PaPjOr6o8JsWjlgP34MpZT86r3Nk Y6uZgieCOruLwy8rCtCZ4fg/xqbrDzpHaOD/MzXEs/KZcVbbjdTfwb2mvc2v9EXdMMeQ jvXt+554Ml/Enrpds6xvID5w6b1TEdraR8+BJO7NmfL+43RA0A3WsduezBOTLbcfK8NM PRXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719285289; x=1719890089; h=cc:to:subject:message-id:date:references:from:mime-version :user-agent:in-reply-to:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=b5peJIDwYIRkkV/tIlK8D2gz2mVm24uz0ewNqhuFn1A=; b=vStmV9gTdsrq6gI5pa8SIgPCfxja2Vdz2Jq3UciPCah4jCMh0uUF2QwFdnYI4BVk7D j0rvukSAMH8Wb7sXG72jEXELpqFUzctJwvYOczRlkO3fFWz3ooH/xchkeFgmBunuYUXz k7TMZY3yUBV3gYQe3gsDJFi0Pp6ITnFmqNQv8CwYTbbmHnjmqgsV1hqlGPkqrIWIyDt2 oZ9zTErkCrKOYO2oXrpiIzRWPld0VtZaTDOpy8N0Gp7UkMwXqim6ttCx7NyYH0+JH7zw 1gEZbDgvH7bHFXRau0yMDv/+AVGLwWZk/Xidyd2RR9HoqchCFYqmQVRE6XgeMR9VVZVB ByUQ== X-Gm-Message-State: AOJu0YxkLxCZK+oeULEysSkgipBDUSjyAnbC543augITvntrnB90otEy ndyXJ86oYR3gBf2BPZ0m3XJrbfs35JELs+7OxmtJGkO8lTIuXoAanmO7dpyJarAxHPB07I/ne7J Uf+7eEhJ7FdRXBzhKRS0Jg1KbhY8KxkQj0MqKqCZGNBNF7F59ZYc= X-Google-Smtp-Source: AGHT+IFh27uCVFGUjWvyt/muZjnTTw+vTBLwxkzPGKvVGm52CfR4lg3C6/mshiQFk47zGAye9OjpTeDNsu5AOYeCpLc= X-Received: by 2002:a4a:3402:0:b0:5b9:89d9:c601 with SMTP id 006d021491bc7-5c1eed38814mr6037673eaf.5.1719285288812; Mon, 24 Jun 2024 20:14:48 -0700 (PDT) Received: from 44278815321 named unknown by gmailapi.google.com with HTTPREST; Mon, 24 Jun 2024 23:14:48 -0400 X-Original-From: Wang Pengcheng In-Reply-To: User-Agent: Mozilla Thunderbird Mime-Version: 1.0 From: Wang Pengcheng References: Date: Mon, 24 Jun 2024 23:14:48 -0400 Message-ID: Subject: Re: Re: [PATCH] RISC-V: Support -m[no-]unaligned-access To: Palmer Dabbelt Cc: gcc-patches@gcc.gnu.org Content-Type: multipart/alternative; boundary="000000000000e86307061bae4c00" X-Spam-Status: No, score=-8.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_MUA_MOZILLA,GIT_PATCH_0,HTML_MESSAGE,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --000000000000e86307061bae4c00 Content-Type: text/plain; charset="UTF-8" Thanks for taking a look! Things have changed after I posted this patch and LLVM doesn't support this option now, so I think we don't need this patch any more. Please see this PR and its references: https://github.com/riscv-non-isa/riscv-c-api-doc/pull/62. On 2024/6/25 2:17, Palmer Dabbelt wrote: > On Fri, 22 Dec 2023 01:23:13 PST (-0800), wangpengcheng.pp@bytedance.com > wrote: >> These two options are negative alias of -m[no-]strict-align. >> >> This matches LLVM implmentation. >> >> gcc/ChangeLog: >> >> * config/riscv/riscv.opt: Add option alias. >> >> gcc/testsuite/ChangeLog: >> >> * gcc.target/riscv/predef-align-10.c: New test. >> * gcc.target/riscv/predef-align-7.c: New test. >> * gcc.target/riscv/predef-align-8.c: New test. >> * gcc.target/riscv/predef-align-9.c: New test. >> >> Signed-off-by: Wang Pengcheng > > Sorry for being slow here. With the scalar/vector alignment split we're > cleaning up a bunch of these LLVM/GCC differences, and we're waiting for > the LLVM folks to decide how these are going to behave. LLVM will > release well before GCC does, so we've got some time. > > So this isn't lost, just slow. > >> --- >> gcc/config/riscv/riscv.opt | 4 ++++ >> gcc/testsuite/gcc.target/riscv/predef-align-10.c | 16 ++++++++++++++++ >> gcc/testsuite/gcc.target/riscv/predef-align-7.c | 15 +++++++++++++++ >> gcc/testsuite/gcc.target/riscv/predef-align-8.c | 16 ++++++++++++++++ >> gcc/testsuite/gcc.target/riscv/predef-align-9.c | 15 +++++++++++++++ >> 5 files changed, 66 insertions(+) >> create mode 100644 gcc/testsuite/gcc.target/riscv/predef-align-10.c >> create mode 100644 gcc/testsuite/gcc.target/riscv/predef-align-7.c >> create mode 100644 gcc/testsuite/gcc.target/riscv/predef-align-8.c >> create mode 100644 gcc/testsuite/gcc.target/riscv/predef-align-9.c >> >> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt >> index cf207d4dcdf..1e22998ce6e 100644 >> --- a/gcc/config/riscv/riscv.opt >> +++ b/gcc/config/riscv/riscv.opt >> @@ -116,6 +116,10 @@ mstrict-align >> Target Mask(STRICT_ALIGN) Save >> Do not generate unaligned memory accesses. >> >> +munaligned-access >> +Target Alias(mstrict-align) NegativeAlias >> +Enable unaligned memory accesses. >> + >> Enum >> Name(code_model) Type(enum riscv_code_model) >> Known code models (for use with the -mcmodel= option): >> diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-10.c >> b/gcc/testsuite/gcc.target/riscv/predef-align-10.c >> new file mode 100644 >> index 00000000000..c86b2c7a5ed >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/riscv/predef-align-10.c >> @@ -0,0 +1,16 @@ >> +/* { dg-do compile } */ >> +/* { dg-options "-mtune=rocket -munaligned-access" } */ >> + >> +int main() { >> + >> +/* rocket default is cpu tune param misaligned access slow */ >> +#if !defined(__riscv_misaligned_slow) >> +#error "__riscv_misaligned_slow is not set" >> +#endif >> + >> +#if defined(__riscv_misaligned_avoid) || >> defined(__riscv_misaligned_fast) >> +#error "__riscv_misaligned_avoid or __riscv_misaligned_fast is >> unexpectedly set" >> +#endif >> + >> + return 0; >> +} >> diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-7.c >> b/gcc/testsuite/gcc.target/riscv/predef-align-7.c >> new file mode 100644 >> index 00000000000..405f3686c2e >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/riscv/predef-align-7.c >> @@ -0,0 +1,15 @@ >> +/* { dg-do compile } */ >> +/* { dg-options "-mtune=thead-c906 -mno-unaligned-access" } */ >> + >> +int main() { >> + >> +#if !defined(__riscv_misaligned_avoid) >> +#error "__riscv_misaligned_avoid is not set" >> +#endif >> + >> +#if defined(__riscv_misaligned_fast) || defined(__riscv_misaligned_slow) >> +#error "__riscv_misaligned_fast or __riscv_misaligned_slow is >> unexpectedly >> set" >> +#endif >> + >> + return 0; >> +} >> diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-8.c >> b/gcc/testsuite/gcc.target/riscv/predef-align-8.c >> new file mode 100644 >> index 00000000000..64072c04a47 >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/riscv/predef-align-8.c >> @@ -0,0 +1,16 @@ >> +/* { dg-do compile } */ >> +/* { dg-options "-mtune=thead-c906 -munaligned-access" } */ >> + >> +int main() { >> + >> +/* thead-c906 default is cpu tune param misaligned access fast */ >> +#if !defined(__riscv_misaligned_fast) >> +#error "__riscv_misaligned_fast is not set" >> +#endif >> + >> +#if defined(__riscv_misaligned_avoid) || >> defined(__riscv_misaligned_slow) >> +#error "__riscv_misaligned_avoid or __riscv_misaligned_slow is >> unexpectedly set" >> +#endif >> + >> + return 0; >> +} >> diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-9.c >> b/gcc/testsuite/gcc.target/riscv/predef-align-9.c >> new file mode 100644 >> index 00000000000..f5418de87cf >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/riscv/predef-align-9.c >> @@ -0,0 +1,15 @@ >> +/* { dg-do compile } */ >> +/* { dg-options "-mtune=rocket -mno-unaligned-access" } */ >> + >> +int main() { >> + >> +#if !defined(__riscv_misaligned_avoid) >> +#error "__riscv_misaligned_avoid is not set" >> +#endif >> + >> +#if defined(__riscv_misaligned_fast) || defined(__riscv_misaligned_slow) >> +#error "__riscv_misaligned_fast or __riscv_misaligned_slow is >> unexpectedly >> set" >> +#endif >> + >> + return 0; >> +} --000000000000e86307061bae4c00--