From: Ramana Radhakrishnan <ramana.gcc@googlemail.com>
To: Christophe Lyon <christophe.lyon@linaro.org>
Cc: gcc-patches <gcc-patches@gcc.gnu.org>
Subject: Re: [Patch ARM-AArch64/testsuite v2 02/21] Add unary operators: vabs and vneg.
Date: Thu, 03 Jul 2014 11:07:00 -0000 [thread overview]
Message-ID: <CAJA7tRZL60ZcWuhwE8Q_oHHGSzHfhtSMWLbiUBssdEy05mrEFQ@mail.gmail.com> (raw)
In-Reply-To: <1404209174-25364-3-git-send-email-christophe.lyon@linaro.org>
On Tue, Jul 1, 2014 at 11:05 AM, Christophe Lyon
<christophe.lyon@linaro.org> wrote:
>
> diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
> index 3a0f99b..44c4990 100644
> --- a/gcc/testsuite/ChangeLog
> +++ b/gcc/testsuite/ChangeLog
> @@ -1,5 +1,11 @@
> 2014-06-30 Christophe Lyon <christophe.lyon@linaro.org>
>
> + * gcc.target/aarch64/neon-intrinsics/unary_op.inc: New file.
> + * gcc.target/aarch64/neon-intrinsics/vabs.c: Likewise.
> + * gcc.target/aarch64/neon-intrinsics/vneg.c: Likewise.
> +
> +2014-06-30 Christophe Lyon <christophe.lyon@linaro.org>
> +
> * gcc.target/arm/README.neon-intrinsics: New file.
> * gcc.target/aarch64/neon-intrinsics/README: Likewise.
> * gcc.target/aarch64/neon-intrinsics/arm-neon-ref.h: Likewise.
Ok for ARM if no regressions.
Wait for an ack from AArch64 maintainers.
Ramana
> diff --git a/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/unary_op.inc b/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/unary_op.inc
> new file mode 100644
> index 0000000..33f9b5f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/unary_op.inc
> @@ -0,0 +1,72 @@
> +/* Template file for unary operator validation.
> +
> + This file is meant to be included by the relevant test files, which
> + have to define the intrinsic family to test. If a given intrinsic
> + supports variants which are not supported by all the other unary
> + operators, these can be tested by providing a definition for
> + EXTRA_TESTS. */
> +
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +#define FNNAME1(NAME) exec_ ## NAME
> +#define FNNAME(NAME) FNNAME1(NAME)
> +
> +void FNNAME (INSN_NAME) (void)
> +{
> + /* Basic test: y=OP(x), then store the result. */
> +#define TEST_UNARY_OP1(INSN, Q, T1, T2, W, N) \
> + VECT_VAR(vector_res, T1, W, N) = \
> + INSN##Q##_##T2##W(VECT_VAR(vector, T1, W, N)); \
> + vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
> +
> +#define TEST_UNARY_OP(INSN, Q, T1, T2, W, N) \
> + TEST_UNARY_OP1(INSN, Q, T1, T2, W, N) \
> +
> + /* No need for 64 bits variants in the general case. */
> + DECL_VARIABLE(vector, int, 8, 8);
> + DECL_VARIABLE(vector, int, 16, 4);
> + DECL_VARIABLE(vector, int, 32, 2);
> + DECL_VARIABLE(vector, int, 8, 16);
> + DECL_VARIABLE(vector, int, 16, 8);
> + DECL_VARIABLE(vector, int, 32, 4);
> +
> + DECL_VARIABLE(vector_res, int, 8, 8);
> + DECL_VARIABLE(vector_res, int, 16, 4);
> + DECL_VARIABLE(vector_res, int, 32, 2);
> + DECL_VARIABLE(vector_res, int, 8, 16);
> + DECL_VARIABLE(vector_res, int, 16, 8);
> + DECL_VARIABLE(vector_res, int, 32, 4);
> +
> + clean_results ();
> +
> + /* Initialize input "vector" from "buffer". */
> + VLOAD(vector, buffer, , int, s, 8, 8);
> + VLOAD(vector, buffer, , int, s, 16, 4);
> + VLOAD(vector, buffer, , int, s, 32, 2);
> + VLOAD(vector, buffer, q, int, s, 8, 16);
> + VLOAD(vector, buffer, q, int, s, 16, 8);
> + VLOAD(vector, buffer, q, int, s, 32, 4);
> +
> + /* Apply a unary operator named INSN_NAME. */
> + TEST_UNARY_OP(INSN_NAME, , int, s, 8, 8);
> + TEST_UNARY_OP(INSN_NAME, , int, s, 16, 4);
> + TEST_UNARY_OP(INSN_NAME, , int, s, 32, 2);
> + TEST_UNARY_OP(INSN_NAME, q, int, s, 8, 16);
> + TEST_UNARY_OP(INSN_NAME, q, int, s, 16, 8);
> + TEST_UNARY_OP(INSN_NAME, q, int, s, 32, 4);
> +
> + CHECK_RESULTS (TEST_MSG, "");
> +
> +#ifdef EXTRA_TESTS
> + EXTRA_TESTS();
> +#endif
> +}
> +
> +int main (void)
> +{
> + FNNAME (INSN_NAME)();
> +
> + return 0;
> +}
> diff --git a/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/vabs.c b/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/vabs.c
> new file mode 100644
> index 0000000..ca3901a
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/vabs.c
> @@ -0,0 +1,74 @@
> +#define INSN_NAME vabs
> +#define TEST_MSG "VABS/VABSQ"
> +
> +/* Extra tests for functions requiring floating-point types. */
> +void exec_vabs_f32(void);
> +#define EXTRA_TESTS exec_vabs_f32
> +
> +#include "unary_op.inc"
> +
> +/* Expected results. */
> +VECT_VAR_DECL(expected,int,8,8) [] = { 0x10, 0xf, 0xe, 0xd,
> + 0xc, 0xb, 0xa, 0x9 };
> +VECT_VAR_DECL(expected,int,16,4) [] = { 0x10, 0xf, 0xe, 0xd };
> +VECT_VAR_DECL(expected,int,32,2) [] = { 0x10, 0xf };
> +VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
> +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected,int,8,16) [] = { 0x10, 0xf, 0xe, 0xd, 0xc, 0xb, 0xa, 0x9,
> + 0x8, 0x7, 0x6, 0x5, 0x4, 0x3, 0x2, 0x1 };
> +VECT_VAR_DECL(expected,int,16,8) [] = { 0x10, 0xf, 0xe, 0xd,
> + 0xc, 0xb, 0xa, 0x9 };
> +VECT_VAR_DECL(expected,int,32,4) [] = { 0x10, 0xf, 0xe, 0xd };
> +VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected,uint,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +
> +/* Expected results for float32 variants. Needs to be separated since
> + the generic test function does not test floating-point
> + versions. */
> +VECT_VAR_DECL(expected_float32,hfloat,32,2) [] = { 0x40133333, 0x40133333 };
> +VECT_VAR_DECL(expected_float32,hfloat,32,4) [] = { 0x4059999a, 0x4059999a,
> + 0x4059999a, 0x4059999a };
> +
> +void exec_vabs_f32(void)
> +{
> + DECL_VARIABLE(vector, float, 32, 2);
> + DECL_VARIABLE(vector, float, 32, 4);
> +
> + DECL_VARIABLE(vector_res, float, 32, 2);
> + DECL_VARIABLE(vector_res, float, 32, 4);
> +
> + VDUP(vector, , float, f, 32, 2, -2.3f);
> + VDUP(vector, q, float, f, 32, 4, 3.4f);
> +
> + TEST_UNARY_OP(INSN_NAME, , float, f, 32, 2);
> + TEST_UNARY_OP(INSN_NAME, q, float, f, 32, 4);
> +
> + CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_float32, "");
> + CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_float32, "");
> +}
> diff --git a/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/vneg.c b/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/vneg.c
> new file mode 100644
> index 0000000..c45492d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/vneg.c
> @@ -0,0 +1,74 @@
> +#define INSN_NAME vneg
> +#define TEST_MSG "VNEG/VNEGQ"
> +
> +/* Extra tests for functions requiring floating-point types. */
> +void exec_vneg_f32(void);
> +#define EXTRA_TESTS exec_vneg_f32
> +
> +#include "unary_op.inc"
> +
> +/* Expected results. */
> +VECT_VAR_DECL(expected,int,8,8) [] = { 0x10, 0xf, 0xe, 0xd,
> + 0xc, 0xb, 0xa, 0x9 };
> +VECT_VAR_DECL(expected,int,16,4) [] = { 0x10, 0xf, 0xe, 0xd };
> +VECT_VAR_DECL(expected,int,32,2) [] = { 0x10, 0xf };
> +VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
> +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected,int,8,16) [] = { 0x10, 0xf, 0xe, 0xd, 0xc, 0xb, 0xa, 0x9,
> + 0x8, 0x7, 0x6, 0x5, 0x4, 0x3, 0x2, 0x1 };
> +VECT_VAR_DECL(expected,int,16,8) [] = { 0x10, 0xf, 0xe, 0xd,
> + 0xc, 0xb, 0xa, 0x9 };
> +VECT_VAR_DECL(expected,int,32,4) [] = { 0x10, 0xf, 0xe, 0xd };
> +VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected,uint,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +
> +/* Expected results for float32 variants. Needs to be separated since
> + the generic test function does not test floating-point
> + versions. */
> +VECT_VAR_DECL(expected_float32,hfloat,32,2) [] = { 0xc0133333, 0xc0133333 };
> +VECT_VAR_DECL(expected_float32,hfloat,32,4) [] = { 0xc059999a, 0xc059999a,
> + 0xc059999a, 0xc059999a };
> +
> +void exec_vneg_f32(void)
> +{
> + DECL_VARIABLE(vector, float, 32, 2);
> + DECL_VARIABLE(vector, float, 32, 4);
> +
> + DECL_VARIABLE(vector_res, float, 32, 2);
> + DECL_VARIABLE(vector_res, float, 32, 4);
> +
> + VDUP(vector, , float, f, 32, 2, 2.3f);
> + VDUP(vector, q, float, f, 32, 4, 3.4f);
> +
> + TEST_UNARY_OP(INSN_NAME, , float, f, 32, 2);
> + TEST_UNARY_OP(INSN_NAME, q, float, f, 32, 4);
> +
> + CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_float32, "");
> + CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_float32, "");
> +}
> --
> 1.8.3.2
>
next prev parent reply other threads:[~2014-07-03 11:07 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-01 10:07 [Patch ARM-AArch64/testsuite v2 00/21] Neon intrinsics executable tests Christophe Lyon
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 14/21] Add vbsl tests Christophe Lyon
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 21/21] Add vuzp and vzip tests Christophe Lyon
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 12/21] Add vaddl tests Christophe Lyon
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 19/21] Add vld2_lane, vld3_lane and vld4_lane Christophe Lyon
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 13/21] Add vaddw tests Christophe Lyon
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 15/21] Add vclz tests Christophe Lyon
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 04/21] Add comparison operators: vceq, vcge, vcgt, vcle and vclt Christophe Lyon
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 20/21] Add vmul tests Christophe Lyon
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 18/21] Add vld2/vld3/vld4 tests Christophe Lyon
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 01/21] Neon intrinsics execution tests initial framework Christophe Lyon
2014-07-03 11:06 ` Ramana Radhakrishnan
2014-07-03 21:04 ` Christophe Lyon
2014-07-10 10:12 ` Marcus Shawcroft
2014-07-11 10:41 ` Richard Earnshaw
2014-09-30 14:27 ` Christophe Lyon
2014-10-01 15:11 ` Marcus Shawcroft
2014-10-07 13:33 ` Christophe Lyon
2014-10-08 12:16 ` Ramana Radhakrishnan
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 06/21] Add unary saturating operators: vqabs and vqneg Christophe Lyon
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 16/21] Add vdup and vmov tests Christophe Lyon
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 11/21] Add vaddhn tests Christophe Lyon
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 10/21] Add vabdl tests Christophe Lyon
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 03/21] Add binary operators: vadd, vand, vbic, veor, vorn, vorr, vsub Christophe Lyon
2014-07-03 11:08 ` Ramana Radhakrishnan
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 17/21] Add vld1_dup tests Christophe Lyon
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 02/21] Add unary operators: vabs and vneg Christophe Lyon
2014-07-03 11:07 ` Ramana Radhakrishnan [this message]
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 08/21] Add vabal tests Christophe Lyon
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 05/21] Add comparison operators with floating-point operands: vcage, vcagt, vcale and cvalt Christophe Lyon
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 09/21] Add vabd tests Christophe Lyon
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 07/21] Add binary saturating operators: vqadd, vqsub Christophe Lyon
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