From: Ramana Radhakrishnan <ramana.gcc@googlemail.com>
To: gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Richard Earnshaw <Richard.Earnshaw@arm.com>
Subject: [Patch Arm] Fix PR 92999
Date: Tue, 8 Nov 2022 18:20:20 +0000 [thread overview]
Message-ID: <CAJA7tRZonrXGHcaqVLNduyoAXa8mT+5TiYk29PsXd4sBwfa2JA@mail.gmail.com> (raw)
[-- Attachment #1: Type: text/plain, Size: 616 bytes --]
PR92999 is a case where the VFP calling convention does not allocate
enough FP registers for a homogenous aggregate containing FP16 values.
I believe this is the complete fix but would appreciate another set of
eyes on this.
Could I get a hand with a regression test run on an armhf environment
while I fix my environment ?
gcc/ChangeLog:
PR target/92999
* config/arm/arm.c (aapcs_vfp_allocate_return_reg): Adjust to handle
aggregates with elements smaller than SFmode.
gcc/testsuite/ChangeLog:
* gcc.target/arm/pr92999.c: New test.
Thanks,
Ramana
Signed-off-by: Ramana Radhakrishnan <ramana.gcc@gmail.com>
[-- Attachment #2: 0001-Patch-Arm-Fix-PR92999.patch.txt --]
[-- Type: text/plain, Size: 1790 bytes --]
---
gcc/config/arm/arm.cc | 6 ++++-
gcc/testsuite/gcc.target/arm/pr92999.c | 31 ++++++++++++++++++++++++++
2 files changed, 36 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/arm/pr92999.c
diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index 2eb4d51e4a3..03f4057f717 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -6740,7 +6740,11 @@ aapcs_vfp_allocate_return_reg (enum arm_pcs pcs_variant ATTRIBUTE_UNUSED,
count *= 2;
}
}
- shift = GET_MODE_SIZE(ag_mode) / GET_MODE_SIZE(SFmode);
+
+ /* Aggregates can contain FP16 or BF16 values which would need to
+ be passed in via FP registers. */
+ shift = (MAX(GET_MODE_SIZE(ag_mode), GET_MODE_SIZE(SFmode))
+ / GET_MODE_SIZE(SFmode));
par = gen_rtx_PARALLEL (mode, rtvec_alloc (count));
for (i = 0; i < count; i++)
{
diff --git a/gcc/testsuite/gcc.target/arm/pr92999.c b/gcc/testsuite/gcc.target/arm/pr92999.c
new file mode 100644
index 00000000000..faa21fdb7d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr92999.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-options "-mfp16-format=ieee" } */
+
+//
+// Compile with gcc -mfp16-format=ieee
+// Any optimization level is fine.
+//
+// Correct output should be
+// "y.first = 1, y.second = -99"
+//
+// Buggy output is
+// "y.first = -99, y.second = -99"
+//
+#include <stdlib.h>
+struct phalf {
+ __fp16 first;
+ __fp16 second;
+};
+
+struct phalf phalf_copy(struct phalf* src) __attribute__((noinline));
+struct phalf phalf_copy(struct phalf* src) {
+ return *src;
+}
+
+int main() {
+ struct phalf x = { 1.0, -99.0};
+ struct phalf y = phalf_copy(&x);
+ if (y.first != 1.0 && y.second != -99.0)
+ abort();
+ return 0;
+}
--
2.34.1
next reply other threads:[~2022-11-08 18:20 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-08 18:20 Ramana Radhakrishnan [this message]
2022-11-09 18:42 ` Alex Coplan
2022-11-10 17:21 ` Richard Earnshaw
2022-11-10 18:03 ` Richard Earnshaw
2022-11-10 19:46 ` Ramana Radhakrishnan
2022-11-11 21:50 ` Ramana Radhakrishnan
2022-11-17 20:15 ` Ramana Radhakrishnan
2022-11-24 12:32 ` Ramana Radhakrishnan
2022-11-24 16:12 ` Richard Earnshaw
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