Re: [PATCH][AArch64] Add separate insn sched class for vector LDP & STP

[Ramana Radhakrishnan <ramana.gcc@googlemail.com>]

On Tue, Sep 29, 2015 at 12:52 AM, Evandro Menezes <e.menezes@samsung.com> wrote:
> In some micro-architectures the insns to load or store pairs of vector
> registers are implemented rather differently from those affecting lanes in
> vector registers.  Then, it's important that such insns be described
> likewise differently in the scheduling model.
>
> This patch adds the insn types neon_ldp{,_q} and neon_stp{,_q} apart from
> the current neon_load2_2reg_q and neon_store2_2reg_q types, respectively.

In such types.md restructuring, please handle these in *all* affected
scheduler descriptions, in this case thunder and xgene are 2 scheduler
descriptions that you have missed - Given Andrew is handling Thunder,
please update the xgene backend too at the same time. I can't think of
anything else that is affected right now.

A simple way to do that is to rename the old form to something else in
an intermediate patch using git to figure out all the
micro-architectures affected that need to be handled for both arm and
aarch64 backends and then add the new forms to handle this.

If there need to be follow up patches for xgene with different
handling, I'm sure Philipp will follow up - added him to CC.

Thanks,
Ramana

>
> Thank you,
>
> --
> Evandro Menezes
>