From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 25802 invoked by alias); 14 Jan 2015 09:54:58 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 25774 invoked by uid 89); 14 Jan 2015 09:54:56 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-qc0-f170.google.com Received: from mail-qc0-f170.google.com (HELO mail-qc0-f170.google.com) (209.85.216.170) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Wed, 14 Jan 2015 09:54:54 +0000 Received: by mail-qc0-f170.google.com with SMTP id x3so6409033qcv.1 for ; Wed, 14 Jan 2015 01:54:52 -0800 (PST) MIME-Version: 1.0 X-Received: by 10.224.54.2 with SMTP id o2mr4963776qag.63.1421229292116; Wed, 14 Jan 2015 01:54:52 -0800 (PST) Received: by 10.140.93.183 with HTTP; Wed, 14 Jan 2015 01:54:52 -0800 (PST) Reply-To: ramrad01@arm.com In-Reply-To: <54B3DA2E.3000209@arm.com> References: <54B3D9CF.3070504@arm.com> <54B3DA2E.3000209@arm.com> Date: Wed, 14 Jan 2015 09:58:00 -0000 Message-ID: Subject: Re: [PATCH][ARM] Fix PR target/64460: Set 'shift' attr properly on some patterns From: Ramana Radhakrishnan To: Kyrill Tkachov Cc: GCC Patches , Ramana Radhakrishnan , Richard Earnshaw Content-Type: text/plain; charset=UTF-8 X-IsSubscribed: yes X-SW-Source: 2015-01/txt/msg00993.txt.bz2 On Mon, Jan 12, 2015 at 2:29 PM, Kyrill Tkachov wrote: > Now with patch attached > > Kyrill > > > On 12/01/15 14:27, Kyrill Tkachov wrote: >> >> Hi all, >> >> In this PR we ICE when compiling with -mtune=xscale. The ICE is a >> segfault in xscale_sched_adjust_cost. >> The root cause is that xscale_sched_adjust_cost uses the value of the >> 'shift' insn attribute to index >> the recog operands. In GCC 5 the form and number of operands in those >> patterns were updated but the >> shift value was not: >> >> Author: rearnsha >> Date: Thu May 29 09:39:07 2014 +0000 >> >> * arm/iterators.md (shiftable_ops): New code iterator. >> (t2_binop0, arith_shift_insn): New code attributes. >> * arm/predicates.md (shift_nomul_operator): New predicate. >> * arm/arm.md (insn_enabled): Delete. >> (enabled): Remove insn_enabled test. >> (*arith_shiftsi): Delete. Replace with ... >> (*_multsi): ... new pattern. >> (*_shiftsi): ... new pattern. >> * config/arm/arm.c (arm_print_operand): Handle operand format >> 'b'. >> >> This led to an out-of-bounds array access. Only xscale_sched_adjust_cost >> uses the shift >> attribute, so the segfault only happens for xscale tuning. In the future >> we might want >> to use a more general pattern-matching approach to find the shifted >> operand in an rtx... >> >> In any case, this patch fixes the value of 'shift' for the offending >> pattern and also >> updates 'shift' for the *_shiftsi pattern to point to >> the correct >> operand that is being shifted. >> >> Tested arm-none-eabi and bootstrapped with -mtune=xscale in BOOT_CFLAGS. >> >> Ok for trunk? >> >> Thanks, >> Kyrill >> >> 2014-01-12 Kyrylo Tkachov >> >> PR target/64460 >> * config/arm/arm.md (*_multsi): Set 'shift' attr >> to 2. >> (*_shiftsi): Set 'shift' attr to 3. >> >> 2014-01-12 Kyrylo Tkachov >> >> PR target/64460 >> * gcc.target/arm/pr64460_1.c: New test. >> >> > OK. Thanks, Ramana