From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by sourceware.org (Postfix) with ESMTPS id EB24D3858C27 for ; Wed, 27 Sep 2023 01:27:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EB24D3858C27 Authentication-Results: sourceware.org; dmarc=pass (p=quarantine dis=none) header.from=googlemail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=googlemail.com Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-405497850dbso81432735e9.0 for ; Tue, 26 Sep 2023 18:27:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20230601; t=1695778069; x=1696382869; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=iU7UuwYBxf7CLJGe8AI96VQ/foWnI6daKAfvXS0zFQ0=; b=FKG7B8BrugWamfntZZFq7mDaqR2N9iukprSGwJ5vURt5tGOREfLfvX9TxsC0FymJsh /GClkV5hGov0Cc+IT9SpXsXFf0LJ3nfcBY0UI4Ujpu46IvgX8WCRaTggPhp6JV/T/e9A WJI0AMSVrrgBc2XbmMSvXGlyrcO6VKQp4ZY2y0u0W0z+XYU26GVNN5SYYQ4j0KVi6Y/6 kX4mViF/Stum3I76djXXl1tlb5wvAyz3C7My3tIqvRQZ3X7UXLZPq5bZaTbHubrPvG8A unwNsIV0Q2YF3dKN+ZipoT6sSqieldb1uT2gJTkqm1suIqPmTJSDqRpbu6GaYcP1VTDp TnCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695778069; x=1696382869; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iU7UuwYBxf7CLJGe8AI96VQ/foWnI6daKAfvXS0zFQ0=; b=CI/skc31P/0SQO54aQ8QMvqdlN8GeH0GJkelwZvc8DDE1WHnKldAzcbSv+Ghnkl11t 7jMD0SPxJlqmoUDe0pa+LCrsjOqy7zWrDwhdXeZdjkZiZVIxK9Qwgdj/wm3pNKnlKmAw n2qyGINIpvmLoCoQk53LdkYL3V+nDkSEUgXwcmPntBlkmT/c6kKiSucuyMNLwda1DUVM jlSZIOdCB6T2IN8rEFy1f6C9LWVufkIwGSVW0KpBjpxtzpSK1P4LP8HzvgyVdPmKIRfD UtN0r3v3Ik4sb8dfSnwvLOq1anI4eXsfCEUAokLZM03nfUK3yhmh2brneD765veb6FqJ 7ekw== X-Gm-Message-State: AOJu0Yw9FjdxsXTM0x8MBINDwZltXheZ9trvU71FXZeS2n1hZMaSK8aN ABsJTSwCRIGHdCFBf68xwpMDlEWx5tTcWk4xz5Q= X-Google-Smtp-Source: AGHT+IH/Xtfk382tvVlQ5qIn29ytRKZLGx1l4jfBnz8zTV6lmERzvn0vvwfFoH6Oy0nTTs6F1aWQcR5iEQ/CVsNPFX8= X-Received: by 2002:adf:ea4a:0:b0:319:8a66:f695 with SMTP id j10-20020adfea4a000000b003198a66f695mr271596wrn.55.1695778069408; Tue, 26 Sep 2023 18:27:49 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Ramana Radhakrishnan Date: Wed, 27 Sep 2023 02:27:38 +0100 Message-ID: Subject: Re: [PATCH]AArch64 Rewrite simd move immediate patterns to new syntax To: Tamar Christina Cc: gcc-patches@gcc.gnu.org, nd@arm.com, Richard.Earnshaw@arm.com, Marcus.Shawcroft@arm.com, Kyrylo.Tkachov@arm.com, richard.sandiford@arm.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Wed, Sep 27, 2023 at 1:53=E2=80=AFAM Tamar Christina wrote: > > Hi All, > > This rewrites the simd MOV patterns to use the new compact syntax. > No change in semantics is expected. This will be needed in follow on pat= ches. > > This also merges the splits into the define_insn which will also be neede= d soon. > > Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. > > Ok for master? > > Thanks, > Tamar > > gcc/ChangeLog: > > PR tree-optimization/109154 > * config/aarch64/aarch64-simd.md (*aarch64_simd_mov): > Rewrite to new syntax. > (*aarch64_simd_mov splits. > > --- inline copy of patch -- > diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarc= h64-simd.md > index e955691f1be8830efacc237465119764ce2a4942..7b4d5a37a9795fefda785aaac= c246918826ed0a2 100644 > --- a/gcc/config/aarch64/aarch64-simd.md > +++ b/gcc/config/aarch64/aarch64-simd.md > @@ -143,54 +143,57 @@ (define_insn "aarch64_dup_lane_" > ) > > (define_insn "*aarch64_simd_mov" > - [(set (match_operand:VDMOV 0 "nonimmediate_operand" > - "=3Dw, r, m, m, m, w, ?r, ?w, ?r, w, w") > - (match_operand:VDMOV 1 "general_operand" > - "m, m, Dz, w, r, w, w, r, r, Dn, Dz"))] > + [(set (match_operand:VDMOV 0 "nonimmediate_operand") > + (match_operand:VDMOV 1 "general_operand"))] > "TARGET_FLOAT > && (register_operand (operands[0], mode) > || aarch64_simd_reg_or_zero (operands[1], mode))" > - "@ > - ldr\t%d0, %1 > - ldr\t%x0, %1 > - str\txzr, %0 > - str\t%d1, %0 > - str\t%x1, %0 > - * return TARGET_SIMD ? \"mov\t%0., %1.\" : \"fmov\t%d= 0, %d1\"; > - * return TARGET_SIMD ? \"umov\t%0, %1.d[0]\" : \"fmov\t%x0, %d1\"; > - fmov\t%d0, %1 > - mov\t%0, %1 > - * return aarch64_output_simd_mov_immediate (operands[1], 64); > - fmov\t%d0, xzr" > - [(set_attr "type" "neon_load1_1reg, load_8, store_8, neon_store1_1r= eg,\ > - store_8, neon_logic, neon_to_gp, f_mcr,\ > - mov_reg, neon_move, f_mcr") > - (set_attr "arch" "*,*,*,*,*,*,*,*,*,simd,*")] > -) > - > -(define_insn "*aarch64_simd_mov" > - [(set (match_operand:VQMOV 0 "nonimmediate_operand" > - "=3Dw, Umn, m, w, ?r, ?w, ?r, w, w") > - (match_operand:VQMOV 1 "general_operand" > - "m, Dz, w, w, w, r, r, Dn, Dz"))] > + {@ [cons: =3D0, 1; attrs: type, arch] > + [w , m ; neon_load1_1reg , * ] ldr\t%d0, %1 > + [r , m ; load_8 , * ] ldr\t%x0, %1 > + [m , Dz; store_8 , * ] str\txzr, %0 > + [m , w ; neon_store1_1reg, * ] str\t%d1, %0 > + [m , r ; store_8 , * ] str\t%x1, %0 This hunk starting here. > + [w , w ; neon_logic , simd] mov\t%0., %1. > + [w , w ; neon_logic , * ] fmov\t%d0, %d1 Can you explain how this hunk is equivalent to return TARGET_SIMD ? \"mov\t%0., %1.\" : \"fmov\t%d0, %d1\"= ; ? > + [?r, w ; neon_to_gp , simd] umov\t%0, %1.d[0] > + [?r, w ; neon_to_gp , * ] fmov\t%x0, %d1 > + [?w, r ; f_mcr , * ] fmov\t%d0, %1 > + [?r, r ; mov_reg , * ] mov\t%0, %1 > + [w , Dn; neon_move , simd] << aarch64_output_simd_mov_imme= diate (operands[1], 64); > + [w , Dz; f_mcr , * ] fmov\t%d0, xzr > + } > +) > + > +(define_insn_and_split "*aarch64_simd_mov" > + [(set (match_operand:VQMOV 0 "nonimmediate_operand") > + (match_operand:VQMOV 1 "general_operand"))] > "TARGET_FLOAT > && (register_operand (operands[0], mode) > || aarch64_simd_reg_or_zero (operands[1], mode))" > - "@ > - ldr\t%q0, %1 > - stp\txzr, xzr, %0 > - str\t%q1, %0 > - mov\t%0., %1. > - # > - # > - # > - * return aarch64_output_simd_mov_immediate (operands[1], 128); > - fmov\t%d0, xzr" > - [(set_attr "type" "neon_load1_1reg, store_16, neon_store1_1reg,\ > - neon_logic, multiple, multiple,\ > - multiple, neon_move, fmov") > - (set_attr "length" "4,4,4,4,8,8,8,4,4") > - (set_attr "arch" "*,*,*,simd,*,*,*,simd,*")] > + {@ [cons: =3D0, 1; attrs: type, arch, length] > + [w , m ; neon_load1_1reg , * , 4] ldr\t%q0, %1 > + [Umn, Dz; store_16 , * , 4] stp\txzr, xzr, %0 > + [m , w ; neon_store1_1reg, * , 4] str\t%q1, %0 > + [w , w ; neon_logic , simd, 4] mov\t%0., %1. > + [?r , w ; multiple , * , 8] # > + [?w , r ; multiple , * , 8] # > + [?r , r ; multiple , * , 8] # > + [w , Dn; neon_move , simd, 4] << aarch64_output_simd_mov_= immediate (operands[1], 128); > + [w , Dz; fmov , * , 4] fmov\t%d0, xzr > + } > + "&& reload_completed > + && !(FP_REGNUM_P (REGNO (operands[0])) > + && FP_REGNUM_P (REGNO (operands[1])))" > + [(const_int 0)] > + { > + if (GP_REGNUM_P (REGNO (operands[0])) > + && GP_REGNUM_P (REGNO (operands[1]))) > + aarch64_simd_emit_reg_reg_move (operands, DImode, 2); > + else > + aarch64_split_simd_move (operands[0], operands[1]); > + DONE; > + } > ) > Reads correctly at first glance. Perhaps a sanity check with the aarch64 simd intrinsics suite, vect.exp or tsvc under a suitable multilib to give some confidence as to no code changes. ? Reviewed-by: Ramana Radhakrishnan regards Ramana Ramana > ;; When storing lane zero we can use the normal STR and its more permiss= ive > @@ -276,33 +279,6 @@ (define_insn "vec_store_pair" > [(set_attr "type" "neon_stp_q")] > ) > > - > -(define_split > - [(set (match_operand:VQMOV 0 "register_operand" "") > - (match_operand:VQMOV 1 "register_operand" ""))] > - "TARGET_FLOAT > - && reload_completed > - && GP_REGNUM_P (REGNO (operands[0])) > - && GP_REGNUM_P (REGNO (operands[1]))" > - [(const_int 0)] > -{ > - aarch64_simd_emit_reg_reg_move (operands, DImode, 2); > - DONE; > -}) > - > -(define_split > - [(set (match_operand:VQMOV 0 "register_operand" "") > - (match_operand:VQMOV 1 "register_operand" ""))] > - "TARGET_FLOAT > - && reload_completed > - && ((FP_REGNUM_P (REGNO (operands[0])) && GP_REGNUM_P (REGNO (operand= s[1]))) > - || (GP_REGNUM_P (REGNO (operands[0])) && FP_REGNUM_P (REGNO (oper= ands[1]))))" > - [(const_int 0)] > -{ > - aarch64_split_simd_move (operands[0], operands[1]); > - DONE; > -}) > - > (define_expand "@aarch64_split_simd_mov" > [(set (match_operand:VQMOV 0) > (match_operand:VQMOV 1))] > > > > > --