From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by sourceware.org (Postfix) with ESMTPS id 54F473858D33 for ; Sun, 20 Nov 2022 22:48:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 54F473858D33 Authentication-Results: sourceware.org; dmarc=pass (p=quarantine dis=none) header.from=googlemail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=googlemail.com Received: by mail-wr1-x42d.google.com with SMTP id g12so17377418wrs.10 for ; Sun, 20 Nov 2022 14:48:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=gB486zLBAQElkn54V6bTkpOFeU+0A5yij/sSgaVeSs0=; b=LsMR5nhmS2yqnNX2TTPwkxnn8hDXd9B4QJFTaeOj5Ei4NFoq//RatguVb2y0JNRtgS K8JdIRxhq8QZtt1xtWbroViwWUZc0TbjfdzJA1bL5e1lW1QDeaQJKVfzvDO7yi2uqvhr QUhbtmS3d60/hrZZzpUPkCv5V+8XzAoMxmxWn2PIT1Ljupn0AiJpJ5UgCAbx2lcwRXjQ tfAFW8gAIZfr6FHMTBTSjh4k9T/AHzNlLtMhpTDSyZ5EsHFrRG+lzE+mzYGeVa5qCpMx jiHYWl0PKfl2e2uwiOeSmnlZ7fjDnv4re7fC+mgUOV5p1StDwfFsqlrQ4PQAwdzAFec6 IwRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=gB486zLBAQElkn54V6bTkpOFeU+0A5yij/sSgaVeSs0=; b=0whW+7uXjRXnXYfRLpVCwJf8JPbgbZW3PlzY63zAkUoIDP+Y/jPvk8BIub1uMMCGgy cOK3JPyV1FsBne348I5Gn6ud8wNWvp5BNcEHwOerRrMY+FpeJ02z4f/dMP/J5iWxuuxJ LoxbfStKtUdUGwR2/0hwFOP/9d4Oqu3g/DFKZ5xmLCYyZunSWPtL4zbFah25b2dxtP4d lwWI6AWSPboCxafBPHJz7XezGCwjIoasPQGzxJLLo1ohX1G8+alvkg7dy+3+IZpPJJNK wVEQBWLTwWYIMsVt0Zm1IxojwpgdA8jt9Mmby1A9wkFB2/g1qN0DU17Xe5OIBii4oVuO 06XQ== X-Gm-Message-State: ANoB5plbCWdLXxbmAoBmkHYnby0WWlZs0lxcsuvTIWu6oARcuaHpRe/R GxSJ61aqMCeOK8jyCGC/gRqg68nfgfmmXO2w9Xw= X-Google-Smtp-Source: AA0mqf716vAO7AmB/eGCNyeFmDrH8xq3f/IsDk5qt67tgvx/tfwVmpq7raXl4SSY8GM72mACqhazxi3yNUjfo6b9dXE= X-Received: by 2002:a5d:6342:0:b0:236:b222:13fb with SMTP id b2-20020a5d6342000000b00236b22213fbmr1944205wrw.307.1668984513931; Sun, 20 Nov 2022 14:48:33 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Ramana Radhakrishnan Date: Sun, 20 Nov 2022 22:48:23 +0000 Message-ID: Subject: Re: [PATCH][GCC] arm: Add support for new frame unwinding instruction "0xb5". To: Srinath Parvathaneni Cc: "gcc-patches@gcc.gnu.org" , Richard Earnshaw , Kyrylo Tkachov Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Fri, Nov 18, 2022 at 9:33 AM Srinath Parvathaneni wrote: > > Hi, > > > -----Original Message----- > > From: Ramana Radhakrishnan > > Sent: Thursday, November 17, 2022 8:27 PM > > To: Srinath Parvathaneni > > Cc: gcc-patches@gcc.gnu.org; Richard Earnshaw > > ; Kyrylo Tkachov > > Subject: Re: [PATCH][GCC] arm: Add support for new frame unwinding > > instruction "0xb5". > > > > On Thu, Nov 10, 2022 at 10:38 AM Srinath Parvathaneni via Gcc-patches > patches@gcc.gnu.org> wrote: > > > > > > Hi, > > > > > > This patch adds support for Arm frame unwinding instruction "0xb5" > > > [1]. When an exception is taken and "0xb5" instruction is encounter > > > during runtime stack-unwinding, we use effective vsp as modifier in pointer > > authentication. > > > On completion of stack unwinding if "0xb5" instruction is not > > > encountered then CFA will be used as modifier in pointer authentication. > > > > > > [1] > > > https://github.com/ARM-software/abi- > > aa/releases/download/2022Q3/ehabi3 > > > 2.pdf > > > > > > Regression tested on arm-none-eabi target and found no regressions. > > > > > > Ok for master? > > > > > > > No, not yet. > > > > Presumably the logic to produce 0xb5 is in the source base and this was > > tested with suitable options that produce said opcode ? I see no logic in place > > to produce the said opcode in the backend in a quick read as the pacbti > > patches still seem to be in review. ? > > > > So what was the test suite run actually testing ? > > Sorry for the late response, the patch supporting the said opcode (directive ".pacspval)" is here: > https://gcc.gnu.org/pipermail/gcc-patches/2022-November/605524.html (still under upstream review) > > and the patch to encode ".pacspval" with the mentioned opcode "0xb5" in binutils is here: > https://sourceware.org/pipermail/binutils/2022-November/124328.html (approved and committed to binutils). Thanks for the answer but perhaps I should make my question more explicit - are you saying that this patch was tested in combination with those and other dependent patches on a suitable simulator with suitable multilibs and C++ to test for this presumably for frame unwinding ? For the future , it would certainly be worth being explicit about this in your patch submission :) regards Ramana > > Regards, > Srinath. > > > regards > > Ramana > > > > > > > Regards, > > > Srinath. > > > > > > gcc/ChangeLog: > > > > > > 2022-11-09 Srinath Parvathaneni > > > > > > * libgcc/config/arm/pr-support.c (__gnu_unwind_execute): Decode > > opcode > > > "0xb5". > > > > > > > > > ############### Attachment also inlined for ease of reply > > ############### > > > > > > > > > diff --git a/libgcc/config/arm/pr-support.c > > > b/libgcc/config/arm/pr-support.c index > > > > > e48854587c667a959aa66ccc4982231f63333ecc..73e4942a39b34a83c2da85de > > f6b1 > > > 3e82ec501552 100644 > > > --- a/libgcc/config/arm/pr-support.c > > > +++ b/libgcc/config/arm/pr-support.c > > > @@ -107,7 +107,9 @@ __gnu_unwind_execute (_Unwind_Context * > > context, __gnu_unwind_state * uws) > > > _uw op; > > > int set_pc; > > > int set_pac = 0; > > > + int set_pac_sp = 0; > > > _uw reg; > > > + _uw sp; > > > > > > set_pc = 0; > > > for (;;) > > > @@ -124,10 +126,11 @@ __gnu_unwind_execute (_Unwind_Context * > > context, > > > __gnu_unwind_state * uws) #if defined(TARGET_HAVE_PACBTI) > > > if (set_pac) > > > { > > > - _uw sp; > > > _uw lr; > > > _uw pac; > > > - _Unwind_VRS_Get (context, _UVRSC_CORE, R_SP, > > _UVRSD_UINT32, &sp); > > > + if (!set_pac_sp) > > > + _Unwind_VRS_Get (context, _UVRSC_CORE, R_SP, > > _UVRSD_UINT32, > > > + &sp); > > > _Unwind_VRS_Get (context, _UVRSC_CORE, R_LR, _UVRSD_UINT32, > > &lr); > > > _Unwind_VRS_Get (context, _UVRSC_PAC, R_IP, > > > _UVRSD_UINT32, &pac); @@ -259,7 +262,19 > > > @@ __gnu_unwind_execute (_Unwind_Context * context, > > __gnu_unwind_state * uws) > > > continue; > > > } > > > > > > - if ((op & 0xfc) == 0xb4) /* Obsolete FPA. */ > > > + /* Use current VSP as modifier in PAC validation. */ > > > + if (op == 0xb5) > > > + { > > > + if (set_pac) > > > + _Unwind_VRS_Get (context, _UVRSC_CORE, R_SP, > > _UVRSD_UINT32, > > > + &sp); > > > + else > > > + return _URC_FAILURE; > > > + set_pac_sp = 1; > > > + continue; > > > + } > > > + > > > + if ((op & 0xfd) == 0xb6) /* Obsolete FPA. */ > > > return _URC_FAILURE; > > > > > > /* op & 0xf8 == 0xb8. */ > > > > > > > > >