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From: Ramana Radhakrishnan <ramana.gcc@googlemail.com>
To: Wilco Dijkstra <Wilco.Dijkstra@arm.com>
Cc: GCC Patches <gcc-patches@gcc.gnu.org>,
	Richard Sandiford <Richard.Sandiford@arm.com>,
	 Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>,
	Richard Earnshaw <Richard.Earnshaw@arm.com>
Subject: Re: [PATCH] AArch64: Fix __sync_val_compare_and_swap [PR111404]
Date: Tue, 26 Sep 2023 23:23:57 +0100	[thread overview]
Message-ID: <CAJA7tRb3VARCzPkmXTw+eq2T+v99xEaT8XpH1zvm5G=4ZRq0gA@mail.gmail.com> (raw)
In-Reply-To: <PAWPR08MB89822ECE134A9BB2E02297E883FCA@PAWPR08MB8982.eurprd08.prod.outlook.com>

Hi Wilco,

Thanks for your email.

On Tue, Sep 26, 2023 at 12:07 AM Wilco Dijkstra <Wilco.Dijkstra@arm.com> wrote:
>
> Hi Ramana,
>
> >> __sync_val_compare_and_swap may be used on 128-bit types and either calls the
> >> outline atomic code or uses an inline loop.  On AArch64 LDXP is only atomic if
> >> the value is stored successfully using STXP, but the current implementations
> >> do not perform the store if the comparison fails.  In this case the value returned
> >> is not read atomically.
> >
> > IIRC, the previous discussions in this space revolved around the
> > difficulty with the store writing to readonly memory which is why I
> > think we went with LDXP in this form.
>
> That's not related to this patch - this fixes a serious atomicity bug that may
> affect the Linux kernel since it uses the older sync primitives. Given that LDXP
> is not atomic on its own, you have to execute the STXP even in the failure case.
> Note that you can't rely on compare&swap not to write memory: load-exclusive
> loops may either always write or avoid writes in the failure case if the load is
> atomic. CAS instructions always write.
>

I am aware of the capabilities of the architecture.

> > Has something changed from then ?
>
> Yes, we now know that using locking atomics was a bad decision. Developers
> actually require efficient and lock-free atomics. Since we didn't support them,
> many applications were forced to add their own atomic implementations using
> hacky inline assembler. It also resulted in a nasty ABI incompatibility between
> GCC and LLVM. Yes - atomics are part of the ABI!

I agree that atomics are part of the ABI.

>
> All that is much worse than worrying about a theoretical corner case that
> can't happen in real applications - atomics only work on writeable memory
> since their purpose is to synchronize reads with writes.


I remember this to be the previous discussions and common understanding.

https://gcc.gnu.org/legacy-ml/gcc/2016-06/msg00017.html

and here

https://gcc.gnu.org/legacy-ml/gcc-patches/2017-02/msg00168.html

Can you point any discussion recently that shows this has changed and
point me at that discussion if any anywhere ? I can't find it in my
searches . Perhaps you've had the discussion some place to show it has
changed.


regards
Ramana



>
> Cheers,
> Wilco

  reply	other threads:[~2023-09-26 22:24 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-13 14:54 Wilco Dijkstra
2023-09-25 20:54 ` Ramana Radhakrishnan
2023-09-25 23:07   ` Wilco Dijkstra
2023-09-26 22:23     ` Ramana Radhakrishnan [this message]
2023-10-16 14:59       ` Wilco Dijkstra
2023-10-16 13:04 ` Wilco Dijkstra
2023-11-06 12:12   ` Wilco Dijkstra
2023-11-30 10:59 ` Richard Sandiford
2023-11-30 18:02   ` Wilco Dijkstra

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