From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 8986 invoked by alias); 5 Jun 2014 06:27:14 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 8972 invoked by uid 89); 5 Jun 2014 06:27:12 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.4 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-qa0-f42.google.com Received: from mail-qa0-f42.google.com (HELO mail-qa0-f42.google.com) (209.85.216.42) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Thu, 05 Jun 2014 06:27:11 +0000 Received: by mail-qa0-f42.google.com with SMTP id j5so759908qaq.29 for ; Wed, 04 Jun 2014 23:27:09 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.224.50.136 with SMTP id z8mr14008971qaf.66.1401949629090; Wed, 04 Jun 2014 23:27:09 -0700 (PDT) Received: by 10.224.220.80 with HTTP; Wed, 4 Jun 2014 23:27:09 -0700 (PDT) Reply-To: ramrad01@arm.com In-Reply-To: References: Date: Thu, 05 Jun 2014 06:27:00 -0000 Message-ID: Subject: Re: [PATCH] [ARM] Post-indexed addressing for NEON memory access From: Ramana Radhakrishnan To: Charles Baylis Cc: GCC Patches , Richard Earnshaw , Ramana Radhakrishnan Content-Type: text/plain; charset=UTF-8 X-IsSubscribed: yes X-SW-Source: 2014-06/txt/msg00418.txt.bz2 On Mon, Jun 2, 2014 at 5:47 PM, Charles Baylis wrote: > This patch adds support for post-indexed addressing for NEON structure > memory accesses. > > For example VLD1.8 {d0}, [r0], r1 > > > Bootstrapped and checked on arm-unknown-gnueabihf using Qemu. > > Ok for trunk? This looks like a reasonable start but this work doesn't look complete to me yet. Can you also look at the impact on performance of a range of benchmarks especially a popular embedded one to see how this behaves unless you have already done so ? POST_INC, POST_MODIFY usually have a funny way of biting you with either ivopts or the way in which address costs work. I think there maybe further tweaks needed but for a first step I'd like to know what the performance impact is. I would also suggest running this through clyon's neon intrinsics testsuite to see if that catches any issues especially with the large vector modes. regards Ramana > > > gcc/Changelog: > > 2014-06-02 Charles Baylis > > * config/arm/arm.c (neon_vector_mem_operand): Allow register > POST_MODIFY for neon loads and stores. > (arm_print_operand): Output post-index register for neon loads and > stores.