From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yb1-xb2e.google.com (mail-yb1-xb2e.google.com [IPv6:2607:f8b0:4864:20::b2e]) by sourceware.org (Postfix) with ESMTPS id 9F64A395A413 for ; Wed, 16 Nov 2022 13:28:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 9F64A395A413 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-yb1-xb2e.google.com with SMTP id v123so124738ybv.5 for ; Wed, 16 Nov 2022 05:28:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=HjMge5E6DnRP8JPity4tksVA0V/tfr5WnJilE1s9Flk=; b=m22a9W8BOmGhKnwCK7zZpR+eF4LhAp8Q1cYz04rJL8uvD4Eo2bNgYcZiuu5x5ryd7L 0GTU9Bi7gmNw/goPrIEnQySJf+M2RnaqPytn1/TZPdknDTFpAxT6DrIgtLo5YT/Ajg/U dn/wcUN5rQXBfUjq24LrX7hgBwnYiA5BLFZnT02KXfUuH/iCo3l6MyEGvxFwKCBIAveb Tl3SU6xco8o8+IpTgYMqkgQvI2ek+JybOhCh1ois7DQ4F0eZ3Z9oTP8m1j93cSFgiR8c lUow9l+DBybp/Tdbg9V01rHSv01b0mPi4hx6PYf/XNeXMTWjdQKm31qHn7SJZMCjYUYr 2aYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=HjMge5E6DnRP8JPity4tksVA0V/tfr5WnJilE1s9Flk=; b=CObx+2l+ING0n5wQn1Zm/tjc1LklhcN62IAeMGvjhLIzIGypJqJz90c2KzAZBO5O9U 3oUc1wL/HYyMQ2qjXNNCBrl7bIWh+wyi/D7MH/3oRB0Myh0/AqXIjmMdP3rb4iArLCsu kLO8GJtCZZERjwPcAKEY6XKdu/geN85YwHvHOdLtNLyUZTE6ANbI9Ge7fAMWEiF1Noo4 QwKfjpLQhwtZV5s+hkaJSGRD2HX7fblyg3MZ9gzLxW8DkksDIIoLafgqZ+YjnpzJ5BWz K5hlvgWHpMlaWQ+Jx3/Dn9+tzI+vDe+xeKAV7hSPncOapIHbFY5sk6rVr5pmCQWd0cNc 7Fnw== X-Gm-Message-State: ANoB5plXAGtgMXAwL6vWPmeEB9M2K9E9pLBpwfJOFn/I2O+x0QhrQJKT EOJ7SXEft8dvo6SCB/WDujEMNEPs8y6xJHdzpvE= X-Google-Smtp-Source: AA0mqf6kZLbucaoi10LIWvrBOI6HD0GigPEWRco3eRLYMz1CpuyFlww62PtoOMaOQ++r5OQxH1VRZTM357NXwQ6Lk1k= X-Received: by 2002:a25:81c7:0:b0:6be:99e7:c5f0 with SMTP id n7-20020a2581c7000000b006be99e7c5f0mr21102562ybm.248.1668605294899; Wed, 16 Nov 2022 05:28:14 -0800 (PST) MIME-Version: 1.0 References: <20221101162637.14238-1-amonakov@ispras.ru> <20221101162637.14238-3-amonakov@ispras.ru> <50d58d4c-3f13-a4c1-ea7a-2cc40761bb1@ispras.ru> In-Reply-To: <50d58d4c-3f13-a4c1-ea7a-2cc40761bb1@ispras.ru> From: =?UTF-8?B?SmFuIEh1YmnEjWth?= Date: Wed, 16 Nov 2022 14:28:04 +0100 Message-ID: Subject: Re: [PATCH 2/2] i386: correct x87&SSE multiplication modeling in znver.md To: Alexander Monakov Cc: "Kumar, Venkataramanan" , "gcc-patches@gcc.gnu.org" , "Joshi, Tejas Sanjay" Content-Type: multipart/alternative; boundary="000000000000df762905ed9671f9" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,HTML_MESSAGE,MEDICAL_SUBJECT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --000000000000df762905ed9671f9 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, Nov 16, 2022 at 2:13 PM Alexander Monakov wrote: > > On Wed, 16 Nov 2022, Jan Hubi=C4=8Dka wrote: > > > This looks really promising. I will experiment with the patch for > separate > > znver3 model, but I think we should be able to keep > > them unified and hopefully get both less code duplicatoin and table > sizes. > > Do you mean separate znver4 (not '3') model (i.e. the recent patch by AMD= )? > Yes. I guess we want to check what variant leads to smaller automaton. I would somewhat prefer to keep the models unified since they are quite similar > > > znver1 native path is 128 and znver2/3 has 256 bit paths. > > > We need to split this into two reservations. One for znver1 and the > other > > > for znver2/3. > > > > > > > isn't it znver2 for 128 and znver3 for 256? > > No, Zen 1 splits AVX256 instructions into pairs of 128-bit uops, Zen 2 and > Zen 3 have native 256-bit units. Zen 4 again executes AVX512 instructions > on 256-bit units. > Ah, of course. I mixed things up in my memory. Sorry fro that. > > I think a split is not needed because the preceding reservation already > handles > znver2 and znver3, we just need to remove them here, like this: > > diff --git a/gcc/config/i386/znver.md b/gcc/config/i386/znver.md > index 882f250f1..16b5afa5d 100644 > --- a/gcc/config/i386/znver.md > +++ b/gcc/config/i386/znver.md > @@ -1242,7 +1242,7 @@ (define_insn_reservation "znver1_sseimul" 3 > "znver1-direct,znver1-fp0") > > (define_insn_reservation "znver1_sseimul_avx256" 4 > - (and (eq_attr "cpu" "znver1,znver2,znver3") > + (and (eq_attr "cpu" "znver1") > It should work even without removal since first reservation matches, but this is quite less confusing indeed. > (and (eq_attr "mode" "OI") > (and (eq_attr "type" "sseimul") > (eq_attr "memory" "none")))) > @@ -1260,7 +1260,7 @@ (define_insn_reservation "znver1_sseimul_load" 10 > "znver1-direct,znver1-load,znver1-fp0") > > (define_insn_reservation "znver1_sseimul_avx256_load" 11 > - (and (eq_attr "cpu" "znver1,znver2,znver3") > + (and (eq_attr "cpu" "znver1") > (and (eq_attr "mode" "OI") > (and (eq_attr "type" "sseimul") > (eq_attr "memory" "load")))) > > > The patch looks good. > > > > > Patch is OK then :) > > For *both* patches in the series? > Yes, thanks a lot for looking into this! Honza > > Alexander --000000000000df762905ed9671f9--