[RFC][LIBGCC][0 of 2] 64 bit divide implementation for processor without hw divide instruction

[RFC][LIBGCC][0 of 2] 64 bit divide implementation for processor without hw divide instruction

[Kugan]

Hi All,

This RFC patch series implements a simple align divisor shift dividend
method for 64bit divide  and enables for ARMv7-a.

This algorithm runs (K+1) times where K is the number of bits divisor is
shifted to align. I have done repeated divides and found that this
implementation performs better for processor without hw divide instruction.

On a chromebook, when K is large (close to 64) this performs on an
average ~10% faster. When K is small (8 to 24), it performs about ~100%
faster on an average.

Regression tested on arm-none-linux-gnueabi with no issues.

OK?

Thanks,
Kugan

Re: [RFC][LIBGCC][1 of 2] 64 bit divide implementation for processor without hw divide instruction

[Kugan]

[-- Attachment #1: Type: text/plain, Size: 385 bytes --]

Hi All,

This RFC patch series implements a simple align divisor shift dividend
method.

Regression tested on arm-none-linux-gnueabi with no issues.

OK?

Thanks,
Kugan

+2013-11-22  Kugan Vivekanandarajah  <kuganv@linaro.org>
+
+	* libgcc/libgcc2.c (__udivmoddi4): Define new implementation when
+	HAVE_NO_HW_DIVIDE is defined, for processors without any divide
+     instructions.
+

[-- Attachment #2: p1.txt --]
[-- Type: text/plain, Size: 2283 bytes --]

diff --git a/libgcc/libgcc2.c b/libgcc/libgcc2.c
index bec411b..a1d3fbc 100644
--- a/libgcc/libgcc2.c
+++ b/libgcc/libgcc2.c
@@ -934,6 +934,74 @@ __parityDI2 (UDWtype x)
 #endif
 
 #ifdef L_udivmoddi4
+#ifdef HAVE_NO_HW_DIVIDE
+
+#if (defined (L_udivdi3) || defined (L_divdi3) || \
+     defined (L_umoddi3) || defined (L_moddi3))
+static inline __attribute__ ((__always_inline__))
+#endif
+UDWtype
+__udivmoddi4 (UDWtype n, UDWtype d, UDWtype *rp)
+{
+  UDWtype q = 0, r = n, y = d;
+  UWtype lz1, lz2, i, k;
+
+  /* Implements align divisor shift dividend method. This algorithm
+     aligns the divisor under the dividend and then perform number of
+     test-subtract iterations which shift the dividend left. Number of
+     iterations is k + 1 where k is the number of bit positions the
+     divisor must be shifted left  to align it under the dividend.
+     quotient bits can be saved in the rightmost positions of the dividend
+     as it shifts left on each test-subtract iteration. */
+
+  if (y <= r)
+    {
+      lz1 = __builtin_clzll (d);
+      lz2 = __builtin_clzll (n);
+
+      k = lz1 - lz2;
+      y = (y << k);
+
+      /* Dividend can exceed 2 ^ (width − 1) − 1 but still be less than the
+	 aligned divisor. Normal iteration can drops the high order bit
+	 of the dividend. Therefore, first test-subtract iteration is a
+	 special case, saving its quotient bit in a separate location and
+	 not shifting the dividend. */
+      if (r >= y)
+	{
+	  r = r - y;
+	  q =  (1ULL << k);
+	}
+
+      if (k > 0)
+	{
+	  y = y >> 1;
+
+	  /* k additional iterations where k regular test subtract shift
+	    dividend iterations are done.  */
+	  i = k;
+	  do
+	    {
+	      if (r >= y)
+		r = ((r - y) << 1) + 1;
+	      else
+		r =  (r << 1);
+	      i = i - 1;
+	    } while (i != 0);
+
+	  /* First quotient bit is combined with the quotient bits resulting
+	     from the k regular iterations.  */
+	  q = q + r;
+	  r = r >> k;
+	  q = q - (r << k);
+	}
+    }
+
+  if (rp)
+    *rp = r;
+  return q;
+}
+#else
 
 #if (defined (L_udivdi3) || defined (L_divdi3) || \
      defined (L_umoddi3) || defined (L_moddi3))
@@ -1152,6 +1220,7 @@ __udivmoddi4 (UDWtype n, UDWtype d, UDWtype *rp)
   return ww.ll;
 }
 #endif
+#endif
 
 #ifdef L_divdi3
 DWtype

Re: [RFC][LIBGCC][2 of 2] 64 bit divide implementation for processor without hw divide instruction

[Kugan]

[-- Attachment #1: Type: text/plain, Size: 294 bytes --]

Hi All,

This RFC patch enables new divide algorithm for ARMV7-A

Regression tested on arm-none-linux-gnueabi with no issues.

OK?

Thanks,
Kugan

+2013-11-22  Kugan Vivekanandarajah  <kuganv@linaro.org>
+
+	* libgcc/config/arm/pbapi-lib.h (HAVE_NO_HW_DIVIDE): Define for
+	__ARM_ARCH_7_A__.
+

[-- Attachment #2: p2.txt --]
[-- Type: text/plain, Size: 414 bytes --]

diff --git a/libgcc/config/arm/bpabi-lib.h b/libgcc/config/arm/bpabi-lib.h
index e0e46a6..85171c8 100644
--- a/libgcc/config/arm/bpabi-lib.h
+++ b/libgcc/config/arm/bpabi-lib.h
@@ -75,3 +75,7 @@
    helper functions - not everything in libgcc - in the interests of
    maintaining backward compatibility.  */
 #define LIBGCC2_FIXEDBIT_GNU_PREFIX
+
+#if defined(__ARM_ARCH_7A__)
+# define HAVE_NO_HW_DIVIDE
+#endif

Re: [RFC][LIBGCC][0 of 2] 64 bit divide implementation for processor without hw divide instruction

[Joseph S. Myers]

This appears to be adding a new libgcc target macro; please document it in 
tm.texi.in and regenerate tm.texi.

-- 
Joseph S. Myers
joseph@codesourcery.com

Re: [RFC][LIBGCC][1 of 2] 64 bit divide implementation for processor without hw divide instruction

[Ian Lance Taylor]

Kugan <kugan.vivekanandarajah@linaro.org> writes:

> This RFC patch series implements a simple align divisor shift dividend
> method.
>
> Regression tested on arm-none-linux-gnueabi with no issues.
>
> OK?
>
> Thanks,
> Kugan
>
> +2013-11-22  Kugan Vivekanandarajah  <kuganv@linaro.org>
> +
> +	* libgcc/libgcc2.c (__udivmoddi4): Define new implementation when
> +	HAVE_NO_HW_DIVIDE is defined, for processors without any divide
> +     instructions.


The code looks fine to me.

You should document HAVE_NO_HW_DIVIDE in gcc/doc/tm.texi in the Library
Calls section.  The macro should probably be something like
TARGET_HAS_NO_HW_DIVIDE.

Ian

Re: [RFC][LIBGCC][1 of 2] 64 bit divide implementation for processor without hw divide instruction

[Kugan]

[-- Attachment #1: Type: text/plain, Size: 1172 bytes --]

On 24/11/13 02:14, Ian Lance Taylor wrote:
> Kugan <kugan.vivekanandarajah@linaro.org> writes:
> 
>> This RFC patch series implements a simple align divisor shift dividend
>> method.
>>
>> Regression tested on arm-none-linux-gnueabi with no issues.
>>
>> OK?
>>
>> Thanks,
>> Kugan
>>
>> +2013-11-22  Kugan Vivekanandarajah  <kuganv@linaro.org>
>> +
>> +	* libgcc/libgcc2.c (__udivmoddi4): Define new implementation when
>> +	HAVE_NO_HW_DIVIDE is defined, for processors without any divide
>> +     instructions.
> 
> 
> The code looks fine to me.
> 
> You should document HAVE_NO_HW_DIVIDE in gcc/doc/tm.texi in the Library
> Calls section.  The macro should probably be something like
> TARGET_HAS_NO_HW_DIVIDE.
> 
Thanks for the review. Is this OK for trunk now?


+2013-11-26  Kugan Vivekanandarajah  <kuganv@linaro.org>
+
+	* libgcc/libgcc2.c (__udivmoddi4): Define new implementation when
+	TARGET_HAS_NO_HW_DIVIDE is defined, for processors without any divide
+	instructions.
+


+2013-11-26  Kugan Vivekanandarajah  <kuganv@linaro.org>
+
+	* doc/tm.texi.in (TARGET_HAS_NO_HW_DIVIDE): Define.
+	* doc/tm.texi (TARGET_HAS_NO_HW_DIVIDE): Regenerate.
+

Thanks,
Kugan

[-- Attachment #2: p1.txt --]
[-- Type: text/plain, Size: 3785 bytes --]

diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index 925d93f..c9697f1 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -5365,6 +5365,14 @@ If this macro evaluates to @code{false} the comparison functions return
 in @file{libgcc.a}, you do not need to define this macro.
 @end defmac
 
+@defmac TARGET_HAS_NO_HW_DIVIDE
+This macro should be defined if the target has no hardware divide
+instructions.  If this macro is defined, GCC will use an algorithm which
+make use of simple logical and arithmetic operations for 64-bit
+division.  If the macro is not defined, GCC will use an algorithm which
+make use of a 64-bit by 32-bit divide primitive.
+@end defmac
+
 @cindex @code{EDOM}, implicit usage
 @findex matherr
 @defmac TARGET_EDOM
diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in
index edca600..03e6662 100644
--- a/gcc/doc/tm.texi.in
+++ b/gcc/doc/tm.texi.in
@@ -4205,6 +4205,14 @@ If this macro evaluates to @code{false} the comparison functions return
 in @file{libgcc.a}, you do not need to define this macro.
 @end defmac
 
+@defmac TARGET_HAS_NO_HW_DIVIDE
+This macro should be defined if the target has no hardware divide
+instructions.  If this macro is defined, GCC will use an algorithm which
+make use of simple logical and arithmetic operations for 64-bit
+division.  If the macro is not defined, GCC will use an algorithm which
+make use of a 64-bit by 32-bit divide primitive.
+@end defmac
+
 @cindex @code{EDOM}, implicit usage
 @findex matherr
 @defmac TARGET_EDOM
diff --git a/libgcc/libgcc2.c b/libgcc/libgcc2.c
index bec411b..8c4cc6a 100644
--- a/libgcc/libgcc2.c
+++ b/libgcc/libgcc2.c
@@ -934,6 +934,74 @@ __parityDI2 (UDWtype x)
 #endif
 
 #ifdef L_udivmoddi4
+#ifdef TARGET_HAS_NO_HW_DIVIDE
+
+#if (defined (L_udivdi3) || defined (L_divdi3) || \
+     defined (L_umoddi3) || defined (L_moddi3))
+static inline __attribute__ ((__always_inline__))
+#endif
+UDWtype
+__udivmoddi4 (UDWtype n, UDWtype d, UDWtype *rp)
+{
+  UDWtype q = 0, r = n, y = d;
+  UWtype lz1, lz2, i, k;
+
+  /* Implements align divisor shift dividend method. This algorithm
+     aligns the divisor under the dividend and then perform number of
+     test-subtract iterations which shift the dividend left. Number of
+     iterations is k + 1 where k is the number of bit positions the
+     divisor must be shifted left  to align it under the dividend.
+     quotient bits can be saved in the rightmost positions of the dividend
+     as it shifts left on each test-subtract iteration. */
+
+  if (y <= r)
+    {
+      lz1 = __builtin_clzll (d);
+      lz2 = __builtin_clzll (n);
+
+      k = lz1 - lz2;
+      y = (y << k);
+
+      /* Dividend can exceed 2 ^ (width − 1) − 1 but still be less than the
+	 aligned divisor. Normal iteration can drops the high order bit
+	 of the dividend. Therefore, first test-subtract iteration is a
+	 special case, saving its quotient bit in a separate location and
+	 not shifting the dividend. */
+      if (r >= y)
+	{
+	  r = r - y;
+	  q =  (1ULL << k);
+	}
+
+      if (k > 0)
+	{
+	  y = y >> 1;
+
+	  /* k additional iterations where k regular test subtract shift
+	    dividend iterations are done.  */
+	  i = k;
+	  do
+	    {
+	      if (r >= y)
+		r = ((r - y) << 1) + 1;
+	      else
+		r =  (r << 1);
+	      i = i - 1;
+	    } while (i != 0);
+
+	  /* First quotient bit is combined with the quotient bits resulting
+	     from the k regular iterations.  */
+	  q = q + r;
+	  r = r >> k;
+	  q = q - (r << k);
+	}
+    }
+
+  if (rp)
+    *rp = r;
+  return q;
+}
+#else
 
 #if (defined (L_udivdi3) || defined (L_divdi3) || \
      defined (L_umoddi3) || defined (L_moddi3))
@@ -1152,6 +1220,7 @@ __udivmoddi4 (UDWtype n, UDWtype d, UDWtype *rp)
   return ww.ll;
 }
 #endif
+#endif
 
 #ifdef L_divdi3
 DWtype

Re: [RFC][LIBGCC][1 of 2] 64 bit divide implementation for processor without hw divide instruction

[Ian Lance Taylor]

On Mon, Nov 25, 2013 at 4:29 PM, Kugan
<kugan.vivekanandarajah@linaro.org> wrote:
>
> +2013-11-26  Kugan Vivekanandarajah  <kuganv@linaro.org>
> +
> +       * libgcc/libgcc2.c (__udivmoddi4): Define new implementation when
> +       TARGET_HAS_NO_HW_DIVIDE is defined, for processors without any divide
> +       instructions.
> +
>
>
> +2013-11-26  Kugan Vivekanandarajah  <kuganv@linaro.org>
> +
> +       * doc/tm.texi.in (TARGET_HAS_NO_HW_DIVIDE): Define.
> +       * doc/tm.texi (TARGET_HAS_NO_HW_DIVIDE): Regenerate.


This is OK.

Thanks.

Ian

Re: [RFC][LIBGCC][2 of 2] 64 bit divide implementation for processor without hw divide instruction

[Richard Earnshaw]

On 23/11/13 01:54, Kugan wrote:
> Hi All,
> 
> This RFC patch enables new divide algorithm for ARMV7-A
> 
> Regression tested on arm-none-linux-gnueabi with no issues.
> 
> OK?
> 
> Thanks,
> Kugan
> 
> +2013-11-22  Kugan Vivekanandarajah  <kuganv@linaro.org>
> +
> +	* libgcc/config/arm/pbapi-lib.h (HAVE_NO_HW_DIVIDE): Define for

It's bpabi-lib.h

> +	__ARM_ARCH_7_A__.
> +
> 
> 

No, this will:
1) Do the wrong thing for Cortex-a7, A12 and A15 (which all have HW
divide, and currently define __ARM_ARCH_7_A__).
2) Do the wrong thing for v7-M and v7-R devices, which have Thumb HW
division instructions.
3) Do the wrong thing for all pre-v7 devices, which don't have HW division.

I think the correct solution is to test !defined(__ARM_ARCH_EXT_IDIV__)

R.

> p2.txt
> 
> 
> diff --git a/libgcc/config/arm/bpabi-lib.h b/libgcc/config/arm/bpabi-lib.h
> index e0e46a6..85171c8 100644
> --- a/libgcc/config/arm/bpabi-lib.h
> +++ b/libgcc/config/arm/bpabi-lib.h
> @@ -75,3 +75,7 @@
>     helper functions - not everything in libgcc - in the interests of
>     maintaining backward compatibility.  */
>  #define LIBGCC2_FIXEDBIT_GNU_PREFIX
> +
> +#if defined(__ARM_ARCH_7A__)
> +# define HAVE_NO_HW_DIVIDE
> +#endif
> 

Re: [RFC][LIBGCC][2 of 2] 64 bit divide implementation for processor without hw divide instruction

[Kugan]

[-- Attachment #1: Type: text/plain, Size: 1045 bytes --]

On 27/11/13 02:07, Richard Earnshaw wrote:
> On 23/11/13 01:54, Kugan wrote:

[snip]

>> +2013-11-22  Kugan Vivekanandarajah  <kuganv@linaro.org>
>> +
>> +	* libgcc/config/arm/pbapi-lib.h (HAVE_NO_HW_DIVIDE): Define for
> 
> It's bpabi-lib.h

Thanks for the review.

>> +	__ARM_ARCH_7_A__.
>> +
>>
>>
> 
> No, this will:
> 1) Do the wrong thing for Cortex-a7, A12 and A15 (which all have HW
> divide, and currently define __ARM_ARCH_7_A__).
> 2) Do the wrong thing for v7-M and v7-R devices, which have Thumb HW
> division instructions.
> 3) Do the wrong thing for all pre-v7 devices, which don't have HW division.
> 
> I think the correct solution is to test !defined(__ARM_ARCH_EXT_IDIV__)

I understand it now and updated the code as attached.

+2013-11-27  Kugan Vivekanandarajah  <kuganv@linaro.org>
+
+	* config/arm/bpapi-lib.h (TARGET_HAS_NO_HW_DIVIDE): Define for
+	architectures that does not have hardware divide instruction.
+	i.e. architectures that does not define __ARM_ARCH_EXT_IDIV__.
+


Is this OK for trunk now?
Thanks,
Kugan

[-- Attachment #2: p2.txt --]
[-- Type: text/plain, Size: 429 bytes --]

diff --git a/libgcc/config/arm/bpabi-lib.h b/libgcc/config/arm/bpabi-lib.h
index e0e46a6..7c6b489 100644
--- a/libgcc/config/arm/bpabi-lib.h
+++ b/libgcc/config/arm/bpabi-lib.h
@@ -75,3 +75,7 @@
    helper functions - not everything in libgcc - in the interests of
    maintaining backward compatibility.  */
 #define LIBGCC2_FIXEDBIT_GNU_PREFIX
+
+#if (!defined(__ARM_ARCH_EXT_IDIV__))
+# define TARGET_HAS_NO_HW_DIVIDE
+#endif

Re: [RFC][LIBGCC][1 of 2] 64 bit divide implementation for processor without hw divide instruction

[Jeff Law]

On 11/25/13 17:29, Kugan wrote:
> On 24/11/13 02:14, Ian Lance Taylor wrote:
>> Kugan <kugan.vivekanandarajah@linaro.org> writes:
>>
>>> This RFC patch series implements a simple align divisor shift dividend
>>> method.
>>>
>>> Regression tested on arm-none-linux-gnueabi with no issues.
>>>
>>> OK?
>>>
>>> Thanks,
>>> Kugan
>>>
>>> +2013-11-22  Kugan Vivekanandarajah  <kuganv@linaro.org>
>>> +
>>> +	* libgcc/libgcc2.c (__udivmoddi4): Define new implementation when
>>> +	HAVE_NO_HW_DIVIDE is defined, for processors without any divide
>>> +     instructions.
>>
>>
>> The code looks fine to me.
>>
>> You should document HAVE_NO_HW_DIVIDE in gcc/doc/tm.texi in the Library
>> Calls section.  The macro should probably be something like
>> TARGET_HAS_NO_HW_DIVIDE.
>>
> Thanks for the review. Is this OK for trunk now?
Yes.  Please install.

jeff

Re: [RFC][LIBGCC][1 of 2] 64 bit divide implementation for processor without hw divide instruction

[Christophe Lyon]

On 27 November 2013 06:53, Jeff Law <law@redhat.com> wrote:
> On 11/25/13 17:29, Kugan wrote:
[...]
>> Thanks for the review. Is this OK for trunk now?
>
> Yes.  Please install.
>
> jeff
>
Thanks, committed on Kugan's behalf as r205444.

Re: [RFC][LIBGCC][2 of 2] 64 bit divide implementation for processor without hw divide instruction

[Kugan]

ping

Thanks,
Kugan

On 27/11/13 15:30, Kugan wrote:
> On 27/11/13 02:07, Richard Earnshaw wrote:
>> On 23/11/13 01:54, Kugan wrote:
> 
> [snip]
> 
>>> +2013-11-22  Kugan Vivekanandarajah  <kuganv@linaro.org>
>>> +
>>> +	* libgcc/config/arm/pbapi-lib.h (HAVE_NO_HW_DIVIDE): Define for
>>
>> It's bpabi-lib.h
> 
> Thanks for the review.
> 
>>> +	__ARM_ARCH_7_A__.
>>> +
>>>
>>>
>>
>> No, this will:
>> 1) Do the wrong thing for Cortex-a7, A12 and A15 (which all have HW
>> divide, and currently define __ARM_ARCH_7_A__).
>> 2) Do the wrong thing for v7-M and v7-R devices, which have Thumb HW
>> division instructions.
>> 3) Do the wrong thing for all pre-v7 devices, which don't have HW division.
>>
>> I think the correct solution is to test !defined(__ARM_ARCH_EXT_IDIV__)
> 
> I understand it now and updated the code as attached.
> 
> +2013-11-27  Kugan Vivekanandarajah  <kuganv@linaro.org>
> +
> +	* config/arm/bpapi-lib.h (TARGET_HAS_NO_HW_DIVIDE): Define for
> +	architectures that does not have hardware divide instruction.
> +	i.e. architectures that does not define __ARM_ARCH_EXT_IDIV__.
> +
> 
> 
> Is this OK for trunk now?
> Thanks,
> Kugan
> 

Re: [RFC][LIBGCC][2 of 2] 64 bit divide implementation for processor without hw divide instruction

[Ian Lance Taylor]

On Mon, Dec 2, 2013 at 10:39 PM, Kugan
<kugan.vivekanandarajah@linaro.org> wrote:
> ping

This patch needs to be approved by an ARM maintainer.

Ian

> On 27/11/13 15:30, Kugan wrote:
>> On 27/11/13 02:07, Richard Earnshaw wrote:
>>> On 23/11/13 01:54, Kugan wrote:
>>
>> [snip]
>>
>>>> +2013-11-22  Kugan Vivekanandarajah  <kuganv@linaro.org>
>>>> +
>>>> +   * libgcc/config/arm/pbapi-lib.h (HAVE_NO_HW_DIVIDE): Define for
>>>
>>> It's bpabi-lib.h
>>
>> Thanks for the review.
>>
>>>> +   __ARM_ARCH_7_A__.
>>>> +
>>>>
>>>>
>>>
>>> No, this will:
>>> 1) Do the wrong thing for Cortex-a7, A12 and A15 (which all have HW
>>> divide, and currently define __ARM_ARCH_7_A__).
>>> 2) Do the wrong thing for v7-M and v7-R devices, which have Thumb HW
>>> division instructions.
>>> 3) Do the wrong thing for all pre-v7 devices, which don't have HW division.
>>>
>>> I think the correct solution is to test !defined(__ARM_ARCH_EXT_IDIV__)
>>
>> I understand it now and updated the code as attached.
>>
>> +2013-11-27  Kugan Vivekanandarajah  <kuganv@linaro.org>
>> +
>> +     * config/arm/bpapi-lib.h (TARGET_HAS_NO_HW_DIVIDE): Define for
>> +     architectures that does not have hardware divide instruction.
>> +     i.e. architectures that does not define __ARM_ARCH_EXT_IDIV__.
>> +
>>
>>
>> Is this OK for trunk now?
>> Thanks,
>> Kugan
>>
>

Re: [RFC][LIBGCC][2 of 2] 64 bit divide implementation for processor without hw divide instruction

[Jeff Law]

On 12/02/13 23:39, Kugan wrote:
>>
>> +2013-11-27  Kugan Vivekanandarajah  <kuganv@linaro.org>
>> +
>> +	* config/arm/bpapi-lib.h (TARGET_HAS_NO_HW_DIVIDE): Define for
>> +	architectures that does not have hardware divide instruction.
>> +	i.e. architectures that does not define __ARM_ARCH_EXT_IDIV__.
>> +
>>
>>
>> Is this OK for trunk now?
Yes, this part is fine too.  AFAICT, it just implements what Richard E. 
suggested ;-)

jeff

Re: [RFC][LIBGCC][2 of 2] 64 bit divide implementation for processor without hw divide instruction

[Christophe Lyon]

Committed on Kugan's behalf as rev 205666.

Christophe.


On 3 December 2013 20:47, Jeff Law <law@redhat.com> wrote:
> On 12/02/13 23:39, Kugan wrote:
>>>
>>>
>>> +2013-11-27  Kugan Vivekanandarajah  <kuganv@linaro.org>
>>> +
>>> +       * config/arm/bpapi-lib.h (TARGET_HAS_NO_HW_DIVIDE): Define for
>>> +       architectures that does not have hardware divide instruction.
>>> +       i.e. architectures that does not define __ARM_ARCH_EXT_IDIV__.
>>> +
>>>
>>>
>>> Is this OK for trunk now?
>
> Yes, this part is fine too.  AFAICT, it just implements what Richard E.
> suggested ;-)
>
> jeff