Re: [PATCH 2/3] MIPS: use mips_isa enum instead hardcoded numbers

[YunQiang Su <syq@debian.org>]

Xi Ruoyao <xry111@mengyan1223.wang> 于2021年8月29日周日 下午1:54写道：
>
> On Sat, 2021-08-28 at 08:05 -0400, YunQiang Su wrote:
> > Currently mips-cpu.defs and mips.h are using hardcoded numbers
> > for isa level.
> >
> > Let's replace them with more readable enum mips_isa.
>
> Good, but there is something like "mips_isa_rev >= 32 && mips_isa_rev <
> 64" in mips.h and netbsd.h.  Not sure if they should be replaced
> altogether.
>

Yes. It is my fault. I missed them.
And we also need to replace the similar lines in config.gcc.

> If they are replaced as well, it will be not necessary to set special
> enum values.
>

no. mips_isa is a predefined macro exposed to C programmer.
Some existing code may depend on this behavior.

syq@XXX:~$ gcc -mabi=32 -mips64 -dM -E - < /dev/null | grep '__mips '
#define __mips 64
syq@XXX:~$ gcc -mabi=32 -mips3 -dM -E - < /dev/null | grep '__mips '
#define __mips 3
syq@XXX:~$ gcc -mabi=32 -mips32 -dM -E - < /dev/null | grep '__mips '
#define __mips 32

And codesearch give us some examples:
    http://codesearch.debian.net/search?q=__mips+%3E&literal=1

> How do the others think?
>
> > gcc/ChangeLog:
> >         * config/mips/mips.md: define_enum "mips_isa".
> >         * config/mips/mips.h (struct mips_cpu_info): use enum
> >           instead of int for 'isa' member.
> >         * config/mips/mips{.h,-cpus.def}: replace hardcoded
> >           numbers with enum.
> > ---
> >  gcc/config/mips/mips-cpus.def | 228 +++++++++++++++++----------------
> > -
> >  gcc/config/mips/mips.h        |  50 ++++----
> >  gcc/config/mips/mips.md       |  17 +++
> >  3 files changed, 156 insertions(+), 139 deletions(-)
> >
> > diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-
> > cpus.def
> > index b02294be4..45fb6bc8b 100644
> > --- a/gcc/config/mips/mips-cpus.def
> > +++ b/gcc/config/mips/mips-cpus.def
> > @@ -33,146 +33,146 @@ along with GCC; see the file COPYING3.  If not
> > see
> >     where the arguments are the fields of struct mips_cpu_info.  */
> >
> >  /* Entries for generic ISAs.  */
> > -MIPS_CPU ("mips1", PROCESSOR_R3000, 1, 0)
> > -MIPS_CPU ("mips2", PROCESSOR_R6000, 2, PTF_AVOID_BRANCHLIKELY_SIZE)
> > -MIPS_CPU ("mips3", PROCESSOR_R4000, 3, PTF_AVOID_BRANCHLIKELY_SIZE)
> > -MIPS_CPU ("mips4", PROCESSOR_R10000, 4, PTF_AVOID_BRANCHLIKELY_SIZE)
> > +MIPS_CPU ("mips1", PROCESSOR_R3000, MIPS_ISA_MIPS1, 0)
> > +MIPS_CPU ("mips2", PROCESSOR_R6000, MIPS_ISA_MIPS2,
> > PTF_AVOID_BRANCHLIKELY_SIZE)
> > +MIPS_CPU ("mips3", PROCESSOR_R4000, MIPS_ISA_MIPS3,
> > PTF_AVOID_BRANCHLIKELY_SIZE)
> > +MIPS_CPU ("mips4", PROCESSOR_R10000, MIPS_ISA_MIPS4,
> > PTF_AVOID_BRANCHLIKELY_SIZE)
> >  /* Prefer not to use branch-likely instructions for generic MIPS32rX
> >     and MIPS64rX code.  The instructions were officially deprecated
> >     in revisions 2 and earlier, but revision 3 is likely to downgrade
> >     that to a recommendation to avoid the instructions in code that
> >     isn't tuned to a specific processor.  */
> > -MIPS_CPU ("mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > -MIPS_CPU ("mips32r2", PROCESSOR_74KF2_1, 33,
> > PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > +MIPS_CPU ("mips32", PROCESSOR_4KC, MIPS_ISA_MIPS32,
> > PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > +MIPS_CPU ("mips32r2", PROCESSOR_74KF2_1, MIPS_ISA_MIPS32R2,
> > PTF_AVOID_BRANCHLIKELY_ALWAYS)
> >  /* mips32r3 is micromips hense why it uses the M4K processor.  */
> > -MIPS_CPU ("mips32r3", PROCESSOR_M4K, 34,
> > PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > -MIPS_CPU ("mips32r5", PROCESSOR_P5600, 36,
> > PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > -MIPS_CPU ("mips32r6", PROCESSOR_I6400, 37, 0)
> > -MIPS_CPU ("mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > +MIPS_CPU ("mips32r3", PROCESSOR_M4K, MIPS_ISA_MIPS32R3,
> > PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > +MIPS_CPU ("mips32r5", PROCESSOR_P5600, MIPS_ISA_MIPS32R5,
> > PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > +MIPS_CPU ("mips32r6", PROCESSOR_I6400, MIPS_ISA_MIPS32R6, 0)
> > +MIPS_CPU ("mips64", PROCESSOR_5KC, MIPS_ISA_MIPS64,
> > PTF_AVOID_BRANCHLIKELY_ALWAYS)
> >  /* ??? For now just tune the generic MIPS64r2 and above for 5KC as
> > well.   */
> > -MIPS_CPU ("mips64r2", PROCESSOR_5KC, 65,
> > PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > -MIPS_CPU ("mips64r3", PROCESSOR_5KC, 66,
> > PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > -MIPS_CPU ("mips64r5", PROCESSOR_5KC, 68,
> > PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > -MIPS_CPU ("mips64r6", PROCESSOR_I6400, 69, 0)
> > +MIPS_CPU ("mips64r2", PROCESSOR_5KC, MIPS_ISA_MIPS64R2,
> > PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > +MIPS_CPU ("mips64r3", PROCESSOR_5KC, MIPS_ISA_MIPS64R3,
> > PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > +MIPS_CPU ("mips64r5", PROCESSOR_5KC, MIPS_ISA_MIPS64R5,
> > PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > +MIPS_CPU ("mips64r6", PROCESSOR_I6400, MIPS_ISA_MIPS64R6, 0)
> >
> >  /* MIPS I processors.  */
> > -MIPS_CPU ("r3000", PROCESSOR_R3000, 1, 0)
> > -MIPS_CPU ("r2000", PROCESSOR_R3000, 1, 0)
> > -MIPS_CPU ("r3900", PROCESSOR_R3900, 1, 0)
> > +MIPS_CPU ("r3000", PROCESSOR_R3000, MIPS_ISA_MIPS1, 0)
> > +MIPS_CPU ("r2000", PROCESSOR_R3000, MIPS_ISA_MIPS1, 0)
> > +MIPS_CPU ("r3900", PROCESSOR_R3900, MIPS_ISA_MIPS1, 0)
> >
> >  /* MIPS II processors.  */
> > -MIPS_CPU ("r6000", PROCESSOR_R6000, 2, 0)
> > +MIPS_CPU ("r6000", PROCESSOR_R6000, MIPS_ISA_MIPS2, 0)
> >
> >  /* MIPS III processors.  */
> > -MIPS_CPU ("r4000", PROCESSOR_R4000, 3, 0)
> > -MIPS_CPU ("vr4100", PROCESSOR_R4100, 3, 0)
> > -MIPS_CPU ("vr4111", PROCESSOR_R4111, 3, 0)
> > -MIPS_CPU ("vr4120", PROCESSOR_R4120, 3, 0)
> > -MIPS_CPU ("vr4130", PROCESSOR_R4130, 3, 0)
> > -MIPS_CPU ("vr4300", PROCESSOR_R4300, 3, 0)
> > -MIPS_CPU ("r4400", PROCESSOR_R4000, 3, 0)
> > -MIPS_CPU ("r4600", PROCESSOR_R4600, 3, 0)
> > -MIPS_CPU ("orion", PROCESSOR_R4600, 3, 0)
> > -MIPS_CPU ("r4650", PROCESSOR_R4650, 3, 0)
> > -MIPS_CPU ("r4700", PROCESSOR_R4700, 3, 0)
> > -MIPS_CPU ("r5900", PROCESSOR_R5900, 3, 0)
> > +MIPS_CPU ("r4000", PROCESSOR_R4000, MIPS_ISA_MIPS3, 0)
> > +MIPS_CPU ("vr4100", PROCESSOR_R4100, MIPS_ISA_MIPS3, 0)
> > +MIPS_CPU ("vr4111", PROCESSOR_R4111, MIPS_ISA_MIPS3, 0)
> > +MIPS_CPU ("vr4120", PROCESSOR_R4120, MIPS_ISA_MIPS3, 0)
> > +MIPS_CPU ("vr4130", PROCESSOR_R4130, MIPS_ISA_MIPS3, 0)
> > +MIPS_CPU ("vr4300", PROCESSOR_R4300, MIPS_ISA_MIPS3, 0)
> > +MIPS_CPU ("r4400", PROCESSOR_R4000, MIPS_ISA_MIPS3, 0)
> > +MIPS_CPU ("r4600", PROCESSOR_R4600, MIPS_ISA_MIPS3, 0)
> > +MIPS_CPU ("orion", PROCESSOR_R4600, MIPS_ISA_MIPS3, 0)
> > +MIPS_CPU ("r4650", PROCESSOR_R4650, MIPS_ISA_MIPS3, 0)
> > +MIPS_CPU ("r4700", PROCESSOR_R4700, MIPS_ISA_MIPS3, 0)
> > +MIPS_CPU ("r5900", PROCESSOR_R5900, MIPS_ISA_MIPS3, 0)
> >  /* ST Loongson 2E/2F processors.  */
> > -MIPS_CPU ("loongson2e", PROCESSOR_LOONGSON_2E, 3,
> > PTF_AVOID_BRANCHLIKELY_SPEED)
> > -MIPS_CPU ("loongson2f", PROCESSOR_LOONGSON_2F, 3,
> > PTF_AVOID_BRANCHLIKELY_SPEED)
> > +MIPS_CPU ("loongson2e", PROCESSOR_LOONGSON_2E, MIPS_ISA_MIPS3,
> > PTF_AVOID_BRANCHLIKELY_SPEED)
> > +MIPS_CPU ("loongson2f", PROCESSOR_LOONGSON_2F, MIPS_ISA_MIPS3,
> > PTF_AVOID_BRANCHLIKELY_SPEED)
> >
> >  /* MIPS IV processors. */
> > -MIPS_CPU ("r8000", PROCESSOR_R8000, 4, 0)
> > -MIPS_CPU ("r10000", PROCESSOR_R10000, 4, 0)
> > -MIPS_CPU ("r12000", PROCESSOR_R10000, 4, 0)
> > -MIPS_CPU ("r14000", PROCESSOR_R10000, 4, 0)
> > -MIPS_CPU ("r16000", PROCESSOR_R10000, 4, 0)
> > -MIPS_CPU ("vr5000", PROCESSOR_R5000, 4, 0)
> > -MIPS_CPU ("vr5400", PROCESSOR_R5400, 4, 0)
> > -MIPS_CPU ("vr5500", PROCESSOR_R5500, 4, PTF_AVOID_BRANCHLIKELY_SPEED)
> > -MIPS_CPU ("rm7000", PROCESSOR_R7000, 4, 0)
> > -MIPS_CPU ("rm9000", PROCESSOR_R9000, 4, 0)
> > +MIPS_CPU ("r8000", PROCESSOR_R8000, MIPS_ISA_MIPS4, 0)
> > +MIPS_CPU ("r10000", PROCESSOR_R10000, MIPS_ISA_MIPS4, 0)
> > +MIPS_CPU ("r12000", PROCESSOR_R10000, MIPS_ISA_MIPS4, 0)
> > +MIPS_CPU ("r14000", PROCESSOR_R10000, MIPS_ISA_MIPS4, 0)
> > +MIPS_CPU ("r16000", PROCESSOR_R10000, MIPS_ISA_MIPS4, 0)
> > +MIPS_CPU ("vr5000", PROCESSOR_R5000, MIPS_ISA_MIPS4, 0)
> > +MIPS_CPU ("vr5400", PROCESSOR_R5400, MIPS_ISA_MIPS4, 0)
> > +MIPS_CPU ("vr5500", PROCESSOR_R5500, MIPS_ISA_MIPS4,
> > PTF_AVOID_BRANCHLIKELY_SPEED)
> > +MIPS_CPU ("rm7000", PROCESSOR_R7000, MIPS_ISA_MIPS4, 0)
> > +MIPS_CPU ("rm9000", PROCESSOR_R9000, MIPS_ISA_MIPS4, 0)
> >
> >  /* MIPS32 processors.  */
> > -MIPS_CPU ("4kc", PROCESSOR_4KC, 32, 0)
> > -MIPS_CPU ("4km", PROCESSOR_4KC, 32, 0)
> > -MIPS_CPU ("4kp", PROCESSOR_4KP, 32, 0)
> > -MIPS_CPU ("4ksc", PROCESSOR_4KC, 32, 0)
> > +MIPS_CPU ("4kc", PROCESSOR_4KC, MIPS_ISA_MIPS32, 0)
> > +MIPS_CPU ("4km", PROCESSOR_4KC, MIPS_ISA_MIPS32, 0)
> > +MIPS_CPU ("4kp", PROCESSOR_4KP, MIPS_ISA_MIPS32, 0)
> > +MIPS_CPU ("4ksc", PROCESSOR_4KC, MIPS_ISA_MIPS32, 0)
> >
> >  /* MIPS32 Release 2 processors.  */
> > -MIPS_CPU ("m4k", PROCESSOR_M4K, 33, 0)
> > -MIPS_CPU ("m14kc", PROCESSOR_M4K, 33, 0)
> > -MIPS_CPU ("m14k", PROCESSOR_M4K, 33, 0)
> > -MIPS_CPU ("m14ke", PROCESSOR_M4K, 33, 0)
> > -MIPS_CPU ("m14kec", PROCESSOR_M4K, 33, 0)
> > -MIPS_CPU ("4kec", PROCESSOR_4KC, 33, 0)
> > -MIPS_CPU ("4kem", PROCESSOR_4KC, 33, 0)
> > -MIPS_CPU ("4kep", PROCESSOR_4KP, 33, 0)
> > -MIPS_CPU ("4ksd", PROCESSOR_4KC, 33, 0)
> > -
> > -MIPS_CPU ("24kc", PROCESSOR_24KC, 33, 0)
> > -MIPS_CPU ("24kf2_1", PROCESSOR_24KF2_1, 33, 0)
> > -MIPS_CPU ("24kf", PROCESSOR_24KF2_1, 33, 0)
> > -MIPS_CPU ("24kf1_1", PROCESSOR_24KF1_1, 33, 0)
> > -MIPS_CPU ("24kfx", PROCESSOR_24KF1_1, 33, 0)
> > -MIPS_CPU ("24kx", PROCESSOR_24KF1_1, 33, 0)
> > -
> > -MIPS_CPU ("24kec", PROCESSOR_24KC, 33, 0) /* 24K with DSP.  */
> > -MIPS_CPU ("24kef2_1", PROCESSOR_24KF2_1, 33, 0)
> > -MIPS_CPU ("24kef", PROCESSOR_24KF2_1, 33, 0)
> > -MIPS_CPU ("24kef1_1", PROCESSOR_24KF1_1, 33, 0)
> > -MIPS_CPU ("24kefx", PROCESSOR_24KF1_1, 33, 0)
> > -MIPS_CPU ("24kex", PROCESSOR_24KF1_1, 33, 0)
> > -
> > -MIPS_CPU ("34kc", PROCESSOR_24KC, 33, 0) /* 34K with MT/DSP.  */
> > -MIPS_CPU ("34kf2_1", PROCESSOR_24KF2_1, 33, 0)
> > -MIPS_CPU ("34kf", PROCESSOR_24KF2_1, 33, 0)
> > -MIPS_CPU ("34kf1_1", PROCESSOR_24KF1_1, 33, 0)
> > -MIPS_CPU ("34kfx", PROCESSOR_24KF1_1, 33, 0)
> > -MIPS_CPU ("34kx", PROCESSOR_24KF1_1, 33, 0)
> > -MIPS_CPU ("34kn", PROCESSOR_24KC, 33, 0)  /* 34K with MT but no DSP.
> > */
> > -
> > -MIPS_CPU ("74kc", PROCESSOR_74KC, 33, PTF_AVOID_IMADD) /* 74K with
> > DSPr2.  */
> > -MIPS_CPU ("74kf2_1", PROCESSOR_74KF2_1, 33, PTF_AVOID_IMADD)
> > -MIPS_CPU ("74kf", PROCESSOR_74KF2_1, 33, PTF_AVOID_IMADD)
> > -MIPS_CPU ("74kf1_1", PROCESSOR_74KF1_1, 33, PTF_AVOID_IMADD)
> > -MIPS_CPU ("74kfx", PROCESSOR_74KF1_1, 33, PTF_AVOID_IMADD)
> > -MIPS_CPU ("74kx", PROCESSOR_74KF1_1, 33, PTF_AVOID_IMADD)
> > -MIPS_CPU ("74kf3_2", PROCESSOR_74KF3_2, 33, PTF_AVOID_IMADD)
> > -
> > -MIPS_CPU ("1004kc", PROCESSOR_24KC, 33, 0) /* 1004K with MT/DSP.  */
> > -MIPS_CPU ("1004kf2_1", PROCESSOR_24KF2_1, 33, 0)
> > -MIPS_CPU ("1004kf", PROCESSOR_24KF2_1, 33, 0)
> > -MIPS_CPU ("1004kf1_1", PROCESSOR_24KF1_1, 33, 0)
> > -
> > -MIPS_CPU ("interaptiv", PROCESSOR_24KF2_1, 33, 0)
> > +MIPS_CPU ("m4k", PROCESSOR_M4K, MIPS_ISA_MIPS32R2, 0)
> > +MIPS_CPU ("m14kc", PROCESSOR_M4K, MIPS_ISA_MIPS32R2, 0)
> > +MIPS_CPU ("m14k", PROCESSOR_M4K, MIPS_ISA_MIPS32R2, 0)
> > +MIPS_CPU ("m14ke", PROCESSOR_M4K, MIPS_ISA_MIPS32R2, 0)
> > +MIPS_CPU ("m14kec", PROCESSOR_M4K, MIPS_ISA_MIPS32R2, 0)
> > +MIPS_CPU ("4kec", PROCESSOR_4KC, MIPS_ISA_MIPS32R2, 0)
> > +MIPS_CPU ("4kem", PROCESSOR_4KC, MIPS_ISA_MIPS32R2, 0)
> > +MIPS_CPU ("4kep", PROCESSOR_4KP, MIPS_ISA_MIPS32R2, 0)
> > +MIPS_CPU ("4ksd", PROCESSOR_4KC, MIPS_ISA_MIPS32R2, 0)
> > +
> > +MIPS_CPU ("24kc", PROCESSOR_24KC, MIPS_ISA_MIPS32R2, 0)
> > +MIPS_CPU ("24kf2_1", PROCESSOR_24KF2_1, MIPS_ISA_MIPS32R2, 0)
> > +MIPS_CPU ("24kf", PROCESSOR_24KF2_1, MIPS_ISA_MIPS32R2, 0)
> > +MIPS_CPU ("24kf1_1", PROCESSOR_24KF1_1, MIPS_ISA_MIPS32R2, 0)
> > +MIPS_CPU ("24kfx", PROCESSOR_24KF1_1, MIPS_ISA_MIPS32R2, 0)
> > +MIPS_CPU ("24kx", PROCESSOR_24KF1_1, MIPS_ISA_MIPS32R2, 0)
> > +
> > +MIPS_CPU ("24kec", PROCESSOR_24KC, MIPS_ISA_MIPS32R2, 0) /* 24K with
> > DSP.  */
> > +MIPS_CPU ("24kef2_1", PROCESSOR_24KF2_1, MIPS_ISA_MIPS32R2, 0)
> > +MIPS_CPU ("24kef", PROCESSOR_24KF2_1, MIPS_ISA_MIPS32R2, 0)
> > +MIPS_CPU ("24kef1_1", PROCESSOR_24KF1_1, MIPS_ISA_MIPS32R2, 0)
> > +MIPS_CPU ("24kefx", PROCESSOR_24KF1_1, MIPS_ISA_MIPS32R2, 0)
> > +MIPS_CPU ("24kex", PROCESSOR_24KF1_1, MIPS_ISA_MIPS32R2, 0)
> > +
> > +MIPS_CPU ("34kc", PROCESSOR_24KC, MIPS_ISA_MIPS32R2, 0) /* 34K with
> > MT/DSP.  */
> > +MIPS_CPU ("34kf2_1", PROCESSOR_24KF2_1, MIPS_ISA_MIPS32R2, 0)
> > +MIPS_CPU ("34kf", PROCESSOR_24KF2_1, MIPS_ISA_MIPS32R2, 0)
> > +MIPS_CPU ("34kf1_1", PROCESSOR_24KF1_1, MIPS_ISA_MIPS32R2, 0)
> > +MIPS_CPU ("34kfx", PROCESSOR_24KF1_1, MIPS_ISA_MIPS32R2, 0)
> > +MIPS_CPU ("34kx", PROCESSOR_24KF1_1, MIPS_ISA_MIPS32R2, 0)
> > +MIPS_CPU ("34kn", PROCESSOR_24KC, MIPS_ISA_MIPS32R2, 0)  /* 34K with
> > MT but no DSP.  */
> > +
> > +MIPS_CPU ("74kc", PROCESSOR_74KC, MIPS_ISA_MIPS32R2, PTF_AVOID_IMADD)
> > /* 74K with DSPr2.  */
> > +MIPS_CPU ("74kf2_1", PROCESSOR_74KF2_1, MIPS_ISA_MIPS32R2,
> > PTF_AVOID_IMADD)
> > +MIPS_CPU ("74kf", PROCESSOR_74KF2_1, MIPS_ISA_MIPS32R2,
> > PTF_AVOID_IMADD)
> > +MIPS_CPU ("74kf1_1", PROCESSOR_74KF1_1, MIPS_ISA_MIPS32R2,
> > PTF_AVOID_IMADD)
> > +MIPS_CPU ("74kfx", PROCESSOR_74KF1_1, MIPS_ISA_MIPS32R2,
> > PTF_AVOID_IMADD)
> > +MIPS_CPU ("74kx", PROCESSOR_74KF1_1, MIPS_ISA_MIPS32R2,
> > PTF_AVOID_IMADD)
> > +MIPS_CPU ("74kf3_2", PROCESSOR_74KF3_2, MIPS_ISA_MIPS32R2,
> > PTF_AVOID_IMADD)
> > +
> > +MIPS_CPU ("1004kc", PROCESSOR_24KC, MIPS_ISA_MIPS32R2, 0) /* 1004K
> > with MT/DSP.  */
> > +MIPS_CPU ("1004kf2_1", PROCESSOR_24KF2_1, MIPS_ISA_MIPS32R2, 0)
> > +MIPS_CPU ("1004kf", PROCESSOR_24KF2_1, MIPS_ISA_MIPS32R2, 0)
> > +MIPS_CPU ("1004kf1_1", PROCESSOR_24KF1_1, MIPS_ISA_MIPS32R2, 0)
> > +
> > +MIPS_CPU ("interaptiv", PROCESSOR_24KF2_1, MIPS_ISA_MIPS32R2, 0)
> >
> >  /* MIPS32 Release 5 processors.  */
> > -MIPS_CPU ("p5600", PROCESSOR_P5600, 36, (PTF_AVOID_BRANCHLIKELY_SPEED
> > +MIPS_CPU ("p5600", PROCESSOR_P5600, MIPS_ISA_MIPS32R5,
> > (PTF_AVOID_BRANCHLIKELY_SPEED
> >                                          | PTF_AVOID_IMADD))
> > -MIPS_CPU ("m5100", PROCESSOR_M5100, 36, PTF_AVOID_BRANCHLIKELY_SPEED)
> > -MIPS_CPU ("m5101", PROCESSOR_M5100, 36, PTF_AVOID_BRANCHLIKELY_SPEED)
> > +MIPS_CPU ("m5100", PROCESSOR_M5100, MIPS_ISA_MIPS32R5,
> > PTF_AVOID_BRANCHLIKELY_SPEED)
> > +MIPS_CPU ("m5101", PROCESSOR_M5100, MIPS_ISA_MIPS32R5,
> > PTF_AVOID_BRANCHLIKELY_SPEED)
> >
> >  /* MIPS64 processors.  */
> > -MIPS_CPU ("5kc", PROCESSOR_5KC, 64, 0)
> > -MIPS_CPU ("5kf", PROCESSOR_5KF, 64, 0)
> > -MIPS_CPU ("20kc", PROCESSOR_20KC, 64, PTF_AVOID_BRANCHLIKELY_SPEED)
> > -MIPS_CPU ("sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY_SPEED)
> > -MIPS_CPU ("sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY_SPEED)
> > -MIPS_CPU ("sr71000", PROCESSOR_SR71000, 64,
> > PTF_AVOID_BRANCHLIKELY_SPEED)
> > -MIPS_CPU ("xlr", PROCESSOR_XLR, 64, PTF_AVOID_BRANCHLIKELY_SPEED)
> > +MIPS_CPU ("5kc", PROCESSOR_5KC, MIPS_ISA_MIPS64, 0)
> > +MIPS_CPU ("5kf", PROCESSOR_5KF, MIPS_ISA_MIPS64, 0)
> > +MIPS_CPU ("20kc", PROCESSOR_20KC, MIPS_ISA_MIPS64,
> > PTF_AVOID_BRANCHLIKELY_SPEED)
> > +MIPS_CPU ("sb1", PROCESSOR_SB1, MIPS_ISA_MIPS64,
> > PTF_AVOID_BRANCHLIKELY_SPEED)
> > +MIPS_CPU ("sb1a", PROCESSOR_SB1A, MIPS_ISA_MIPS64,
> > PTF_AVOID_BRANCHLIKELY_SPEED)
> > +MIPS_CPU ("sr71000", PROCESSOR_SR71000, MIPS_ISA_MIPS64,
> > PTF_AVOID_BRANCHLIKELY_SPEED)
> > +MIPS_CPU ("xlr", PROCESSOR_XLR, MIPS_ISA_MIPS64,
> > PTF_AVOID_BRANCHLIKELY_SPEED)
> >
> >  /* MIPS64 Release 2 processors.  */
> > -MIPS_CPU ("loongson3a", PROCESSOR_GS464, 65,
> > PTF_AVOID_BRANCHLIKELY_SPEED)
> > -MIPS_CPU ("gs464", PROCESSOR_GS464, 65, PTF_AVOID_BRANCHLIKELY_SPEED)
> > -MIPS_CPU ("gs464e", PROCESSOR_GS464E, 65,
> > PTF_AVOID_BRANCHLIKELY_SPEED)
> > -MIPS_CPU ("gs264e", PROCESSOR_GS264E, 65,
> > PTF_AVOID_BRANCHLIKELY_SPEED)
> > -MIPS_CPU ("octeon", PROCESSOR_OCTEON, 65,
> > PTF_AVOID_BRANCHLIKELY_SPEED)
> > -MIPS_CPU ("octeon+", PROCESSOR_OCTEON, 65,
> > PTF_AVOID_BRANCHLIKELY_SPEED)
> > -MIPS_CPU ("octeon2", PROCESSOR_OCTEON2, 65,
> > PTF_AVOID_BRANCHLIKELY_SPEED)
> > -MIPS_CPU ("octeon3", PROCESSOR_OCTEON3, 65,
> > PTF_AVOID_BRANCHLIKELY_SPEED)
> > -MIPS_CPU ("xlp", PROCESSOR_XLP, 65, PTF_AVOID_BRANCHLIKELY_SPEED)
> > +MIPS_CPU ("loongson3a", PROCESSOR_GS464, MIPS_ISA_MIPS64R2,
> > PTF_AVOID_BRANCHLIKELY_SPEED)
> > +MIPS_CPU ("gs464", PROCESSOR_GS464, MIPS_ISA_MIPS64R2,
> > PTF_AVOID_BRANCHLIKELY_SPEED)
> > +MIPS_CPU ("gs464e", PROCESSOR_GS464E, MIPS_ISA_MIPS64R2,
> > PTF_AVOID_BRANCHLIKELY_SPEED)
> > +MIPS_CPU ("gs264e", PROCESSOR_GS264E, MIPS_ISA_MIPS64R2,
> > PTF_AVOID_BRANCHLIKELY_SPEED)
> > +MIPS_CPU ("octeon", PROCESSOR_OCTEON, MIPS_ISA_MIPS64R2,
> > PTF_AVOID_BRANCHLIKELY_SPEED)
> > +MIPS_CPU ("octeon+", PROCESSOR_OCTEON, MIPS_ISA_MIPS64R2,
> > PTF_AVOID_BRANCHLIKELY_SPEED)
> > +MIPS_CPU ("octeon2", PROCESSOR_OCTEON2, MIPS_ISA_MIPS64R2,
> > PTF_AVOID_BRANCHLIKELY_SPEED)
> > +MIPS_CPU ("octeon3", PROCESSOR_OCTEON3, MIPS_ISA_MIPS64R2,
> > PTF_AVOID_BRANCHLIKELY_SPEED)
> > +MIPS_CPU ("xlp", PROCESSOR_XLP, MIPS_ISA_MIPS64R2,
> > PTF_AVOID_BRANCHLIKELY_SPEED)
> >
> >  /* MIPS64 Release 6 processors.  */
> > -MIPS_CPU ("i6400", PROCESSOR_I6400, 69, 0)
> > -MIPS_CPU ("i6500", PROCESSOR_I6400, 69, 0)
> > -MIPS_CPU ("p6600", PROCESSOR_P6600, 69, 0)
> > +MIPS_CPU ("i6400", PROCESSOR_I6400, MIPS_ISA_MIPS64R6, 0)
> > +MIPS_CPU ("i6500", PROCESSOR_I6400, MIPS_ISA_MIPS64R6, 0)
> > +MIPS_CPU ("p6600", PROCESSOR_P6600, MIPS_ISA_MIPS64R6, 0)
> > diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
> > index 47aac9d3d..3b3af9c0d 100644
> > --- a/gcc/config/mips/mips.h
> > +++ b/gcc/config/mips/mips.h
> > @@ -81,7 +81,7 @@ struct mips_cpu_info {
> >    enum processor cpu;
> >
> >    /* The ISA level that the processor implements.  */
> > -  int isa;
> > +  enum mips_isa isa;
> >
> >    /* A mask of PTF_* values.  */
> >    unsigned int tune_flags;
> > @@ -247,20 +247,20 @@ struct mips_cpu_info {
> >    (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
> >
> >  /* Generic ISA defines.  */
> > -#define ISA_MIPS1                  (mips_isa == 1)
> > -#define ISA_MIPS2                  (mips_isa == 2)
> > -#define ISA_MIPS3                   (mips_isa == 3)
> > -#define ISA_MIPS4                  (mips_isa == 4)
> > -#define ISA_MIPS32                 (mips_isa == 32)
> > -#define ISA_MIPS32R2               (mips_isa == 33)
> > -#define ISA_MIPS32R3               (mips_isa == 34)
> > -#define ISA_MIPS32R5               (mips_isa == 36)
> > -#define ISA_MIPS32R6               (mips_isa == 37)
> > -#define ISA_MIPS64                  (mips_isa == 64)
> > -#define ISA_MIPS64R2               (mips_isa == 65)
> > -#define ISA_MIPS64R3               (mips_isa == 66)
> > -#define ISA_MIPS64R5               (mips_isa == 68)
> > -#define ISA_MIPS64R6               (mips_isa == 69)
> > +#define ISA_MIPS1                  (mips_isa == MIPS_ISA_MIPS1)
> > +#define ISA_MIPS2                  (mips_isa == MIPS_ISA_MIPS2)
> > +#define ISA_MIPS3                   (mips_isa == MIPS_ISA_MIPS3)
> > +#define ISA_MIPS4                  (mips_isa == MIPS_ISA_MIPS4)
> > +#define ISA_MIPS32                 (mips_isa == MIPS_ISA_MIPS32)
> > +#define ISA_MIPS32R2               (mips_isa == MIPS_ISA_MIPS32R2)
> > +#define ISA_MIPS32R3               (mips_isa == MIPS_ISA_MIPS32R3)
> > +#define ISA_MIPS32R5               (mips_isa == MIPS_ISA_MIPS32R5)
> > +#define ISA_MIPS32R6               (mips_isa == MIPS_ISA_MIPS32R6)
> > +#define ISA_MIPS64                  (mips_isa == MIPS_ISA_MIPS64)
> > +#define ISA_MIPS64R2               (mips_isa == MIPS_ISA_MIPS64R2)
> > +#define ISA_MIPS64R3               (mips_isa == MIPS_ISA_MIPS64R3)
> > +#define ISA_MIPS64R5               (mips_isa == MIPS_ISA_MIPS64R5)
> > +#define ISA_MIPS64R6               (mips_isa == MIPS_ISA_MIPS64R6)
> >
> >  /* Architecture target defines.  */
> >  #define TARGET_LOONGSON_2E          (mips_arch ==
> > PROCESSOR_LOONGSON_2E)
> > @@ -708,25 +708,25 @@ struct mips_cpu_info {
> >  #endif
> >
> >  #ifndef MULTILIB_ISA_DEFAULT
> > -#if MIPS_ISA_DEFAULT == 1
> > +#if MIPS_ISA_DEFAULT == MIPS_ISA_MIPS1
> >  #define MULTILIB_ISA_DEFAULT "mips1"
> > -#elif MIPS_ISA_DEFAULT == 2
> > +#elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS2
> >  #define MULTILIB_ISA_DEFAULT "mips2"
> > -#elif MIPS_ISA_DEFAULT == 3
> > +#elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS3
> >  #define MULTILIB_ISA_DEFAULT "mips3"
> > -#elif MIPS_ISA_DEFAULT == 4
> > +#elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS4
> >  #define MULTILIB_ISA_DEFAULT "mips4"
> > -#elif MIPS_ISA_DEFAULT == 32
> > +#elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS32
> >  #define MULTILIB_ISA_DEFAULT "mips32"
> > -#elif MIPS_ISA_DEFAULT == 33
> > +#elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS32R2
> >  #define MULTILIB_ISA_DEFAULT "mips32r2"
> > -#elif MIPS_ISA_DEFAULT == 37
> > +#elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS32R6
> >  #define MULTILIB_ISA_DEFAULT "mips32r6"
> > -#elif MIPS_ISA_DEFAULT == 64
> > +#elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS64
> >  #define MULTILIB_ISA_DEFAULT "mips64"
> > -#elif MIPS_ISA_DEFAULT == 65
> > +#elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS64R2
> >  #define MULTILIB_ISA_DEFAULT "mips64r2"
> > -#elif MIPS_ISA_DEFAULT == 69
> > +#elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS64R6
> >  #define MULTILIB_ISA_DEFAULT "mips64r6"
> >  #else
> >  #define MULTILIB_ISA_DEFAULT "mips1"
> > diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
> > index 455b9b802..f35e50ced 100644
> > --- a/gcc/config/mips/mips.md
> > +++ b/gcc/config/mips/mips.md
> > @@ -21,6 +21,23 @@
> >  ;; along with GCC; see the file COPYING3.  If not see
> >  ;; <http://www.gnu.org/licenses/>.
> >
> > +(define_enum "mips_isa" [
> > +  mips1=1
> > +  mips2
> > +  mips3
> > +  mips4
> > +  mips32=32
> > +  mips32r2
> > +  mips32r3
> > +  mips32r5=36
> > +  mips32r6
> > +  mips64=64
> > +  mips64r2
> > +  mips64r3
> > +  mips64r5=68
> > +  mips64r6
> > +])
> > +
> >  (define_enum "processor" [
> >    r3000
> >    4kc
>
> --
> Xi Ruoyao <xry111@mengyan1223.wang>
> School of Aerospace Science and Technology, Xidian University
>