From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x62a.google.com (mail-pl1-x62a.google.com [IPv6:2607:f8b0:4864:20::62a]) by sourceware.org (Postfix) with ESMTPS id E070F3858C33 for ; Wed, 19 Jul 2023 06:58:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E070F3858C33 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-1b9e93a538dso36883155ad.3 for ; Tue, 18 Jul 2023 23:58:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1689749903; x=1690354703; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=R/UuvBOmSkttN2JDpYa96ZmUbVoDnbB4P2LJ4kY6TwE=; b=AJiy7FkYvt2i+qbR4/cKYswngBow/GJ5+mJJDUB8azp+uUWMmJ5CrvzZb9A+SN3mqC skWb1b7uzzVSYyqds+pQu2dXCkWw8TI7aTQz4TseD3ExBzn8WPKtWPIx2MhGThNQc3Ys Sj25FzknGXzqcaL/6vUjCGYLna098c3/Tt9zIOh+4IsVtcXHmhWCn30W7O4XZNeNYZwv O6PlMc8FXC57vY3QATTzLUZanWZC960W3Aqk/vqJsbxszT7VtdOILeaqKjN17lDFLQS/ aKVsJhRBBnsUwnXgKHnzM1oKXvjG9kQCX6vvUoctjdMO3gi2H+7hvV7TvDf7Z1OE/Nzu f0Dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689749903; x=1690354703; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=R/UuvBOmSkttN2JDpYa96ZmUbVoDnbB4P2LJ4kY6TwE=; b=hzrzSpi2i+Q0xgFcs4gW3ITCygUcpeW7aH1pS1F8ANVrglZYkaY7TLGjF4YemexUgr h2WyO+d3c407UBIDq24VayPxbm+uCYhv5W6/2p6d1on4o8Ikuve3mhJ5mJSPwtwCg8HP EStsoUQNe0+AV6HvIpXjMuV/xd058xxPmxXcwrrvmhdeyUPgjbEQZc3psxxdbKVdK7C3 B7e2nx+EhutaIwgF7RggAReAw8Jp4PsfeR5lyKZ9uYHvI66afydq4HfB45paR42rhM8g 7Y/OVmce7J+XZUAvFMePAcvIJfOB29XSIeyvFG+trtxxaONxfkGfTFjG/h0Y6VF5sXM9 MvdA== X-Gm-Message-State: ABy/qLb0FtVMXdM6ix1gEpjjS7uG+VUoE3OLcZtKWAfpiw0vG0dxViC+ JPIxYtI0jTq1abw7cjefpEicJaUjpePHUROqEpk= X-Google-Smtp-Source: APBJJlG9kxIHlnxeWX7m5n7b1rn7ZT5V5tEqMbbuZXfUMC7MFHfZJ8Qa87UxCAMFijlnzi+5yANS10Z2Og8Aa9swlH4= X-Received: by 2002:a17:902:e549:b0:1b8:aef2:773e with SMTP id n9-20020a170902e54900b001b8aef2773emr18494487plf.46.1689749903047; Tue, 18 Jul 2023 23:58:23 -0700 (PDT) MIME-Version: 1.0 References: <20230719041639.2967597-1-yunqiang.su@cipunited.com> In-Reply-To: From: YunQiang Su Date: Wed, 19 Jul 2023 14:58:10 +0800 Message-ID: Subject: Re: [PATCH v2] Store_bit_field_1: Use SUBREG instead of REG if possible To: Richard Biener Cc: YunQiang Su , gcc-patches@gcc.gnu.org, pinskia@gmail.com, jeffreyalaw@gmail.com, ian@airs.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-6.2 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Richard Biener via Gcc-patches =E4=BA=8E2023=E5= =B9=B47=E6=9C=8819=E6=97=A5=E5=91=A8=E4=B8=89 14:27=E5=86=99=E9=81=93=EF=BC= =9A > > On Wed, 19 Jul 2023, YunQiang Su wrote: > > > PR #104914 > > > > When work with > > int val; > > ((unsigned char*)&val)[3] =3D *buf; > > if (val > 0) ... > > The RTX mode is obtained from REG instead of SUBREG, which make > > D is used instead of . Thus something wrong happens > > on sign-extend default architectures, like MIPS64. > > > > Let's use str_rtx and mode of str_rtx as the parameters for > > store_integral_bit_field if: > > modes of op0 and str_rtx are INT; > > length of op0 is greater than str_rtx. > > > > This patch has been tested on aarch64-linux-gnu, x86_64-linux-gnu, > > mips64el-linux-gnuabi64 without regression. > > I still think you are "fixing" this in the wrong place. The bugzilla > audit trail points to combine and later notes an eventual expansion > issue (but for another testcase/target). > > You have to explain in more detail on what is wrong with the initial > RTL on mips. > In the first RTL file, aka xx.c.256r.expand, the zero_extract RTX is like (insn 10 9 11 2 (set (zero_extract:DI (reg/v:DI 200 [ val ]) (const_int 8 [0x8]) (const_int 0 [0])) (subreg:DI (reg:QI 202) 0)) "../xx.c":4:29 -1 (nil)) Not, all of the REG are in DImode. On MIPS64, it will expand to `DINS` instructions. While in fact here, we expect an SImode operation, due to `val` in C code is `int`. With my patch, the RTX will be like: (insn 10 9 11 2 (set (zero_extract:SI (subreg:SI (reg/v:DI 200 [ val ]) 0) (const_int 8 [0x8]) (const_int 0 [0])) (subreg:SI (reg:QI 202) 0)) "xx.c":4:29 -1 (nil)) So the operation will be SImode, aka `INS` instruction for MIPS64. The problem is based on 2 fact/root cause: 1. MIPS's `INS` instruction will be always to sign-extension, while `DINS` = won't li $7, 0xff li $8, 0 ins $8,$7,24,8 # set the 24-32 bits of $8 to 0xff. The value of $8 will be 0xff ff ff ff ff 00 00 00. li $7, 0xff li $8, 0 dins $8,$7,24,8 # set the 24-32 bits of $8 to 0xff. The value of $8 will be 0x 00 00 00 00 ff 00 00 00. 2. Due to most of MIPS instructions work with 32bit value, aka instructions without `d` as its first char (in fact with few exception), are sign-extens= ion, the MIPS backend just ignore `extendsidi2`, aka RTX (insn 14 13 15 2 (set (reg/v:DI 200 [ val ]) (sign_extend:DI (subreg:SI (reg/v:DI 200 [ val ]) 0))) "xx.c":5:29 = -1 (nil)) > Richard. > > > gcc/ChangeLog: > > PR: 104914. > > * expmed.cc(store_bit_field_1): Pass str_rtx and its mode > > to store_integral_bit_field if the length of op0 is greater > > than str_rtx. > > > > gcc/testsuite/ChangeLog: > > PR: 104914. > > * gcc.target/mips/pr104914.c: New testcase. > > --- > > gcc/expmed.cc | 20 +++++++++++++++++--- > > gcc/testsuite/gcc.target/mips/pr104914.c | 17 +++++++++++++++++ > > 2 files changed, 34 insertions(+), 3 deletions(-) > > create mode 100644 gcc/testsuite/gcc.target/mips/pr104914.c > > > > diff --git a/gcc/expmed.cc b/gcc/expmed.cc > > index fbd4ce2d42f..5531c19e891 100644 > > --- a/gcc/expmed.cc > > +++ b/gcc/expmed.cc > > @@ -850,6 +850,7 @@ store_bit_field_1 (rtx str_rtx, poly_uint64 bitsize= , poly_uint64 bitnum, > > since that case is valid for any mode. The following cases are o= nly > > valid for integral modes. */ > > opt_scalar_int_mode op0_mode =3D int_mode_for_mode (GET_MODE (op0)); > > + opt_scalar_int_mode str_mode =3D int_mode_for_mode (GET_MODE (str_rt= x)); > > scalar_int_mode imode; > > if (!op0_mode.exists (&imode) || imode !=3D GET_MODE (op0)) > > { > > @@ -881,9 +882,22 @@ store_bit_field_1 (rtx str_rtx, poly_uint64 bitsiz= e, poly_uint64 bitnum, > > op0 =3D gen_lowpart (op0_mode.require (), op0); > > } > > > > - return store_integral_bit_field (op0, op0_mode, ibitsize, ibitnum, > > - bitregion_start, bitregion_end, > > - fieldmode, value, reverse, fallback_p)= ; > > + /* If MODEs of str_rtx and op0 are INT, and the length of op0 is gre= ater than > > + str_rtx, it means that str_rtx has a shorter SUBREG: int32 on 64 = mach/ABI > > + is an example. For this case, we should use the mode of SUBREG, = otherwise > > + bad code will generate for sign-extension ports, like MIPS. */ > > + bool use_str_mode =3D false; > > + if (GET_MODE_CLASS (GET_MODE (str_rtx)) =3D=3D MODE_INT > > + && GET_MODE_CLASS (GET_MODE (op0)) =3D=3D MODE_INT > > + && known_gt (GET_MODE_SIZE (GET_MODE (op0)), > > + GET_MODE_SIZE (GET_MODE (str_rtx)))) > > + use_str_mode =3D true; > > + > > + return store_integral_bit_field (use_str_mode ? str_rtx : op0, > > + use_str_mode ? str_mode : op0_mode, > > + ibitsize, ibitnum, bitregion_start, > > + bitregion_end, fieldmode, value, > > + reverse, fallback_p); > > } > > > > /* Subroutine of store_bit_field_1, with the same arguments, except > > diff --git a/gcc/testsuite/gcc.target/mips/pr104914.c b/gcc/testsuite/g= cc.target/mips/pr104914.c > > new file mode 100644 > > index 00000000000..fd6ef6af446 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/mips/pr104914.c > > @@ -0,0 +1,17 @@ > > +/* { dg-do compile } */ > > +/* { dg-options "-march=3Dmips64r2 -mabi=3D64" } */ > > + > > +/* { dg-final { scan-assembler-not "\tdins\t" } } */ > > + > > +NOMIPS16 int test (const unsigned char *buf) > > +{ > > + int val; > > + ((unsigned char*)&val)[0] =3D *buf++; > > + ((unsigned char*)&val)[1] =3D *buf++; > > + ((unsigned char*)&val)[2] =3D *buf++; > > + ((unsigned char*)&val)[3] =3D *buf++; > > + if(val > 0) > > + return 1; > > + else > > + return 0; > > +} > > > > -- > Richard Biener > SUSE Software Solutions Germany GmbH, Frankenstrasse 146, 90461 Nuernberg= , > Germany; GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman; > HRB 36809 (AG Nuernberg) --=20 YunQiang Su