Re: [RFC 1/7] Avoid references to register names in instruction output patterns.

[YunQiang Su <syq@debian.org>]

Dragan Mladjenovic via Gcc-patches <gcc-patches@gcc.gnu.org>
于2021年9月26日周日 下午9:26写道：
>
> This allows us to choose the different names if needed in the future.
>

I try to apply this patch to current gcc, I get this error:
/build/mips-mti-elf/srcs-gcc/gcc/testsuite/gcc.c-torture/compile/20010226-1.c:
In function 'foo':^M
/build/mips-mti-elf/srcs-gcc/gcc/testsuite/gcc.c-torture/compile/20010226-1.c:24:1:
internal compiler error: output_operand: invalid %-code^M
0xa435c4 output_operand_lossage(char const*, ...)^M
        ../../srcs-gcc/gcc/final.c:3235^M
0xa43ec6 output_asm_insn(char const*, rtx_def**)^M
        ../../srcs-gcc/gcc/final.c:3604^M
0xa482c7 output_asm_insn(char const*, rtx_def**)^M
        ../../srcs-gcc/gcc/final.c:3466^M
0xa482c7 final_scan_insn_1^M
        ../../srcs-gcc/gcc/final.c:2894^M
0xa485bb final_scan_insn(rtx_insn*, _IO_FILE*, int, int, int*)^M
        ../../srcs-gcc/gcc/final.c:2940^M
0xa486a6 final_1^M
        ../../srcs-gcc/gcc/final.c:1997^M
0xa49262 rest_of_handle_final^M
        ../../srcs-gcc/gcc/final.c:4285^M
0xa49262 execute^M
        ../../srcs-gcc/gcc/final.c:4363^M
Please submit a full bug report,^M
with preprocessed source if appropriate.^M
Please include the complete backtrace with any bug report.^M
See <https://gcc.gnu.org/bugs/> for instructions.^M
compiler exited with status 1

> gcc/ChangeLog:
>
>         * config/mips/mips.c (mips_print_operand_punctuation):
>         Handle '&' punctuation.
>         (mips_output_probe_stack_range): Use '%.' instead of $0.
>         * config/mips/mips.h (GLOBAL_POINTER_REGNUM): Move to ...
>         * config/mips/mips.md (GLOBAL_POINTER_REGNUM): ... here.
>         (trap, *conditional_trap_reg<mode>, *msac, *muls,
>         *muls<u>_di, <u>msubsidi4): Use '%.' instead of $0.
>         (clear_hazard_<mode>): Use '%&' instead of $31.
> ---
>  gcc/config/mips/mips.c  |  9 +++++++--
>  gcc/config/mips/mips.h  |  4 ----
>  gcc/config/mips/mips.md | 17 +++++++++--------
>  3 files changed, 16 insertions(+), 14 deletions(-)
>  3 files changed, 16 insertions(+), 14 deletions(-)
>
> diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
> index ce60c5500b7..ab63575eb26 100644
> --- a/gcc/config/mips/mips.c
> +++ b/gcc/config/mips/mips.c
> @@ -8816,6 +8816,7 @@ mips_pop_asm_switch (struct mips_asm_switch *asm_switch)
>     '^' Print the name of the pic call-through register (t9 or $25).
>     '+' Print the name of the gp register (usually gp or $28).
>     '$' Print the name of the stack pointer register (sp or $29).
> +   '&' Print the name of the return register (ra or $31).
>     ':'  Print "c" to use the compact version if the delay slot is a nop.
>     '!'  Print "s" to use the short version if the delay slot contains a
>         16-bit instruction.
> @@ -8902,6 +8903,10 @@ mips_print_operand_punctuation (FILE *file, int ch)
>        fputs (reg_names[STACK_POINTER_REGNUM], file);
>        break;
>
> +    case '&':
> +      fputs (reg_names[RETURN_ADDR_REGNUM], file);
> +      break;
> +
>      case ':':
>        /* When final_sequence is 0, the delay slot will be a nop.  We can
>          use the compact version where available.  The %: formatter will
> @@ -12133,9 +12138,9 @@ mips_output_probe_stack_range (rtx reg1, rtx reg2)
>    strcpy (tmp, "%(%<bne\t%0,%1,");
>    output_asm_insn (strcat (tmp, &loop_lab[1]), xops);
>    if (TARGET_64BIT)
> -    output_asm_insn ("sd\t$0,0(%0)%)", xops);
> +    output_asm_insn ("sd\t%.,0(%0)%)", xops);
>    else
> -    output_asm_insn ("sw\t$0,0(%0)%)", xops);
> +    output_asm_insn ("sw\t%.,0(%0)%)", xops);
>

I guess the problem is due to this.

>    return "";
>  }
> diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
> index f4e30ba3fdb..a44ccada0bc 100644
> --- a/gcc/config/mips/mips.h
> +++ b/gcc/config/mips/mips.h
> @@ -2064,10 +2064,6 @@ FP_ASM_SPEC "\
>     function address than to call an address kept in a register.  */
>  #define NO_FUNCTION_CSE 1
>
> -/* The ABI-defined global pointer.  Sometimes we use a different
> -   register in leaf functions: see PIC_OFFSET_TABLE_REGNUM.  */
> -#define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
> -
>  /* We normally use $28 as the global pointer.  However, when generating
>     n32/64 PIC, it is better for leaf functions to use a call-clobbered
>     register instead.  They can then avoid saving and restoring $28
> diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
> index dee71dc1fb0..1c8b3b98b20 100644
> --- a/gcc/config/mips/mips.md
> +++ b/gcc/config/mips/mips.md
> @@ -167,6 +167,7 @@
>     (GET_FCSR_REGNUM            2)
>     (SET_FCSR_REGNUM            4)
>     (PIC_FUNCTION_ADDR_REGNUM   25)
> +   (GLOBAL_POINTER_REGNUM      28)
>     (RETURN_ADDR_REGNUM         31)
>     (CPRESTORE_SLOT_REGNUM      76)
>     (GOT_VERSION_REGNUM         79)
> @@ -1205,7 +1206,7 @@
>    ""
>  {
>    if (ISA_HAS_COND_TRAP)
> -    return "teq\t$0,$0";
> +    return "teq\t%.,%.";
>    else if (TARGET_MIPS16)
>      return "break 0";
>    else
> @@ -1230,7 +1231,7 @@
>                                  (match_operand:GPR 2 "reg_or_0_operand" "dJ")])
>             (const_int 0))]
>    "ISA_HAS_COND_TRAP && !ISA_HAS_COND_TRAPI"
> -  "t%C0\t%z1,%2"
> +  "t%C0\t%z1,%z2"
>    [(set_attr "type" "trap")])
>
>  (define_insn "*conditional_trap<mode>"
> @@ -1860,7 +1861,7 @@
>    else if (TARGET_MIPS5500)
>      return "msub\t%2,%3";
>    else
> -    return "msac\t$0,%2,%3";
> +    return "msac\t%.,%2,%3";
>  }
>    [(set_attr "type"     "imadd")
>     (set_attr "accum_in"        "1")
> @@ -2060,7 +2061,7 @@
>     (clobber (match_scratch:SI 3 "=X,l"))]
>    "ISA_HAS_MULS"
>    "@
> -   muls\t$0,%1,%2
> +   muls\t%.,%1,%2
>     muls\t%0,%1,%2"
>    [(set_attr "type"     "imul,imul3")
>     (set_attr "mode"     "SI")])
> @@ -2243,7 +2244,7 @@
>           (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
>           (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
>    "!TARGET_64BIT && ISA_HAS_MULS"
> -  "muls<u>\t$0,%1,%2"
> +  "muls<u>\t%.,%1,%2"
>    [(set_attr "type" "imul")
>     (set_attr "mode" "SI")])
>
> @@ -2268,7 +2269,7 @@
>    else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
>      return "msub<u>\t%1,%2";
>    else
> -    return "msac<u>\t$0,%1,%2";
> +    return "msac<u>\t%.,%1,%2";
>  }
>    [(set_attr "type" "imadd")
>     (set_attr "accum_in"        "3")
> @@ -5622,8 +5623,8 @@
>  {
>    return "%(%<bal\t1f\n"
>           "\tnop\n"
> -         "1:\t<d>addiu\t$31,$31,12\n"
> -         "\tjr.hb\t$31\n"
> +         "1:\t<d>addiu\t%&,%&,12\n"
> +         "\tjr.hb\t%&\n"
>           "\tnop%>%)";
>  }