From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pg1-x52b.google.com (mail-pg1-x52b.google.com [IPv6:2607:f8b0:4864:20::52b]) by sourceware.org (Postfix) with ESMTPS id 5DDBE384F009 for ; Wed, 5 May 2021 14:09:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 5DDBE384F009 Received: by mail-pg1-x52b.google.com with SMTP id m124so1841575pgm.13 for ; Wed, 05 May 2021 07:09:36 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=chU4O0/G7Fs+S4+6Ntyc6h5t3OfdkoIzXzsY/TJ7Efw=; b=kZN8Ec+EbVyUlVkww3g32MbLUi/s3b1IhiMaCNawH/DjF2kt8Inokr84MOmlJqoQe9 xzuiGobYhJv0406gF85HOzYy4lRDMOzabEhLKSh9XLLTIfAHqO58W6pVj5sgRuAJIQ/4 krjisDy+rY1nA5vwY7tnwBYFAlj1NkOWmsj54/2vE5zE2GG/W7AFGMyL7YsqAD0Dm+gx t17vmL9xfC63xflyjxUqtmLIS5JiI04oDiT6+6GnJnu84rzhpNQmU2zDr2WGCub0Zc8F R/24maxcIBnP7Ll1UU3FeiHq2UoWAVPD44r7GnEpONp6u4vTmOYOqpqFEqIyCJOBW2pL UUXQ== X-Gm-Message-State: AOAM531tWi9f+NbKQgJkCnlO9FEpQJhFkDwd0+iZku9ELBLWrF+dXWvF a93aMy4E5EVHKNSkcTqxtmUYAu5kutFHM/O0EgTOpY6Kjpx+uQ== X-Google-Smtp-Source: ABdhPJx0z7+ilDqXF6tGgCOsvkPikzU89RimRqgrB6M3Z0OLSuDKbWJSHhHVRZ0+zAu4kjQzK7hw/sB+NpY5fwQL4I4= X-Received: by 2002:a63:f90d:: with SMTP id h13mr28764890pgi.18.1620223775111; Wed, 05 May 2021 07:09:35 -0700 (PDT) MIME-Version: 1.0 References: <1619791790-628-1-git-send-email-christophe.lyon@linaro.org> <1619791790-628-7-git-send-email-christophe.lyon@linaro.org> <12b710c0-f646-d44e-c18d-6a550140911b@arm.com> In-Reply-To: From: Christophe Lyon Date: Wed, 5 May 2021 16:09:24 +0200 Message-ID: Subject: Re: [PATCH 7/9] arm: Auto-vectorization for MVE: add __fp16 support to VCMP To: "Andre Vieira (lists)" Cc: "gcc-patches@gcc.gnu.org" Content-Type: multipart/mixed; boundary="00000000000092aba105c195be77" X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 05 May 2021 14:09:39 -0000 --00000000000092aba105c195be77 Content-Type: text/plain; charset="UTF-8" On Tue, 4 May 2021 at 19:03, Christophe Lyon wrote: > > On Tue, 4 May 2021 at 15:43, Christophe Lyon wrote: > > > > On Tue, 4 May 2021 at 13:48, Andre Vieira (lists) > > wrote: > > > > > > It would be good to also add tests for NEON as you also enable auto-vec > > > for it. I checked and I do think the necessary 'neon_vc' patterns exist > > > for 'VH', so we should be OK there. > > > > > > > Actually since I posted the patch series, I've noticed a regression in > > armv8_2-fp16-arith-1.c, because we now vectorize all the float16x[48]_t loops, > > but we lose the fact that some FP comparisons can throw exceptions. > > > > I'll have to revisit this patch. > > Actually it looks like my patch does the right thing: we now vectorize > appropriately, given that the testcase is compiled with -ffast-math. > I need to update the testcase, though. > Here is a new version, with armv8_2-fp16-arith-1.c updated to take into account the new vectorization. Christophe > > > > Thanks, > > > > Christophe > > > > > On 30/04/2021 15:09, Christophe Lyon via Gcc-patches wrote: > > > > This patch adds __fp16 support to the previous patch that added vcmp > > > > support with MVE. For this we update existing expanders to use VDQWH > > > > iterator, and add a new expander vcond. In the > > > > process we need to create suitable iterators, and update v_cmp_result > > > > as needed. > > > > > > > > 2021-04-26 Christophe Lyon > > > > > > > > gcc/ > > > > * config/arm/iterators.md (V16): New iterator. > > > > (VH_cvtto): New iterator. > > > > (v_cmp_result): Added V4HF and V8HF support. > > > > * config/arm/vec-common.md (vec_cmp): Use VDQWH. > > > > (vcond): Likewise. > > > > (vcond_mask_): Likewise. > > > > (vcond): New expander. > > > > > > > > gcc/testsuite/ > > > > * gcc.target/arm/simd/mve-compare-3.c: New test with GCC vectors. > > > > * gcc.target/arm/simd/mve-vcmp-f16.c: New test for > > > > auto-vectorization. > > > > --- > > > > gcc/config/arm/iterators.md | 6 ++++ > > > > gcc/config/arm/vec-common.md | 40 ++++++++++++++++------- > > > > gcc/testsuite/gcc.target/arm/simd/mve-compare-3.c | 38 +++++++++++++++++++++ > > > > gcc/testsuite/gcc.target/arm/simd/mve-vcmp-f16.c | 30 +++++++++++++++++ > > > > 4 files changed, 102 insertions(+), 12 deletions(-) > > > > create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-compare-3.c > > > > create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-vcmp-f16.c > > > > > > > > diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md > > > > index a128465..3042baf 100644 > > > > --- a/gcc/config/arm/iterators.md > > > > +++ b/gcc/config/arm/iterators.md > > > > @@ -231,6 +231,9 @@ (define_mode_iterator VU [V16QI V8HI V4SI]) > > > > ;; Vector modes for 16-bit floating-point support. > > > > (define_mode_iterator VH [V8HF V4HF]) > > > > > > > > +;; Modes with 16-bit elements only. > > > > +(define_mode_iterator V16 [V4HI V4HF V8HI V8HF]) > > > > + > > > > ;; 16-bit floating-point vector modes suitable for moving (includes BFmode). > > > > (define_mode_iterator VHFBF [V8HF V4HF V4BF V8BF]) > > > > > > > > @@ -571,6 +574,8 @@ (define_mode_attr V_cvtto [(V2SI "v2sf") (V2SF "v2si") > > > > ;; (Opposite) mode to convert to/from for vector-half mode conversions. > > > > (define_mode_attr VH_CVTTO [(V4HI "V4HF") (V4HF "V4HI") > > > > (V8HI "V8HF") (V8HF "V8HI")]) > > > > +(define_mode_attr VH_cvtto [(V4HI "v4hf") (V4HF "v4hi") > > > > + (V8HI "v8hf") (V8HF "v8hi")]) > > > > > > > > ;; Define element mode for each vector mode. > > > > (define_mode_attr V_elem [(V8QI "QI") (V16QI "QI") > > > > @@ -720,6 +725,7 @@ (define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI") > > > > (define_mode_attr v_cmp_result [(V8QI "v8qi") (V16QI "v16qi") > > > > (V4HI "v4hi") (V8HI "v8hi") > > > > (V2SI "v2si") (V4SI "v4si") > > > > + (V4HF "v4hi") (V8HF "v8hi") > > > > (DI "di") (V2DI "v2di") > > > > (V2SF "v2si") (V4SF "v4si")]) > > > > > > > > diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md > > > > index 034b48b..3fd341c 100644 > > > > --- a/gcc/config/arm/vec-common.md > > > > +++ b/gcc/config/arm/vec-common.md > > > > @@ -366,8 +366,8 @@ (define_expand "vlshr3" > > > > (define_expand "vec_cmp" > > > > [(set (match_operand: 0 "s_register_operand") > > > > (match_operator: 1 "comparison_operator" > > > > - [(match_operand:VDQW 2 "s_register_operand") > > > > - (match_operand:VDQW 3 "reg_or_zero_operand")]))] > > > > + [(match_operand:VDQWH 2 "s_register_operand") > > > > + (match_operand:VDQWH 3 "reg_or_zero_operand")]))] > > > > "ARM_HAVE__ARITH > > > > && !TARGET_REALLY_IWMMXT > > > > && (! || flag_unsafe_math_optimizations)" > > > > @@ -399,13 +399,13 @@ (define_expand "vec_cmpu" > > > > ;; element-wise. > > > > > > > > (define_expand "vcond" > > > > - [(set (match_operand:VDQW 0 "s_register_operand") > > > > - (if_then_else:VDQW > > > > + [(set (match_operand:VDQWH 0 "s_register_operand") > > > > + (if_then_else:VDQWH > > > > (match_operator 3 "comparison_operator" > > > > - [(match_operand:VDQW 4 "s_register_operand") > > > > - (match_operand:VDQW 5 "reg_or_zero_operand")]) > > > > - (match_operand:VDQW 1 "s_register_operand") > > > > - (match_operand:VDQW 2 "s_register_operand")))] > > > > + [(match_operand:VDQWH 4 "s_register_operand") > > > > + (match_operand:VDQWH 5 "reg_or_zero_operand")]) > > > > + (match_operand:VDQWH 1 "s_register_operand") > > > > + (match_operand:VDQWH 2 "s_register_operand")))] > > > > "ARM_HAVE__ARITH > > > > && !TARGET_REALLY_IWMMXT > > > > && (! || flag_unsafe_math_optimizations)" > > > > @@ -430,6 +430,22 @@ (define_expand "vcond" > > > > DONE; > > > > }) > > > > > > > > +(define_expand "vcond" > > > > + [(set (match_operand: 0 "s_register_operand") > > > > + (if_then_else: > > > > + (match_operator 3 "comparison_operator" > > > > + [(match_operand:V16 4 "s_register_operand") > > > > + (match_operand:V16 5 "reg_or_zero_operand")]) > > > > + (match_operand: 1 "s_register_operand") > > > > + (match_operand: 2 "s_register_operand")))] > > > > + "ARM_HAVE__ARITH > > > > + && !TARGET_REALLY_IWMMXT > > > > + && (! || flag_unsafe_math_optimizations)" > > > > +{ > > > > + arm_expand_vcond (operands, mode); > > > > + DONE; > > > > +}) > > > > + > > > > (define_expand "vcondu" > > > > [(set (match_operand:VDQW 0 "s_register_operand") > > > > (if_then_else:VDQW > > > > @@ -446,11 +462,11 @@ (define_expand "vcondu" > > > > }) > > > > > > > > (define_expand "vcond_mask_" > > > > - [(set (match_operand:VDQW 0 "s_register_operand") > > > > - (if_then_else:VDQW > > > > + [(set (match_operand:VDQWH 0 "s_register_operand") > > > > + (if_then_else:VDQWH > > > > (match_operand: 3 "s_register_operand") > > > > - (match_operand:VDQW 1 "s_register_operand") > > > > - (match_operand:VDQW 2 "s_register_operand")))] > > > > + (match_operand:VDQWH 1 "s_register_operand") > > > > + (match_operand:VDQWH 2 "s_register_operand")))] > > > > "ARM_HAVE__ARITH > > > > && !TARGET_REALLY_IWMMXT" > > > > { > > > > diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-compare-3.c b/gcc/testsuite/gcc.target/arm/simd/mve-compare-3.c > > > > new file mode 100644 > > > > index 0000000..76f81e8 > > > > --- /dev/null > > > > +++ b/gcc/testsuite/gcc.target/arm/simd/mve-compare-3.c > > > > @@ -0,0 +1,38 @@ > > > > +/* { dg-do assemble } */ > > > > +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > > > > +/* { dg-add-options arm_v8_1m_mve_fp } */ > > > > +/* { dg-additional-options "-O3 -funsafe-math-optimizations" } */ > > > > + > > > > +/* float 16 tests. */ > > > > + > > > > +#ifndef ELEM_TYPE > > > > +#define ELEM_TYPE __fp16 > > > > +#endif > > > > +#ifndef INT_ELEM_TYPE > > > > +#define INT_ELEM_TYPE __INT16_TYPE__ > > > > +#endif > > > > + > > > > +#define COMPARE(NAME, OP) \ > > > > + int_vec \ > > > > + cmp_##NAME##_reg (vec a, vec b) \ > > > > + { \ > > > > + return a OP b; \ > > > > + } > > > > + > > > > +typedef INT_ELEM_TYPE int_vec __attribute__((vector_size(16))); > > > > +typedef ELEM_TYPE vec __attribute__((vector_size(16))); > > > > + > > > > +COMPARE (eq, ==) > > > > +COMPARE (ne, !=) > > > > +COMPARE (lt, <) > > > > +COMPARE (le, <=) > > > > +COMPARE (gt, >) > > > > +COMPARE (ge, >=) > > > > + > > > > +/* eq, ne, lt, le, gt, ge. > > > > +/* { dg-final { scan-assembler-times {\tvcmp.f16\teq, q[0-9]+, q[0-9]+\n} 1 } } */ > > > > +/* { dg-final { scan-assembler-times {\tvcmp.f16\tne, q[0-9]+, q[0-9]+\n} 1 } } */ > > > > +/* { dg-final { scan-assembler-times {\tvcmp.f16\tlt, q[0-9]+, q[0-9]+\n} 1 } } */ > > > > +/* { dg-final { scan-assembler-times {\tvcmp.f16\tle, q[0-9]+, q[0-9]+\n} 1 } } */ > > > > +/* { dg-final { scan-assembler-times {\tvcmp.f16\tgt, q[0-9]+, q[0-9]+\n} 1 } } */ > > > > +/* { dg-final { scan-assembler-times {\tvcmp.f16\tge, q[0-9]+, q[0-9]+\n} 1 } } */ > > > > diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vcmp-f16.c b/gcc/testsuite/gcc.target/arm/simd/mve-vcmp-f16.c > > > > new file mode 100644 > > > > index 0000000..dbae2d1 > > > > --- /dev/null > > > > +++ b/gcc/testsuite/gcc.target/arm/simd/mve-vcmp-f16.c > > > > @@ -0,0 +1,30 @@ > > > > +/* { dg-do assemble } */ > > > > +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > > > > +/* { dg-add-options arm_v8_1m_mve_fp } */ > > > > +/* { dg-additional-options "-O3 -funsafe-math-optimizations" } */ > > > > + > > > > +#include > > > > + > > > > +#define NB 8 > > > > + > > > > +#define FUNC(OP, NAME) \ > > > > + void test_ ## NAME ##_f (__fp16 * __restrict__ dest, __fp16 *a, __fp16 *b) { \ > > > > + int i; \ > > > > + for (i=0; i > > > + dest[i] = a[i] OP b[i]; \ > > > > + } \ > > > > + } > > > > + > > > > +FUNC(==, vcmpeq) > > > > +FUNC(!=, vcmpne) > > > > +FUNC(<, vcmplt) > > > > +FUNC(<=, vcmple) > > > > +FUNC(>, vcmpgt) > > > > +FUNC(>=, vcmpge) > > > > + > > > > +/* { dg-final { scan-assembler-times {\tvcmp.f16\teq, q[0-9]+, q[0-9]+\n} 1 } } */ > > > > +/* { dg-final { scan-assembler-times {\tvcmp.f16\tne, q[0-9]+, q[0-9]+\n} 1 } } */ > > > > +/* { dg-final { scan-assembler-times {\tvcmp.f16\tlt, q[0-9]+, q[0-9]+\n} 1 } } */ > > > > +/* { dg-final { scan-assembler-times {\tvcmp.f16\tle, q[0-9]+, q[0-9]+\n} 1 } } */ > > > > +/* { dg-final { scan-assembler-times {\tvcmp.f16\tgt, q[0-9]+, q[0-9]+\n} 1 } } */ > > > > +/* { dg-final { scan-assembler-times {\tvcmp.f16\tge, q[0-9]+, q[0-9]+\n} 1 } } */ --00000000000092aba105c195be77 Content-Type: text/x-patch; charset="US-ASCII"; name="v2-0007-arm-Auto-vectorization-for-MVE-add-__fp16-support.patch" Content-Disposition: attachment; filename="v2-0007-arm-Auto-vectorization-for-MVE-add-__fp16-support.patch" Content-Transfer-Encoding: base64 Content-ID: X-Attachment-Id: f_kobjdenu0 RnJvbSAwZmQ0MmUzMmQ3NmI0NTViNmMxYTQ5ZGNjMjQ5MDJmODEwZDlkNDgyIE1vbiBTZXAgMTcg MDA6MDA6MDAgMjAwMQpGcm9tOiBDaHJpc3RvcGhlIEx5b24gPGNocmlzdG9waGUubHlvbkBsaW5h cm8ub3JnPgpEYXRlOiBGcmksIDIzIEFwciAyMDIxIDE0OjE3OjEwICswMDAwClN1YmplY3Q6IFtQ QVRDSCB2MiA3LzldIGFybTogQXV0by12ZWN0b3JpemF0aW9uIGZvciBNVkU6IGFkZCBfX2ZwMTYg c3VwcG9ydCB0bwogVkNNUAoKVGhpcyBwYXRjaCBhZGRzIF9fZnAxNiBzdXBwb3J0IHRvIHRoZSBw cmV2aW91cyBwYXRjaCB0aGF0IGFkZGVkIHZjbXAKc3VwcG9ydCB3aXRoIE1WRS4gRm9yIHRoaXMg d2UgdXBkYXRlIGV4aXN0aW5nIGV4cGFuZGVycyB0byB1c2UgVkRRV0gKaXRlcmF0b3IsIGFuZCBh ZGQgYSBuZXcgZXhwYW5kZXIgdmNvbmQ8VkhfY3Z0dG8+PG1vZGU+LiAgSW4gdGhlCnByb2Nlc3Mg d2UgbmVlZCB0byBjcmVhdGUgc3VpdGFibGUgaXRlcmF0b3JzLCBhbmQgdXBkYXRlIHZfY21wX3Jl c3VsdAphcyBuZWVkZWQuCgoyMDIxLTA0LTI2ICBDaHJpc3RvcGhlIEx5b24gIDxjaHJpc3RvcGhl Lmx5b25AbGluYXJvLm9yZz4KCglnY2MvCgkqIGNvbmZpZy9hcm0vaXRlcmF0b3JzLm1kIChWMTYp OiBOZXcgaXRlcmF0b3IuCgkoVkhfY3Z0dG8pOiBOZXcgaXRlcmF0b3IuCgkodl9jbXBfcmVzdWx0 KTogQWRkZWQgVjRIRiBhbmQgVjhIRiBzdXBwb3J0LgoJKiBjb25maWcvYXJtL3ZlYy1jb21tb24u bWQgKHZlY19jbXA8bW9kZT48dl9jbXBfcmVzdWx0Pik6IFVzZSBWRFFXSC4KCSh2Y29uZDxtb2Rl Pjxtb2RlPik6IExpa2V3aXNlLgoJKHZjb25kX21hc2tfPG1vZGU+PHZfY21wX3Jlc3VsdD4pOiBM aWtld2lzZS4KCSh2Y29uZDxWSF9jdnR0bz48bW9kZT4pOiBOZXcgZXhwYW5kZXIuCgoJZ2NjL3Rl c3RzdWl0ZS8KCSogZ2NjLnRhcmdldC9hcm0vc2ltZC9tdmUtY29tcGFyZS0zLmM6IE5ldyB0ZXN0 IHdpdGggR0NDIHZlY3RvcnMuCgkqIGdjYy50YXJnZXQvYXJtL3NpbWQvbXZlLXZjbXAtZjE2LmM6 IE5ldyB0ZXN0IGZvcgoJYXV0by12ZWN0b3JpemF0aW9uLgoJKiBnY2MudGFyZ2V0L2FybS9hcm12 OF8yLWZwMTYtYXJpdGgtMS5jOiBBZGp1c3Qgc2luY2Ugd2Ugbm93Cgl2ZWN0b3JpemUgZmxvYXQx Nl90IHZlY3RvcnMuCi0tLQogZ2NjL2NvbmZpZy9hcm0vaXRlcmF0b3JzLm1kICAgICAgICAgICAg ICAgICAgICAgICAgfCAgNiArKysrCiBnY2MvY29uZmlnL2FybS92ZWMtY29tbW9uLm1kICAgICAg ICAgICAgICAgICAgICAgICB8IDQwICsrKysrKysrKysrKysrKy0tLS0tLS0KIC4uLi9nY2MudGFy Z2V0L2FybS9hcm12OF8yLWZwMTYtYXJpdGgtMS5jICAgICAgICAgIHwgMTYgKysrKysrKy0tCiBn Y2MvdGVzdHN1aXRlL2djYy50YXJnZXQvYXJtL3NpbWQvbXZlLWNvbXBhcmUtMy5jICB8IDM4ICsr KysrKysrKysrKysrKysrKysrCiBnY2MvdGVzdHN1aXRlL2djYy50YXJnZXQvYXJtL3NpbWQvbXZl LXZjbXAtZjE2LmMgICB8IDMwICsrKysrKysrKysrKysrKysKIDUgZmlsZXMgY2hhbmdlZCwgMTE2 IGluc2VydGlvbnMoKyksIDE0IGRlbGV0aW9ucygtKQogY3JlYXRlIG1vZGUgMTAwNjQ0IGdjYy90 ZXN0c3VpdGUvZ2NjLnRhcmdldC9hcm0vc2ltZC9tdmUtY29tcGFyZS0zLmMKIGNyZWF0ZSBtb2Rl IDEwMDY0NCBnY2MvdGVzdHN1aXRlL2djYy50YXJnZXQvYXJtL3NpbWQvbXZlLXZjbXAtZjE2LmMK CmRpZmYgLS1naXQgYS9nY2MvY29uZmlnL2FybS9pdGVyYXRvcnMubWQgYi9nY2MvY29uZmlnL2Fy bS9pdGVyYXRvcnMubWQKaW5kZXggYTEyODQ2NS4uMzA0MmJhZiAxMDA2NDQKLS0tIGEvZ2NjL2Nv bmZpZy9hcm0vaXRlcmF0b3JzLm1kCisrKyBiL2djYy9jb25maWcvYXJtL2l0ZXJhdG9ycy5tZApA QCAtMjMxLDYgKzIzMSw5IEBAIChkZWZpbmVfbW9kZV9pdGVyYXRvciBWVSBbVjE2UUkgVjhISSBW NFNJXSkKIDs7IFZlY3RvciBtb2RlcyBmb3IgMTYtYml0IGZsb2F0aW5nLXBvaW50IHN1cHBvcnQu CiAoZGVmaW5lX21vZGVfaXRlcmF0b3IgVkggW1Y4SEYgVjRIRl0pCiAKKzs7IE1vZGVzIHdpdGgg MTYtYml0IGVsZW1lbnRzIG9ubHkuCisoZGVmaW5lX21vZGVfaXRlcmF0b3IgVjE2IFtWNEhJIFY0 SEYgVjhISSBWOEhGXSkKKwogOzsgMTYtYml0IGZsb2F0aW5nLXBvaW50IHZlY3RvciBtb2RlcyBz dWl0YWJsZSBmb3IgbW92aW5nIChpbmNsdWRlcyBCRm1vZGUpLgogKGRlZmluZV9tb2RlX2l0ZXJh dG9yIFZIRkJGIFtWOEhGIFY0SEYgVjRCRiBWOEJGXSkKIApAQCAtNTcxLDYgKzU3NCw4IEBAIChk ZWZpbmVfbW9kZV9hdHRyIFZfY3Z0dG8gWyhWMlNJICJ2MnNmIikgKFYyU0YgInYyc2kiKQogOzsg KE9wcG9zaXRlKSBtb2RlIHRvIGNvbnZlcnQgdG8vZnJvbSBmb3IgdmVjdG9yLWhhbGYgbW9kZSBj b252ZXJzaW9ucy4KIChkZWZpbmVfbW9kZV9hdHRyIFZIX0NWVFRPIFsoVjRISSAiVjRIRiIpIChW NEhGICJWNEhJIikKIAkJCSAgICAoVjhISSAiVjhIRiIpIChWOEhGICJWOEhJIildKQorKGRlZmlu ZV9tb2RlX2F0dHIgVkhfY3Z0dG8gWyhWNEhJICJ2NGhmIikgKFY0SEYgInY0aGkiKQorCQkJICAg IChWOEhJICJ2OGhmIikgKFY4SEYgInY4aGkiKV0pCiAKIDs7IERlZmluZSBlbGVtZW50IG1vZGUg Zm9yIGVhY2ggdmVjdG9yIG1vZGUuCiAoZGVmaW5lX21vZGVfYXR0ciBWX2VsZW0gWyhWOFFJICJR SSIpIChWMTZRSSAiUUkiKQpAQCAtNzIwLDYgKzcyNSw3IEBAIChkZWZpbmVfbW9kZV9hdHRyIFZf Y21wX3Jlc3VsdCBbKFY4UUkgIlY4UUkiKSAoVjE2UUkgIlYxNlFJIikKIChkZWZpbmVfbW9kZV9h dHRyIHZfY21wX3Jlc3VsdCBbKFY4UUkgInY4cWkiKSAoVjE2UUkgInYxNnFpIikKIAkJCQkoVjRI SSAidjRoaSIpIChWOEhJICAidjhoaSIpCiAJCQkJKFYyU0kgInYyc2kiKSAoVjRTSSAgInY0c2ki KQorCQkJCShWNEhGICJ2NGhpIikgKFY4SEYgICJ2OGhpIikKIAkJCQkoREkgICAiZGkiKSAgIChW MkRJICAidjJkaSIpCiAJCQkJKFYyU0YgInYyc2kiKSAoVjRTRiAgInY0c2kiKV0pCiAKZGlmZiAt LWdpdCBhL2djYy9jb25maWcvYXJtL3ZlYy1jb21tb24ubWQgYi9nY2MvY29uZmlnL2FybS92ZWMt Y29tbW9uLm1kCmluZGV4IDQ0ODczMWYuLjI2NWZhNDAgMTAwNjQ0Ci0tLSBhL2djYy9jb25maWcv YXJtL3ZlYy1jb21tb24ubWQKKysrIGIvZ2NjL2NvbmZpZy9hcm0vdmVjLWNvbW1vbi5tZApAQCAt MzY2LDggKzM2Niw4IEBAIChkZWZpbmVfZXhwYW5kICJ2bHNocjxtb2RlPjMiCiAoZGVmaW5lX2V4 cGFuZCAidmVjX2NtcDxtb2RlPjx2X2NtcF9yZXN1bHQ+IgogICBbKHNldCAobWF0Y2hfb3BlcmFu ZDo8Vl9jbXBfcmVzdWx0PiAwICJzX3JlZ2lzdGVyX29wZXJhbmQiKQogCShtYXRjaF9vcGVyYXRv cjo8Vl9jbXBfcmVzdWx0PiAxICJjb21wYXJpc29uX29wZXJhdG9yIgotCSAgWyhtYXRjaF9vcGVy YW5kOlZEUVcgMiAic19yZWdpc3Rlcl9vcGVyYW5kIikKLQkgICAobWF0Y2hfb3BlcmFuZDpWRFFX IDMgInJlZ19vcl96ZXJvX29wZXJhbmQiKV0pKV0KKwkgIFsobWF0Y2hfb3BlcmFuZDpWRFFXSCAy ICJzX3JlZ2lzdGVyX29wZXJhbmQiKQorCSAgIChtYXRjaF9vcGVyYW5kOlZEUVdIIDMgInJlZ19v cl96ZXJvX29wZXJhbmQiKV0pKV0KICAgIkFSTV9IQVZFXzxNT0RFPl9BUklUSAogICAgJiYgIVRB UkdFVF9SRUFMTFlfSVdNTVhUCiAgICAmJiAoITxJc19mbG9hdF9tb2RlPiB8fCBmbGFnX3Vuc2Fm ZV9tYXRoX29wdGltaXphdGlvbnMpIgpAQCAtMzk5LDEzICszOTksMTMgQEAgKGRlZmluZV9leHBh bmQgInZlY19jbXB1PG1vZGU+PG1vZGU+IgogOzsgZWxlbWVudC13aXNlLgogCiAoZGVmaW5lX2V4 cGFuZCAidmNvbmQ8bW9kZT48bW9kZT4iCi0gIFsoc2V0IChtYXRjaF9vcGVyYW5kOlZEUVcgMCAi c19yZWdpc3Rlcl9vcGVyYW5kIikKLQkoaWZfdGhlbl9lbHNlOlZEUVcKKyAgWyhzZXQgKG1hdGNo X29wZXJhbmQ6VkRRV0ggMCAic19yZWdpc3Rlcl9vcGVyYW5kIikKKwkoaWZfdGhlbl9lbHNlOlZE UVdICiAJICAobWF0Y2hfb3BlcmF0b3IgMyAiY29tcGFyaXNvbl9vcGVyYXRvciIKLQkgICAgWyht YXRjaF9vcGVyYW5kOlZEUVcgNCAic19yZWdpc3Rlcl9vcGVyYW5kIikKLQkgICAgIChtYXRjaF9v cGVyYW5kOlZEUVcgNSAicmVnX29yX3plcm9fb3BlcmFuZCIpXSkKLQkgIChtYXRjaF9vcGVyYW5k OlZEUVcgMSAic19yZWdpc3Rlcl9vcGVyYW5kIikKLQkgIChtYXRjaF9vcGVyYW5kOlZEUVcgMiAi c19yZWdpc3Rlcl9vcGVyYW5kIikpKV0KKwkgICAgWyhtYXRjaF9vcGVyYW5kOlZEUVdIIDQgInNf cmVnaXN0ZXJfb3BlcmFuZCIpCisJICAgICAobWF0Y2hfb3BlcmFuZDpWRFFXSCA1ICJyZWdfb3Jf emVyb19vcGVyYW5kIildKQorCSAgKG1hdGNoX29wZXJhbmQ6VkRRV0ggMSAic19yZWdpc3Rlcl9v cGVyYW5kIikKKwkgIChtYXRjaF9vcGVyYW5kOlZEUVdIIDIgInNfcmVnaXN0ZXJfb3BlcmFuZCIp KSldCiAgICJBUk1fSEFWRV88TU9ERT5fQVJJVEgKICAgICYmICFUQVJHRVRfUkVBTExZX0lXTU1Y VAogICAgJiYgKCE8SXNfZmxvYXRfbW9kZT4gfHwgZmxhZ191bnNhZmVfbWF0aF9vcHRpbWl6YXRp b25zKSIKQEAgLTQzMCw2ICs0MzAsMjIgQEAgKGRlZmluZV9leHBhbmQgInZjb25kPFZfY3Z0dG8+ PG1vZGU+IgogICBET05FOwogfSkKIAorKGRlZmluZV9leHBhbmQgInZjb25kPFZIX2N2dHRvPjxt b2RlPiIKKyAgWyhzZXQgKG1hdGNoX29wZXJhbmQ6PFZIX0NWVFRPPiAwICJzX3JlZ2lzdGVyX29w ZXJhbmQiKQorCShpZl90aGVuX2Vsc2U6PFZIX0NWVFRPPgorCSAgKG1hdGNoX29wZXJhdG9yIDMg ImNvbXBhcmlzb25fb3BlcmF0b3IiCisJICAgIFsobWF0Y2hfb3BlcmFuZDpWMTYgNCAic19yZWdp c3Rlcl9vcGVyYW5kIikKKwkgICAgIChtYXRjaF9vcGVyYW5kOlYxNiA1ICJyZWdfb3JfemVyb19v cGVyYW5kIildKQorCSAgKG1hdGNoX29wZXJhbmQ6PFZIX0NWVFRPPiAxICJzX3JlZ2lzdGVyX29w ZXJhbmQiKQorCSAgKG1hdGNoX29wZXJhbmQ6PFZIX0NWVFRPPiAyICJzX3JlZ2lzdGVyX29wZXJh bmQiKSkpXQorICAiQVJNX0hBVkVfPE1PREU+X0FSSVRICisgICAmJiAhVEFSR0VUX1JFQUxMWV9J V01NWFQKKyAgICYmICghPElzX2Zsb2F0X21vZGU+IHx8IGZsYWdfdW5zYWZlX21hdGhfb3B0aW1p emF0aW9ucykiCit7CisgIGFybV9leHBhbmRfdmNvbmQgKG9wZXJhbmRzLCA8Vl9jbXBfcmVzdWx0 Pm1vZGUpOworICBET05FOworfSkKKwogKGRlZmluZV9leHBhbmQgInZjb25kdTxtb2RlPjx2X2Nt cF9yZXN1bHQ+IgogICBbKHNldCAobWF0Y2hfb3BlcmFuZDpWRFFXIDAgInNfcmVnaXN0ZXJfb3Bl cmFuZCIpCiAJKGlmX3RoZW5fZWxzZTpWRFFXCkBAIC00NDYsMTEgKzQ2MiwxMSBAQCAoZGVmaW5l X2V4cGFuZCAidmNvbmR1PG1vZGU+PHZfY21wX3Jlc3VsdD4iCiB9KQogCiAoZGVmaW5lX2V4cGFu ZCAidmNvbmRfbWFza188bW9kZT48dl9jbXBfcmVzdWx0PiIKLSAgWyhzZXQgKG1hdGNoX29wZXJh bmQ6VkRRVyAwICJzX3JlZ2lzdGVyX29wZXJhbmQiKQotICAgICAgICAoaWZfdGhlbl9lbHNlOlZE UVcKKyAgWyhzZXQgKG1hdGNoX29wZXJhbmQ6VkRRV0ggMCAic19yZWdpc3Rlcl9vcGVyYW5kIikK KyAgICAgICAgKGlmX3RoZW5fZWxzZTpWRFFXSAogICAgICAgICAgIChtYXRjaF9vcGVyYW5kOjxW X2NtcF9yZXN1bHQ+IDMgInNfcmVnaXN0ZXJfb3BlcmFuZCIpCi0gICAgICAgICAgKG1hdGNoX29w ZXJhbmQ6VkRRVyAxICJzX3JlZ2lzdGVyX29wZXJhbmQiKQotICAgICAgICAgIChtYXRjaF9vcGVy YW5kOlZEUVcgMiAic19yZWdpc3Rlcl9vcGVyYW5kIikpKV0KKyAgICAgICAgICAobWF0Y2hfb3Bl cmFuZDpWRFFXSCAxICJzX3JlZ2lzdGVyX29wZXJhbmQiKQorICAgICAgICAgIChtYXRjaF9vcGVy YW5kOlZEUVdIIDIgInNfcmVnaXN0ZXJfb3BlcmFuZCIpKSldCiAgICJBUk1fSEFWRV88TU9ERT5f QVJJVEgKICAgICYmICFUQVJHRVRfUkVBTExZX0lXTU1YVAogICAgJiYgKCE8SXNfZmxvYXRfbW9k ZT4gfHwgZmxhZ191bnNhZmVfbWF0aF9vcHRpbWl6YXRpb25zKSIKZGlmZiAtLWdpdCBhL2djYy90 ZXN0c3VpdGUvZ2NjLnRhcmdldC9hcm0vYXJtdjhfMi1mcDE2LWFyaXRoLTEuYyBiL2djYy90ZXN0 c3VpdGUvZ2NjLnRhcmdldC9hcm0vYXJtdjhfMi1mcDE2LWFyaXRoLTEuYwppbmRleCA5MjFkMjZl Li41MmI4NzM3IDEwMDY0NAotLS0gYS9nY2MvdGVzdHN1aXRlL2djYy50YXJnZXQvYXJtL2FybXY4 XzItZnAxNi1hcml0aC0xLmMKKysrIGIvZ2NjL3Rlc3RzdWl0ZS9nY2MudGFyZ2V0L2FybS9hcm12 OF8yLWZwMTYtYXJpdGgtMS5jCkBAIC0xMDQsOCArMTA0LDIwIEBAIFRFU1RfQ01QIChncmVhdGVy dGhhbnF1YWwsID49LCBpbnQxNng4X3QsIGZsb2F0MTZ4OF90KQogLyogeyBkZy1maW5hbCB7IHNj YW4tYXNzZW1ibGVyLXRpbWVzIHt2bXVsXC5mMTZcdHFbMC05XSssIHFbMC05XSssIHFbMC05XSt9 IDEgfSB9ICAqLwogCiAvKiB7IGRnLWZpbmFsIHsgc2Nhbi1hc3NlbWJsZXItdGltZXMge3ZkaXZc LmYxNlx0c1swLTldKywgc1swLTldKywgc1swLTldK30gMTMgfSB9ICAqLwotLyogeyBkZy1maW5h bCB7IHNjYW4tYXNzZW1ibGVyLXRpbWVzIHt2Y21wXC5mMzJcdHNbMC05XSssIHNbMC05XSt9IDI2 IH0gfSAgKi8KLS8qIHsgZGctZmluYWwgeyBzY2FuLWFzc2VtYmxlci10aW1lcyB7dmNtcGVcLmYz Mlx0c1swLTldKywgc1swLTldK30gNTIgfSB9ICAqLworCisvKiBGb3IgZmxvYXQxNl90LiAgKi8K Ky8qIHsgZGctZmluYWwgeyBzY2FuLWFzc2VtYmxlci10aW1lcyB7dmNtcFwuZjMyXHRzWzAtOV0r LCBzWzAtOV0rfSAyIH0gfSAgKi8KKy8qIHsgZGctZmluYWwgeyBzY2FuLWFzc2VtYmxlci10aW1l cyB7dmNtcGVcLmYzMlx0c1swLTldKywgc1swLTldK30gNCB9IH0gICovCisKKy8qIEZvciBmbG9h dDE2eDRfdC4gICovCisvKiB7IGRnLWZpbmFsIHsgc2Nhbi1hc3NlbWJsZXItdGltZXMge3ZjZXFc LmYxNlx0ZFswLTldKywgZFswLTldK30gMiB9IH0gICovCisvKiB7IGRnLWZpbmFsIHsgc2Nhbi1h c3NlbWJsZXItdGltZXMge3ZjZ2VcLmYxNlx0ZFswLTldKywgZFswLTldK30gMiB9IH0gICovCisv KiB7IGRnLWZpbmFsIHsgc2Nhbi1hc3NlbWJsZXItdGltZXMge3ZjZ3RcLmYxNlx0ZFswLTldKywg ZFswLTldK30gMiB9IH0gICovCisKKy8qIEZvciBmbG9hdDE2eDhfdC4gICovCisvKiB7IGRnLWZp bmFsIHsgc2Nhbi1hc3NlbWJsZXItdGltZXMge3ZjZXFcLmYxNlx0cVswLTldKywgcVswLTldK30g MiB9IH0gICovCisvKiB7IGRnLWZpbmFsIHsgc2Nhbi1hc3NlbWJsZXItdGltZXMge3ZjZ2VcLmYx Nlx0cVswLTldKywgcVswLTldK30gMiB9IH0gICovCisvKiB7IGRnLWZpbmFsIHsgc2Nhbi1hc3Nl bWJsZXItdGltZXMge3ZjZ3RcLmYxNlx0cVswLTldKywgcVswLTldK30gMiB9IH0gICovCiAKIC8q IHsgZGctZmluYWwgeyBzY2FuLWFzc2VtYmxlci1ub3Qge3ZhZGRcLmYzMn0gfSB9ICAqLwogLyog eyBkZy1maW5hbCB7IHNjYW4tYXNzZW1ibGVyLW5vdCB7dnN1YlwuZjMyfSB9IH0gICovCmRpZmYg LS1naXQgYS9nY2MvdGVzdHN1aXRlL2djYy50YXJnZXQvYXJtL3NpbWQvbXZlLWNvbXBhcmUtMy5j IGIvZ2NjL3Rlc3RzdWl0ZS9nY2MudGFyZ2V0L2FybS9zaW1kL212ZS1jb21wYXJlLTMuYwpuZXcg ZmlsZSBtb2RlIDEwMDY0NAppbmRleCAwMDAwMDAwLi43NmY4MWU4Ci0tLSAvZGV2L251bGwKKysr IGIvZ2NjL3Rlc3RzdWl0ZS9nY2MudGFyZ2V0L2FybS9zaW1kL212ZS1jb21wYXJlLTMuYwpAQCAt MCwwICsxLDM4IEBACisvKiB7IGRnLWRvIGFzc2VtYmxlIH0gKi8KKy8qIHsgZGctcmVxdWlyZS1l ZmZlY3RpdmUtdGFyZ2V0IGFybV92OF8xbV9tdmVfZnBfb2sgfSAqLworLyogeyBkZy1hZGQtb3B0 aW9ucyBhcm1fdjhfMW1fbXZlX2ZwIH0gKi8KKy8qIHsgZGctYWRkaXRpb25hbC1vcHRpb25zICIt TzMgLWZ1bnNhZmUtbWF0aC1vcHRpbWl6YXRpb25zIiB9ICovCisKKy8qIGZsb2F0IDE2IHRlc3Rz LiAgKi8KKworI2lmbmRlZiBFTEVNX1RZUEUKKyNkZWZpbmUgRUxFTV9UWVBFIF9fZnAxNgorI2Vu ZGlmCisjaWZuZGVmIElOVF9FTEVNX1RZUEUKKyNkZWZpbmUgSU5UX0VMRU1fVFlQRSBfX0lOVDE2 X1RZUEVfXworI2VuZGlmCisKKyNkZWZpbmUgQ09NUEFSRShOQU1FLCBPUCkJCQlcCisgIGludF92 ZWMJCQkJCVwKKyAgY21wXyMjTkFNRSMjX3JlZyAodmVjIGEsIHZlYyBiKQkJXAorICB7CQkJCQkJ XAorICAgIHJldHVybiBhIE9QIGI7CQkJCVwKKyAgfQorCit0eXBlZGVmIElOVF9FTEVNX1RZUEUg aW50X3ZlYyBfX2F0dHJpYnV0ZV9fKCh2ZWN0b3Jfc2l6ZSgxNikpKTsKK3R5cGVkZWYgRUxFTV9U WVBFIHZlYyBfX2F0dHJpYnV0ZV9fKCh2ZWN0b3Jfc2l6ZSgxNikpKTsKKworQ09NUEFSRSAoZXEs ID09KQorQ09NUEFSRSAobmUsICE9KQorQ09NUEFSRSAobHQsIDwpCitDT01QQVJFIChsZSwgPD0p CitDT01QQVJFIChndCwgPikKK0NPTVBBUkUgKGdlLCA+PSkKKworLyogZXEsIG5lLCBsdCwgbGUs IGd0LCBnZS4KKy8qIHsgZGctZmluYWwgeyBzY2FuLWFzc2VtYmxlci10aW1lcyB7XHR2Y21wLmYx Nlx0ZXEsIHFbMC05XSssIHFbMC05XStcbn0gMSB9IH0gKi8KKy8qIHsgZGctZmluYWwgeyBzY2Fu LWFzc2VtYmxlci10aW1lcyB7XHR2Y21wLmYxNlx0bmUsIHFbMC05XSssIHFbMC05XStcbn0gMSB9 IH0gKi8KKy8qIHsgZGctZmluYWwgeyBzY2FuLWFzc2VtYmxlci10aW1lcyB7XHR2Y21wLmYxNlx0 bHQsIHFbMC05XSssIHFbMC05XStcbn0gMSB9IH0gKi8KKy8qIHsgZGctZmluYWwgeyBzY2FuLWFz c2VtYmxlci10aW1lcyB7XHR2Y21wLmYxNlx0bGUsIHFbMC05XSssIHFbMC05XStcbn0gMSB9IH0g Ki8KKy8qIHsgZGctZmluYWwgeyBzY2FuLWFzc2VtYmxlci10aW1lcyB7XHR2Y21wLmYxNlx0Z3Qs IHFbMC05XSssIHFbMC05XStcbn0gMSB9IH0gKi8KKy8qIHsgZGctZmluYWwgeyBzY2FuLWFzc2Vt Ymxlci10aW1lcyB7XHR2Y21wLmYxNlx0Z2UsIHFbMC05XSssIHFbMC05XStcbn0gMSB9IH0gKi8K ZGlmZiAtLWdpdCBhL2djYy90ZXN0c3VpdGUvZ2NjLnRhcmdldC9hcm0vc2ltZC9tdmUtdmNtcC1m MTYuYyBiL2djYy90ZXN0c3VpdGUvZ2NjLnRhcmdldC9hcm0vc2ltZC9tdmUtdmNtcC1mMTYuYwpu ZXcgZmlsZSBtb2RlIDEwMDY0NAppbmRleCAwMDAwMDAwLi5kYmFlMmQxCi0tLSAvZGV2L251bGwK KysrIGIvZ2NjL3Rlc3RzdWl0ZS9nY2MudGFyZ2V0L2FybS9zaW1kL212ZS12Y21wLWYxNi5jCkBA IC0wLDAgKzEsMzAgQEAKKy8qIHsgZGctZG8gYXNzZW1ibGUgfSAqLworLyogeyBkZy1yZXF1aXJl LWVmZmVjdGl2ZS10YXJnZXQgYXJtX3Y4XzFtX212ZV9mcF9vayB9ICovCisvKiB7IGRnLWFkZC1v cHRpb25zIGFybV92OF8xbV9tdmVfZnAgfSAqLworLyogeyBkZy1hZGRpdGlvbmFsLW9wdGlvbnMg Ii1PMyAtZnVuc2FmZS1tYXRoLW9wdGltaXphdGlvbnMiIH0gKi8KKworI2luY2x1ZGUgPHN0ZGlu dC5oPgorCisjZGVmaW5lIE5CIDgKKworI2RlZmluZSBGVU5DKE9QLCBOQU1FKQkJCQkJCQlcCisg IHZvaWQgdGVzdF8gIyMgTkFNRSAjI19mIChfX2ZwMTYgKiBfX3Jlc3RyaWN0X18gZGVzdCwgX19m cDE2ICphLCBfX2ZwMTYgKmIpIHsgXAorICAgIGludCBpOwkJCQkJCQkJXAorICAgIGZvciAoaT0w OyBpPE5COyBpKyspIHsJCQkJCQlcCisgICAgICBkZXN0W2ldID0gYVtpXSBPUCBiW2ldOwkJCQkJ CVwKKyAgICB9CQkJCQkJCQkJXAorICB9CisKK0ZVTkMoPT0sIHZjbXBlcSkKK0ZVTkMoIT0sIHZj bXBuZSkKK0ZVTkMoPCwgdmNtcGx0KQorRlVOQyg8PSwgdmNtcGxlKQorRlVOQyg+LCB2Y21wZ3Qp CitGVU5DKD49LCB2Y21wZ2UpCisKKy8qIHsgZGctZmluYWwgeyBzY2FuLWFzc2VtYmxlci10aW1l cyB7XHR2Y21wLmYxNlx0ZXEsIHFbMC05XSssIHFbMC05XStcbn0gMSB9IH0gKi8KKy8qIHsgZGct ZmluYWwgeyBzY2FuLWFzc2VtYmxlci10aW1lcyB7XHR2Y21wLmYxNlx0bmUsIHFbMC05XSssIHFb MC05XStcbn0gMSB9IH0gKi8KKy8qIHsgZGctZmluYWwgeyBzY2FuLWFzc2VtYmxlci10aW1lcyB7 XHR2Y21wLmYxNlx0bHQsIHFbMC05XSssIHFbMC05XStcbn0gMSB9IH0gKi8KKy8qIHsgZGctZmlu YWwgeyBzY2FuLWFzc2VtYmxlci10aW1lcyB7XHR2Y21wLmYxNlx0bGUsIHFbMC05XSssIHFbMC05 XStcbn0gMSB9IH0gKi8KKy8qIHsgZGctZmluYWwgeyBzY2FuLWFzc2VtYmxlci10aW1lcyB7XHR2 Y21wLmYxNlx0Z3QsIHFbMC05XSssIHFbMC05XStcbn0gMSB9IH0gKi8KKy8qIHsgZGctZmluYWwg eyBzY2FuLWFzc2VtYmxlci10aW1lcyB7XHR2Y21wLmYxNlx0Z2UsIHFbMC05XSssIHFbMC05XStc bn0gMSB9IH0gKi8KLS0gCjIuNy40Cgo= --00000000000092aba105c195be77--