From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 104191 invoked by alias); 26 Sep 2016 12:48:41 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 101046 invoked by uid 89); 26 Sep 2016 12:48:40 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 spammy=Hx-languages-length:2127 X-HELO: mail-qt0-f176.google.com Received: from mail-qt0-f176.google.com (HELO mail-qt0-f176.google.com) (209.85.216.176) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 26 Sep 2016 12:48:30 +0000 Received: by mail-qt0-f176.google.com with SMTP id 93so80051085qtg.2 for ; Mon, 26 Sep 2016 05:48:29 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=HZl9H7qXnJ6OUka01tijap12ocigHlf6vkuAu2LyHac=; b=l7ppJHmz0xZpKf2YY06kWUUJSN/ziNGsDd28jzsGP4tSfwPbaerFQCIRL70K81E4tD ybGfWIbbWsytdq9zVnqwR3iRdA2j27cMnlZUeucZLqJdK83yI9Q5zkLmoTaUWN0o3Neo yn9bvpx1S7zYR+wU1MBu6LRFSwvNPYr9ZLTXZ/EZQ7lvoXnPpmfoAf5PdD00QbFhnLep rQlwWFJFNZsOwxQV7qeEDLxZX/8q22POqGFSrGxbIF6/L8EOVAP4aCTWeIKYZjg01JbI f7zVuFy9V0GPSj/4Ai5f6Ue6pRvgt5rBOoNY7adBiF3kAh8ryDFl0QE5bfXK/2SDLiEz NcWw== X-Gm-Message-State: AA6/9Rnw6iN+3NC0nGHjfUOmE6WUnzuGs3Zh9LThrZ9REKQAvoXWLCS92CauZpjksxVi8Vv+NP4Xb4QATBXbqP32 X-Received: by 10.200.47.3 with SMTP id j3mr20624201qta.27.1474894108349; Mon, 26 Sep 2016 05:48:28 -0700 (PDT) MIME-Version: 1.0 Received: by 10.140.21.80 with HTTP; Mon, 26 Sep 2016 05:48:27 -0700 (PDT) In-Reply-To: <57E8EDDB.3010008@foss.arm.com> References: <573B28A3.9030603@foss.arm.com> <573B2B5E.3000206@foss.arm.com> <57E8EDDB.3010008@foss.arm.com> From: Christophe Lyon Date: Mon, 26 Sep 2016 12:54:00 -0000 Message-ID: Subject: Re: [PATCH 6/17][ARM] Add data processing intrinsics for float16_t. To: Matthew Wahab Cc: Ramana Radhakrishnan , gcc-patches Content-Type: text/plain; charset=UTF-8 X-IsSubscribed: yes X-SW-Source: 2016-09/txt/msg01818.txt.bz2 On 26 September 2016 at 11:43, Matthew Wahab wrote: > Hello, > > On 25/09/16 14:00, Christophe Lyon wrote: >>>> >>>> >>>> This patch adds the new intrinsics: >>>> vbsl_f16, vbslq_f16, vdup_n_f16, vdupq_n_f16, vdup_lane_f16, >>>> vdupq_lane_f16, vext_f16, vextq_f16, vmov_n_f16, vmovq_n_f16, >>>> vrev64_f16, vrev64q_f16, vtrn_f16, vtrnq_f16, vuzp_f16, vuzpq_f16, >>>> vzip_f16, vzipq_f16. >>>> >>>> This patch also updates the advsimd-intrinsics testsuite to test the f16 >>>> variants for ARM targets. These intrinsics are only implemented in the >>>> ARM target so the tests are disabled for AArch64 using an extra >>>> condition on a new convenience macro FP16_SUPPORTED. This patch also >>>> disables, for the ARM target, the testsuite defined macro vdup_n_f16 as >>>> it is no longer needed. >> >> >> Since you committed this patch, I've noticed that libgcc fails to build >> when GCC is configured: >> --target arm-none-eabi and default cpu >> /tmp/9649048_29.tmpdir/ccuBwQJJ.s: Assembler messages: >> /tmp/9649048_29.tmpdir/ccuBwQJJ.s:64: Error: selected processor does >> not support ARM mode `movwlt r0,32768' >> /tmp/9649048_29.tmpdir/ccuBwQJJ.s:65: Error: selected processor does >> not support ARM mode `movwge r0,32767' >> make[4]: *** [_ssaddHQ.o] Error 1 >> make[4]: Leaving directory >> >> `/tmp/9649048_29.tmpdir/aci-gcc-fsf/builds/gcc-fsf-gccsrc/obj-arm-none-eabi/gcc1/arm-none-eabi/fpu/libgcc' >> > > > I can't reproduce the failure, could you send the configure arguments for > the build. > If I'm not mistaken, that is: --target=arm-none-eabi --disable-nls --disable-libgomp --disable-libmudflap --disable-libcilkrts --enable-checking --enable-languages=c,c++ --with-newlib Maybe you've disabled multilibs? > I've tried assembling the string 'movw r0, 32768' and get the error when > -march=armv6kz or earlier. I suspect the new movhi and/or movhf patterns > added earlier in the series need the architecture level added as a > precondition but I'll need to look into it. > > Matthew Thanks, Christophe