From: Christophe Lyon <christophe.lyon@linaro.org>
To: Tejas Belagod <tejas.belagod@arm.com>
Cc: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>
Subject: Re: [[ARM/AArch64][testsuite] 17/36] Add vpadd, vpmax and vpmin tests.
Date: Tue, 20 Jan 2015 15:34:00 -0000 [thread overview]
Message-ID: <CAKdteOYRocU+U79nF-QwLG46+QqG210wm4zc6-Cxaj3YKPgo8w@mail.gmail.com> (raw)
In-Reply-To: <CAKdteOZ-CbjG0bwaPaT0z=812GejtgwSOccKnQeHfv-e6XqDDw@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 7275 bytes --]
On 16 January 2015 at 18:54, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> On 16 January 2015 at 18:52, Tejas Belagod <tejas.belagod@arm.com> wrote:
>> On 13/01/15 15:18, Christophe Lyon wrote:
>>>
>>> * gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc: New file.
>>> * gcc.target/aarch64/advsimd-intrinsics/vpadd.c: New file.
>>> * gcc.target/aarch64/advsimd-intrinsics/vpmax.c: New file.
>>> * gcc.target/aarch64/advsimd-intrinsics/vpmin.c: New file.
>>>
>>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc
>>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc
>>> new file mode 100644
>>> index 0000000..7ac2ed4
>>> --- /dev/null
>>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc
>>> @@ -0,0 +1,67 @@
>>> +#define FNNAME1(NAME) exec_ ## NAME
>>> +#define FNNAME(NAME) FNNAME1(NAME)
>>> +
>>> +void FNNAME (INSN_NAME) (void)
>>> +{
>>> + /* Basic test: y=OP(x), then store the result. */
>>> +#define TEST_VPADD1(INSN, T1, T2, W, N)
>>> \
>>> + VECT_VAR(vector_res, T1, W, N) = \
>>> + INSN##_##T2##W(VECT_VAR(vector, T1, W, N), \
>>> + VECT_VAR(vector, T1, W, N)); \
>>> + vst1##_##T2##W(VECT_VAR(result, T1, W, N), \
>>> + VECT_VAR(vector_res, T1, W, N))
>>> +
>>> +#define TEST_VPADD(INSN, T1, T2, W, N) \
>>> + TEST_VPADD1(INSN, T1, T2, W, N) \
>>> +
>>> + /* No need for 64 bits variants. */
>>> + DECL_VARIABLE(vector, int, 8, 8);
>>> + DECL_VARIABLE(vector, int, 16, 4);
>>> + DECL_VARIABLE(vector, int, 32, 2);
>>> + DECL_VARIABLE(vector, uint, 8, 8);
>>> + DECL_VARIABLE(vector, uint, 16, 4);
>>> + DECL_VARIABLE(vector, uint, 32, 2);
>>> + DECL_VARIABLE(vector, float, 32, 2);
>>> +
>>> + DECL_VARIABLE(vector_res, int, 8, 8);
>>> + DECL_VARIABLE(vector_res, int, 16, 4);
>>> + DECL_VARIABLE(vector_res, int, 32, 2);
>>> + DECL_VARIABLE(vector_res, uint, 8, 8);
>>> + DECL_VARIABLE(vector_res, uint, 16, 4);
>>> + DECL_VARIABLE(vector_res, uint, 32, 2);
>>> + DECL_VARIABLE(vector_res, float, 32, 2);
>>> +
>>> + clean_results ();
>>> +
>>> + /* Initialize input "vector" from "buffer". */
>>> + VLOAD(vector, buffer, , int, s, 8, 8);
>>> + VLOAD(vector, buffer, , int, s, 16, 4);
>>> + VLOAD(vector, buffer, , int, s, 32, 2);
>>> + VLOAD(vector, buffer, , uint, u, 8, 8);
>>> + VLOAD(vector, buffer, , uint, u, 16, 4);
>>> + VLOAD(vector, buffer, , uint, u, 32, 2);
>>> + VLOAD(vector, buffer, , float, f, 32, 2);
>>> +
>>> + /* Apply a unary operator named INSN_NAME. */
>>
>>
>> Unary op?
>>
> Hmm cut & paste issue. Thanks
>
Here is an updated versoin, also renaming VPADD into VPXXX, since it's
in a template.
>>
>>> + TEST_VPADD(INSN_NAME, int, s, 8, 8);
>>> + TEST_VPADD(INSN_NAME, int, s, 16, 4);
>>> + TEST_VPADD(INSN_NAME, int, s, 32, 2);
>>> + TEST_VPADD(INSN_NAME, uint, u, 8, 8);
>>> + TEST_VPADD(INSN_NAME, uint, u, 16, 4);
>>> + TEST_VPADD(INSN_NAME, uint, u, 32, 2);
>>> + TEST_VPADD(INSN_NAME, float, f, 32, 2);
>>> +
>>> + CHECK(TEST_MSG, int, 8, 8, PRIx32, expected, "");
>>> + CHECK(TEST_MSG, int, 16, 4, PRIx64, expected, "");
>>> + CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, "");
>>> + CHECK(TEST_MSG, uint, 8, 8, PRIx32, expected, "");
>>> + CHECK(TEST_MSG, uint, 16, 4, PRIx64, expected, "");
>>> + CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
>>> + CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, "");
>>> +}
>>> +
>>> +int main (void)
>>> +{
>>> + FNNAME (INSN_NAME) ();
>>> + return 0;
>>> +}
>>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c
>>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c
>>> new file mode 100644
>>> index 0000000..5ddfd3d
>>> --- /dev/null
>>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c
>>> @@ -0,0 +1,19 @@
>>> +#include <arm_neon.h>
>>> +#include "arm-neon-ref.h"
>>> +#include "compute-ref-data.h"
>>> +
>>> +#define INSN_NAME vpadd
>>> +#define TEST_MSG "VPADD"
>>> +
>>> +/* Expected results. */
>>> +VECT_VAR_DECL(expected,int,8,8) [] = { 0xe1, 0xe5, 0xe9, 0xed,
>>> + 0xe1, 0xe5, 0xe9, 0xed };
>>> +VECT_VAR_DECL(expected,int,16,4) [] = { 0xffe1, 0xffe5, 0xffe1, 0xffe5 };
>>> +VECT_VAR_DECL(expected,int,32,2) [] = { 0xffffffe1, 0xffffffe1 };
>>> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0xe1, 0xe5, 0xe9, 0xed,
>>> + 0xe1, 0xe5, 0xe9, 0xed };
>>> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xffe1, 0xffe5, 0xffe1, 0xffe5
>>> };
>>> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffffe1, 0xffffffe1 };
>>> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1f80000, 0xc1f80000 };
>>> +
>>> +#include "vpXXX.inc"
>>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c
>>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c
>>> new file mode 100644
>>> index 0000000..f27a9a9
>>> --- /dev/null
>>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c
>>> @@ -0,0 +1,20 @@
>>> +#include <arm_neon.h>
>>> +#include "arm-neon-ref.h"
>>> +#include "compute-ref-data.h"
>>> +
>>> +
>>> +#define INSN_NAME vpmax
>>> +#define TEST_MSG "VPMAX"
>>> +
>>> +/* Expected results. */
>>> +VECT_VAR_DECL(expected,int,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7,
>>> + 0xf1, 0xf3, 0xf5, 0xf7 };
>>> +VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff1, 0xfff3, 0xfff1, 0xfff3 };
>>> +VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff1, 0xfffffff1 };
>>> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7,
>>> + 0xf1, 0xf3, 0xf5, 0xf7 };
>>> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff1, 0xfff3, 0xfff1, 0xfff3
>>> };
>>> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff1, 0xfffffff1 };
>>> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1700000, 0xc1700000 };
>>> +
>>> +#include "vpXXX.inc"
>>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c
>>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c
>>> new file mode 100644
>>> index 0000000..a7cb696
>>> --- /dev/null
>>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c
>>> @@ -0,0 +1,20 @@
>>> +#include <arm_neon.h>
>>> +#include "arm-neon-ref.h"
>>> +#include "compute-ref-data.h"
>>> +
>>> +
>>> +#define INSN_NAME vpmin
>>> +#define TEST_MSG "VPMIN"
>>> +
>>> +/* Expected results. */
>>> +VECT_VAR_DECL(expected,int,8,8) [] = { 0xf0, 0xf2, 0xf4, 0xf6,
>>> + 0xf0, 0xf2, 0xf4, 0xf6 };
>>> +VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff0, 0xfff2, 0xfff0, 0xfff2 };
>>> +VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0xfffffff0 };
>>> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf0, 0xf2, 0xf4, 0xf6,
>>> + 0xf0, 0xf2, 0xf4, 0xf6 };
>>> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff0, 0xfff2, 0xfff0, 0xfff2
>>> };
>>> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff0 };
>>> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0xc1800000 };
>>> +
>>> +#include "vpXXX.inc"
>>>
>>
>> Otherwise LGTM.
>>
>> Tejas.
>>
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From 3a8d5a974d49332cd4de6675aa0d58501b967518 Mon Sep 17 00:00:00 2001
From: Christophe Lyon <christophe.lyon@linaro.org>
Date: Tue, 9 Dec 2014 22:27:01 +0100
Subject: [[ARM/AArch64][testsuite] 17/36] Add vpadd, vpmax and vpmin tests.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc
new file mode 100644
index 0000000..c1b7235
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc
@@ -0,0 +1,67 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+ /* Basic test: y=OP(x), then store the result. */
+#define TEST_VPXXX1(INSN, T1, T2, W, N) \
+ VECT_VAR(vector_res, T1, W, N) = \
+ INSN##_##T2##W(VECT_VAR(vector, T1, W, N), \
+ VECT_VAR(vector, T1, W, N)); \
+ vst1##_##T2##W(VECT_VAR(result, T1, W, N), \
+ VECT_VAR(vector_res, T1, W, N))
+
+#define TEST_VPXXX(INSN, T1, T2, W, N) \
+ TEST_VPXXX1(INSN, T1, T2, W, N) \
+
+ /* No need for 64 bits variants. */
+ DECL_VARIABLE(vector, int, 8, 8);
+ DECL_VARIABLE(vector, int, 16, 4);
+ DECL_VARIABLE(vector, int, 32, 2);
+ DECL_VARIABLE(vector, uint, 8, 8);
+ DECL_VARIABLE(vector, uint, 16, 4);
+ DECL_VARIABLE(vector, uint, 32, 2);
+ DECL_VARIABLE(vector, float, 32, 2);
+
+ DECL_VARIABLE(vector_res, int, 8, 8);
+ DECL_VARIABLE(vector_res, int, 16, 4);
+ DECL_VARIABLE(vector_res, int, 32, 2);
+ DECL_VARIABLE(vector_res, uint, 8, 8);
+ DECL_VARIABLE(vector_res, uint, 16, 4);
+ DECL_VARIABLE(vector_res, uint, 32, 2);
+ DECL_VARIABLE(vector_res, float, 32, 2);
+
+ clean_results ();
+
+ /* Initialize input "vector" from "buffer". */
+ VLOAD(vector, buffer, , int, s, 8, 8);
+ VLOAD(vector, buffer, , int, s, 16, 4);
+ VLOAD(vector, buffer, , int, s, 32, 2);
+ VLOAD(vector, buffer, , uint, u, 8, 8);
+ VLOAD(vector, buffer, , uint, u, 16, 4);
+ VLOAD(vector, buffer, , uint, u, 32, 2);
+ VLOAD(vector, buffer, , float, f, 32, 2);
+
+ /* Apply a binary operator named INSN_NAME. */
+ TEST_VPXXX(INSN_NAME, int, s, 8, 8);
+ TEST_VPXXX(INSN_NAME, int, s, 16, 4);
+ TEST_VPXXX(INSN_NAME, int, s, 32, 2);
+ TEST_VPXXX(INSN_NAME, uint, u, 8, 8);
+ TEST_VPXXX(INSN_NAME, uint, u, 16, 4);
+ TEST_VPXXX(INSN_NAME, uint, u, 32, 2);
+ TEST_VPXXX(INSN_NAME, float, f, 32, 2);
+
+ CHECK(TEST_MSG, int, 8, 8, PRIx32, expected, "");
+ CHECK(TEST_MSG, int, 16, 4, PRIx64, expected, "");
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 8, 8, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 16, 4, PRIx64, expected, "");
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
+ CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, "");
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c
new file mode 100644
index 0000000..5ddfd3d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c
@@ -0,0 +1,19 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vpadd
+#define TEST_MSG "VPADD"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xe1, 0xe5, 0xe9, 0xed,
+ 0xe1, 0xe5, 0xe9, 0xed };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xffe1, 0xffe5, 0xffe1, 0xffe5 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xffffffe1, 0xffffffe1 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0xe1, 0xe5, 0xe9, 0xed,
+ 0xe1, 0xe5, 0xe9, 0xed };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xffe1, 0xffe5, 0xffe1, 0xffe5 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffffe1, 0xffffffe1 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1f80000, 0xc1f80000 };
+
+#include "vpXXX.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c
new file mode 100644
index 0000000..f27a9a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c
@@ -0,0 +1,20 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+
+#define INSN_NAME vpmax
+#define TEST_MSG "VPMAX"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7,
+ 0xf1, 0xf3, 0xf5, 0xf7 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff1, 0xfff3, 0xfff1, 0xfff3 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff1, 0xfffffff1 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7,
+ 0xf1, 0xf3, 0xf5, 0xf7 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff1, 0xfff3, 0xfff1, 0xfff3 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff1, 0xfffffff1 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1700000, 0xc1700000 };
+
+#include "vpXXX.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c
new file mode 100644
index 0000000..a7cb696
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c
@@ -0,0 +1,20 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+
+#define INSN_NAME vpmin
+#define TEST_MSG "VPMIN"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xf0, 0xf2, 0xf4, 0xf6,
+ 0xf0, 0xf2, 0xf4, 0xf6 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff0, 0xfff2, 0xfff0, 0xfff2 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0xfffffff0 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf0, 0xf2, 0xf4, 0xf6,
+ 0xf0, 0xf2, 0xf4, 0xf6 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff0, 0xfff2, 0xfff0, 0xfff2 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff0 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0xc1800000 };
+
+#include "vpXXX.inc"
--
2.1.0
next prev parent reply other threads:[~2015-01-20 15:30 UTC|newest]
Thread overview: 144+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 30/36] Add vpaddl tests Christophe Lyon
2015-01-16 18:48 ` Tejas Belagod
2015-01-16 19:05 ` Christophe Lyon
2015-01-16 20:34 ` Christophe Lyon
2015-01-20 15:50 ` Christophe Lyon
2015-01-26 14:47 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 08/36] Add vtrn tests. Refactor vzup and vzip tests Christophe Lyon
2015-01-16 16:06 ` Tejas Belagod
2015-01-16 18:12 ` Christophe Lyon
2015-01-19 13:52 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 32/36] Add vqdmulh_lane tests Christophe Lyon
2015-01-19 16:47 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 25/36] Add vmull tests Christophe Lyon
2015-01-16 18:26 ` Tejas Belagod
2015-01-19 15:34 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 02/36] Be more verbose, and actually confirm that a test was checked Christophe Lyon
2015-01-16 13:46 ` Tejas Belagod
2015-01-16 17:17 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 23/36] Add vmul_lane tests Christophe Lyon
2015-01-16 18:23 ` Tejas Belagod
2015-01-19 15:17 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 27/36] Add vmull_n tests Christophe Lyon
2015-01-16 18:32 ` Tejas Belagod
2015-01-19 15:35 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 16/36] Add vqdmlal_n and vqdmlsl_n tests Christophe Lyon
2015-01-16 17:26 ` Tejas Belagod
2015-01-19 14:14 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 29/36] Add vpadal tests Christophe Lyon
2015-01-16 18:41 ` Tejas Belagod
2015-01-20 15:39 ` Christophe Lyon
2015-01-26 14:34 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 20/36] Add vsubw tests, putting most of the code in common with vaddw through vXXWw.inc Christophe Lyon
2015-01-16 18:16 ` Tejas Belagod
2015-01-19 14:41 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 04/36] Add vld1_lane tests Christophe Lyon
2015-01-16 14:31 ` Tejas Belagod
2015-01-16 16:31 ` Christophe Lyon
2015-01-16 17:22 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 22/36] Add vmovn tests Christophe Lyon
2015-01-16 18:21 ` Tejas Belagod
2015-01-19 14:44 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 09/36] Add vsubhn, vraddhn and vrsubhn tests. Split vaddhn.c into vXXXhn.inc and vaddhn.c to share code with other new tests Christophe Lyon
2015-01-16 16:21 ` Tejas Belagod
2015-01-16 16:35 ` Christophe Lyon
2015-01-20 15:30 ` Christophe Lyon
2015-01-26 14:03 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 12/36] Add vmlal_n and vmlsl_n tests Christophe Lyon
2015-01-16 16:29 ` Tejas Belagod
2015-01-19 13:54 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 28/36] Add vmnv tests Christophe Lyon
2015-01-16 18:39 ` Tejas Belagod
2015-01-20 15:36 ` Christophe Lyon
2015-01-26 14:30 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 07/36] Add vmla_lane and vmls_lane tests Christophe Lyon
2015-01-16 15:57 ` Tejas Belagod
2015-01-19 13:43 ` Marcus Shawcroft
2015-01-21 0:02 ` Christophe Lyon
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 14/36] Add vqdmlal and vqdmlsl tests Christophe Lyon
2015-01-16 16:45 ` Tejas Belagod
2015-01-19 14:11 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 03/36] Add vmax, vmin, vhadd, vhsub and vrhadd tests Christophe Lyon
2015-01-16 14:08 ` Tejas Belagod
2015-01-16 16:23 ` Christophe Lyon
2015-01-16 17:20 ` Marcus Shawcroft
2015-01-16 17:59 ` Christophe Lyon
2015-01-19 13:34 ` Marcus Shawcroft
2015-01-19 15:49 ` Christophe Lyon
2015-01-19 17:33 ` Marcus Shawcroft
2015-01-21 16:35 ` Christophe Lyon
2015-01-22 12:37 ` Tejas Belagod
2015-01-22 14:42 ` Christophe Lyon
2015-01-22 15:58 ` Tejas Belagod
2015-01-22 23:10 ` Christophe Lyon
2015-01-23 11:02 ` Tejas Belagod
2015-01-23 12:08 ` Christophe Lyon
2015-01-23 15:21 ` Christophe Lyon
2015-01-25 22:51 ` Christophe Lyon
2015-01-26 13:23 ` Tejas Belagod
2015-01-26 13:57 ` Christophe Lyon
2015-02-02 10:39 ` Christophe Lyon
2015-02-02 15:38 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 01/36] Add explicit dependency on Neon Cumulative Saturation flag (QC) Christophe Lyon
2015-01-16 13:43 ` Tejas Belagod
2015-01-16 17:15 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 06/36] Add vmla and vmls tests Christophe Lyon
2015-01-16 15:52 ` Tejas Belagod
2015-01-16 16:32 ` Christophe Lyon
2015-01-19 13:42 ` Marcus Shawcroft
2015-01-20 22:23 ` Christophe Lyon
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 31/36] Add vqdmulh tests Christophe Lyon
2015-01-19 16:46 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 34/36] Add vqdmull tests Christophe Lyon
2015-01-19 16:52 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 05/36] Add vldX_dup test Christophe Lyon
2015-01-16 15:35 ` Tejas Belagod
2015-01-16 18:17 ` Christophe Lyon
2015-01-19 13:39 ` Marcus Shawcroft
2015-01-22 16:32 ` Tejas Belagod
2015-01-22 22:23 ` Christophe Lyon
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 21/36] Add vmovl tests Christophe Lyon
2015-01-16 18:18 ` Tejas Belagod
2015-01-20 15:35 ` Christophe Lyon
2015-01-26 14:19 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 18/36] Add vsli_n and vsri_n tests Christophe Lyon
2015-01-16 18:11 ` Tejas Belagod
2015-01-19 14:15 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 33/36] Add vqdmulh_n tests Christophe Lyon
2015-01-19 16:48 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 24/36] Add vmul_n tests Christophe Lyon
2015-01-16 18:24 ` Tejas Belagod
2015-01-19 15:23 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 15/36] Add vqdmlal_lane and vqdmlsl_lane tests Christophe Lyon
2015-01-16 16:52 ` Tejas Belagod
2015-01-19 14:13 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 13/36] Add vmla_n and vmls_n tests Christophe Lyon
2015-01-16 16:30 ` Tejas Belagod
2015-01-20 15:33 ` Christophe Lyon
2015-01-26 14:08 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 26/36] Add vmull_lane tests Christophe Lyon
2015-01-16 18:28 ` Tejas Belagod
2015-01-19 15:35 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 11/36] Add vmlal_lane and vmlsl_lane tests Christophe Lyon
2015-01-16 16:23 ` Tejas Belagod
2015-01-19 13:53 ` Marcus Shawcroft
2015-01-13 15:20 ` [[ARM/AArch64][testsuite] 17/36] Add vpadd, vpmax and vpmin tests Christophe Lyon
2015-01-16 17:54 ` Tejas Belagod
2015-01-16 18:02 ` Christophe Lyon
2015-01-20 15:34 ` Christophe Lyon [this message]
2015-01-26 14:19 ` Marcus Shawcroft
2015-01-13 15:20 ` [[ARM/AArch64][testsuite] 19/36] Add vsubl tests, put most of the code in common with vaddl in vXXXl.inc Christophe Lyon
2015-01-16 18:12 ` Tejas Belagod
2015-01-19 14:37 ` Marcus Shawcroft
2015-01-13 15:20 ` [[ARM/AArch64][testsuite] 10/36] Add vmlal and vmlsl tests Christophe Lyon
2015-01-16 16:22 ` Tejas Belagod
2015-01-19 13:51 ` Marcus Shawcroft
2015-01-13 15:21 ` [[ARM/AArch64][testsuite] 35/36] Add vqdmull_lane tests Christophe Lyon
2015-01-19 16:54 ` Marcus Shawcroft
2015-01-13 15:22 ` [[ARM/AArch64][testsuite] 36/36] Add vqdmull_n tests Christophe Lyon
2015-01-16 18:49 ` Tejas Belagod
2015-01-16 19:20 ` Christophe Lyon
2015-01-19 17:16 ` Marcus Shawcroft
2015-01-19 17:18 ` [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Marcus Shawcroft
2015-01-20 15:26 ` Christophe Lyon
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