From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 83367 invoked by alias); 5 Sep 2019 08:32:08 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 83358 invoked by uid 89); 5 Sep 2019 08:32:08 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-16.1 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.1 spammy=H*i:sk:CAKdteO X-HELO: mail-lj1-f194.google.com Received: from mail-lj1-f194.google.com (HELO mail-lj1-f194.google.com) (209.85.208.194) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 05 Sep 2019 08:32:06 +0000 Received: by mail-lj1-f194.google.com with SMTP id t14so1516932lji.4 for ; Thu, 05 Sep 2019 01:32:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=BByy6DRL6C0Ao2ldf4EJEBnNbRj5QFX32m5HaF4XCDQ=; b=mkvzPKCZH0ZxH6hYp0piCRw4k/6G5kY+xF17SFBO/ok55tVDZ5r1P92H5oG/PmWDHn 9oq2KjTJHSly9mLPhAJfGpXb5Iwdi0hPAPAJB5KrmXrYlAZYzpVqm1HOGqGtEJ2DEPti WoRiKaUm538M6tK07nNaD6eQxTst3ngFqi7SB3yDnBc6ZwJrQd1pmnqJHt3BEkO6NLJc x4/ti64cDTOFa55iLpn8y8FzH+4sDtPuSOaxCMQU3oei5cbwr0vk2ZOfYxZp2NhhfWqk LKbNdD9Pnb5I2t5a8IvsfRReSOg4r73Z6wwniG+jMlK32dUY+NksQGTnAw61gU1Twh70 BUFA== MIME-Version: 1.0 References: <20190515124006.25840-1-christophe.lyon@st.com> <20190515124006.25840-14-christophe.lyon@st.com> <19a091e0-c1fe-c4f7-5eab-5e09ab1de3fd@foss.arm.com> In-Reply-To: From: Christophe Lyon Date: Thu, 05 Sep 2019 08:32:00 -0000 Message-ID: Subject: Re: [ARM/FDPIC v5 13/21] [ARM] FDPIC: Force LSB bit for PC in Cortex-M architecture To: Kyrill Tkachov , Ian Lance Taylor Cc: Christophe Lyon , "gcc-patches@gcc.gnu.org" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2019-09/txt/msg00246.txt.bz2 Sorry, I forgot again to cc: Ian. Thanks, Christophe On Thu, 5 Sep 2019 at 10:30, Christophe Lyon w= rote: > > On Thu, 29 Aug 2019 at 17:32, Kyrill Tkachov > wrote: > > > > Hi Christophe, > > > > On 5/15/19 1:39 PM, Christophe Lyon wrote: > > > Without this, when we are unwinding across a signal frame we can jump > > > to an even address which leads to an exception. > > > > > > This is needed in __gnu_persnality_sigframe_fdpic() when restoring the > > > PC from the signal frame since the PC saved by the kernel has the LSB > > > bit set to zero. > > > > > > 2019-XX-XX Christophe Lyon > > > Micka=C3=ABl Gu=C3=AAn=C3=A9 > > > > > > libgcc/ > > > * config/arm/unwind-arm.c (_Unwind_VRS_Set): Handle v7m > > > architecture. > > > > > > Change-Id: Ie84de548226bcf1751e19a09e8f091fb3013ccea > > > > > > diff --git a/libgcc/config/arm/unwind-arm.c > > > b/libgcc/config/arm/unwind-arm.c > > > index 9ba73e7..ba47150 100644 > > > --- a/libgcc/config/arm/unwind-arm.c > > > +++ b/libgcc/config/arm/unwind-arm.c > > > @@ -199,6 +199,11 @@ _Unwind_VRS_Result _Unwind_VRS_Set > > > (_Unwind_Context *context, > > > return _UVRSR_FAILED; > > > > > > vrs->core.r[regno] =3D *(_uw *) valuep; > > > +#if defined(__ARM_ARCH_7M__) > > > + /* Force LSB bit since we always run thumb code. */ > > > + if (regno =3D=3D 15) > > > + vrs->core.r[regno] |=3D 1; > > > +#endif > > > > Hmm, this looks quite specific. There are other architectures that are > > thumb-only too (6-M, 7E-M etc). > > > > Would checking for __thumb__ be better? > > > Right. > The attached updated patch also uses R_PC instead of 15. > > Christophe > > > Thanks, > > > > Kyrill > > > > > > > return _UVRSR_OK; > > > > > > case _UVRSC_VFP: > > > -- > > > 2.6.3 > > >