From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 76426 invoked by alias); 18 Sep 2018 22:00:34 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 76144 invoked by uid 89); 18 Sep 2018 22:00:18 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy=UD:copysign-bsl.c, copysign-bsl.c, copysignbslc, Is X-HELO: mail-lf1-f65.google.com Received: from mail-lf1-f65.google.com (HELO mail-lf1-f65.google.com) (209.85.167.65) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 18 Sep 2018 22:00:16 +0000 Received: by mail-lf1-f65.google.com with SMTP id c29-v6so3300103lfj.1 for ; Tue, 18 Sep 2018 15:00:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=WUfY9lAT4p7ikAwRDZLDfV1lZWssaQmqUCeJAV3s4cw=; b=RxqoBTP3lrOgaZkPjVzs9/0FcO2gjk5dNweBg9th2ahf53dhiOYtmK24jHJI70fPF0 zkivVhR3ZE5e8yRMsj/Pffw5kKgoByrzGe2oNvuMoktraq7kqZIpATDHKOwgVFFEHbvM WbXK2imROm4TvhoaDXQWZPawsbaH/FphIaec8= MIME-Version: 1.0 References: <44d5392a-f033-ed0d-d679-116b3eafa0b9@arm.com> <20180828225320.GE22590@arm.com> <20180911152000.GA37978@arm.com> <4ab58a71-c586-410c-9fc2-5e9bb0c07de6@arm.com> <5B9A329D.4060009@foss.arm.com> In-Reply-To: <5B9A329D.4060009@foss.arm.com> From: Christophe Lyon Date: Tue, 18 Sep 2018 22:26:00 -0000 Message-ID: Subject: Re: [GCC][PATCH v2][Aarch64] Exploiting BFXIL when OR-ing two AND-operations with appropriate bitmasks To: Kyrill Tkachov Cc: sam.tebbs@arm.com, James Greenhalgh , gcc Patches , Marcus Shawcroft , Richard Earnshaw , nd Content-Type: text/plain; charset="UTF-8" X-IsSubscribed: yes X-SW-Source: 2018-09/txt/msg01032.txt.bz2 On Thu, 13 Sep 2018 at 11:49, Kyrill Tkachov wrote: > > > On 13/09/18 10:25, Sam Tebbs wrote: > > > > On 09/11/2018 04:20 PM, James Greenhalgh wrote: > > > On Tue, Sep 04, 2018 at 10:13:43AM -0500, Sam Tebbs wrote: > > >> Hi James, > > >> > > >> Thanks for the feedback. Here is an update with the changes you proposed > > >> and an updated changelog. > > >> > > >> gcc/ > > >> 2018-09-04 Sam Tebbs > > >> > > >> PR target/85628 > > >> * config/aarch64/aarch64.md (*aarch64_bfxil): > > >> Define. > > >> * config/aarch64/constraints.md (Ulc): Define > > >> * config/aarch64/aarch64-protos.h (aarch64_high_bits_all_ones_p): > > >> Define. > > >> * config/aarch64/aarch64.c (aarch64_high_bits_all_ones_p): New function. > > >> > > >> gcc/testsuite > > >> 2018-09-04 Sam Tebbs > > >> > > >> PR target/85628 > > >> * gcc.target/aarch64/combine_bfxil.c: New file. > > >> * gcc.target/aarch64/combine_bfxil_2.c: New file. > > >> > > >> > > > > > > > > >> +/* Return true if I's bits are consecutive ones from the MSB. */ > > >> +bool > > >> +aarch64_high_bits_all_ones_p (HOST_WIDE_INT i) > > >> +{ > > >> + return exact_log2(-i) != HOST_WIDE_INT_M1; > > >> +} > > > You need a space in here between the function name and the bracket: > > > > > > exact_log2 (-i) > > > > > > > > >> +extern void abort(void); > > > The same comment applies multiple places in this file. > > > > > > Likewise; if ( > > > > > > Otherwise, OK, please apply with those fixes. > > > > > > Thanks, > > > James > > > > Thanks for noticing that, here's the fixed version. > > > > Thanks Sam, I've committed the patch on your behalf with r264264. > If you want to get write-after-approval access to the SVN repo to commit patches yourself in the future > please fill out the form at https://sourceware.org/cgi-bin/pdw/ps_form.cgi putting my address from the MAINTAINERS file as the approver. > Hi, You've probably already noticed by now since you fixed the combine_bfi_1 issue introduced by this commit, but it add another regression: FAIL: gcc.target/aarch64/copysign-bsl.c scan-assembler b(sl|it|if)\tv[0-9] Christophe > Kyrill > > > Sam >