[PATCH] gcc/genflags.c: Improve error message

[PATCH] gcc/genflags.c: Improve error message

[Christophe Lyon]

When an iterator cannot be expanded, it is helpful to see the expanded
name which is causing problems.  It would be better to also print the
current iterator value (which couldn't match), but I couldn't find
how.

2021-03-01  Christophe Lyon  <christophe.lyon@linaro.org>

	gcc/
	* genflags.c (gen_insn): Print failed expansion string.
---
 gcc/genflags.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/genflags.c b/gcc/genflags.c
index f65b16a..a154b85 100644
--- a/gcc/genflags.c
+++ b/gcc/genflags.c
@@ -152,7 +152,7 @@ gen_insn (md_rtx_info *info)
   lt = strchr (name, '<');
   if (lt && strchr (lt + 1, '>'))
     {
-      error_at (info->loc, "unresolved iterator");
+      error_at (info->loc, "unresolved iterator in %s", name);
       return;
     }
 
@@ -160,7 +160,7 @@ gen_insn (md_rtx_info *info)
   if (lt || gt)
     {
       error_at (info->loc, "unmatched angle brackets, likely "
-		"an error in iterator syntax");
+		"an error in iterator syntax in %s", name);
       return;
     }
 
-- 
2.7.4

[PATCH] testsuite/arm: Improve mve-vshr.c

[Christophe Lyon]

Vector right shifts by immediate use vshr, while right shifts by
vectors instead use vneg and vshl.

This patch adds the corresponding scan-assembler-times that were
missing.

2021-04-22  Christophe Lyon  <christophe.lyon@linaro.org>

	gcc/testsuite/
	* gcc.target/arm/simd/mve-vshr.c: Add more scan-assembler-times.
---
 gcc/testsuite/gcc.target/arm/simd/mve-vshr.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c b/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c
index d4e658c..d4258e9 100644
--- a/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c
+++ b/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c
@@ -55,5 +55,12 @@ FUNC_IMM(u, uint, 8, 16, >>, vshrimm)
 
 /* MVE has only 128-bit vectors, so we can vectorize only half of the
    functions above.  */
+/* Vector right shifts use vneg and left shifts.  */
+/* { dg-final { scan-assembler-times {vshl.s[0-9]+\tq[0-9]+, q[0-9]+} 3 } } */
+/* { dg-final { scan-assembler-times {vshl.u[0-9]+\tq[0-9]+, q[0-9]+} 3 } } */
+/* { dg-final { scan-assembler-times {vneg.s[0-9]+  q[0-9]+, q[0-9]+} 6 } } */
+
+
+/* Shift by immediate.  */
 /* { dg-final { scan-assembler-times {vshr.s[0-9]+\tq[0-9]+, q[0-9]+} 3 } } */
 /* { dg-final { scan-assembler-times {vshr.u[0-9]+\tq[0-9]+, q[0-9]+} 3 } } */
-- 
2.7.4

[PATCH] testsuite/arm: Factorize and increase coverage in mve-sub_1.c

[Christophe Lyon]

Use a template macro to factorize the existing test functions.

This patch also adds a version to check subtraction with __fp16 type.

2021-04-26  Christophe Lyon  <christophe.lyon@linaro.org>

	gcc/testsuite/
	* gcc.target/arm/simd/mve-vsub_1.c: Factorize and add __fp16 test.
---
 gcc/testsuite/gcc.target/arm/simd/mve-vsub_1.c | 60 +++++++++-----------------
 1 file changed, 21 insertions(+), 39 deletions(-)

diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vsub_1.c b/gcc/testsuite/gcc.target/arm/simd/mve-vsub_1.c
index 842e5c6..5a6c345 100644
--- a/gcc/testsuite/gcc.target/arm/simd/mve-vsub_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/mve-vsub_1.c
@@ -5,60 +5,42 @@
 
 #include <stdint.h>
 
-void test_vsub_i32 (int32_t * dest, int32_t * a, int32_t * b) {
-  int i;
-  for (i=0; i<4; i++) {
-    dest[i] = a[i] - b[i];
-  }
+#define FUNC(SIGN, TYPE, BITS, NB, OP, NAME)				\
+  void test_ ## NAME ##_ ## SIGN ## BITS ## x ## NB (TYPE##BITS##_t * __restrict__ dest, \
+						     TYPE##BITS##_t *a, TYPE##BITS##_t *b) { \
+    int i;								\
+    for (i=0; i<NB; i++) {						\
+      dest[i] = a[i] OP b[i];						\
+    }									\
 }
 
-void test_vsub_i32_u (uint32_t * dest, uint32_t * a, uint32_t * b) {
-  int i;
-  for (i=0; i<4; i++) {
-    dest[i] = a[i] - b[i];
-  }
-}
+/* 128-bit vectors.  */
+FUNC(s, int, 32, 4, -, vsub)
+FUNC(u, uint, 32, 4, -, vsub)
+FUNC(s, int, 16, 8, -, vsub)
+FUNC(u, uint, 16, 8, -, vsub)
+FUNC(s, int, 8, 16, -, vsub)
+FUNC(u, uint, 8, 16, -, vsub)
 
 /* { dg-final { scan-assembler-times {vsub\.i32\tq[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
-
-void test_vsub_i16 (int16_t * dest, int16_t * a, int16_t * b) {
-  int i;
-  for (i=0; i<8; i++) {
-    dest[i] = a[i] - b[i];
-  }
-}
-
-void test_vsub_i16_u (uint16_t * dest, uint16_t * a, uint16_t * b) {
-  int i;
-  for (i=0; i<8; i++) {
-    dest[i] = a[i] - b[i];
-  }
-}
-
 /* { dg-final { scan-assembler-times {vsub\.i16\tq[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.i8\tq[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
 
-void test_vsub_i8 (int8_t * dest, int8_t * a, int8_t * b) {
-  int i;
-  for (i=0; i<16; i++) {
-    dest[i] = a[i] - b[i];
-  }
-}
-
-void test_vsub_i8_u (uint8_t * dest, uint8_t * a, uint8_t * b) {
+void test_vsub_f32 (float * dest, float * a, float * b) {
   int i;
-  for (i=0; i<16; i++) {
+  for (i=0; i<4; i++) {
     dest[i] = a[i] - b[i];
   }
 }
+/* { dg-final { scan-assembler-times {vsub\.f32\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } } */
 
-/* { dg-final { scan-assembler-times {vsub\.i8\tq[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
 
-void test_vsub_f32 (float * dest, float * a, float * b) {
+void test_vsub_f16 (__fp16 * dest, __fp16 * a, __fp16 * b) {
   int i;
-  for (i=0; i<4; i++) {
+  for (i=0; i<8; i++) {
     dest[i] = a[i] - b[i];
   }
 }
 
-/* { dg-final { scan-assembler-times {vsub\.f32\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsub\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } } */
 
-- 
2.7.4

[PATCH] testsuite/arm: Add mve-vadd-1.c test

[Christophe Lyon]

Support for vadd has been present for a while, but it was lacking a
test.

2021-04-22  Christophe Lyon  <christophe.lyon@linaro.org>

	gcc/testsuite/
	* gcc.target/arm/simd/mve-vadd-1.c: New.
---
 gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c | 43 ++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c

diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c b/gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c
new file mode 100644
index 0000000..15a9daa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O3" } */
+
+#include <stdint.h>
+
+#define FUNC(SIGN, TYPE, BITS, NB, OP, NAME)				\
+  void test_ ## NAME ##_ ## SIGN ## BITS ## x ## NB (TYPE##BITS##_t * __restrict__ dest, \
+						     TYPE##BITS##_t *a, TYPE##BITS##_t *b) { \
+    int i;								\
+    for (i=0; i<NB; i++) {						\
+      dest[i] = a[i] OP b[i];						\
+    }									\
+}
+
+/* 128-bit vectors.  */
+FUNC(s, int, 32, 4, +, vadd)
+FUNC(u, uint, 32, 4, +, vadd)
+FUNC(s, int, 16, 8, +, vadd)
+FUNC(u, uint, 16, 8, +, vadd)
+FUNC(s, int, 8, 16, +, vadd)
+FUNC(u, uint, 8, 16, +, vadd)
+
+/* { dg-final { scan-assembler-times {vadd\.i32  q[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vadd\.i16  q[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vadd\.i8  q[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
+
+void test_vadd_f32 (float * dest, float * a, float * b) {
+  int i;
+  for (i=0; i<4; i++) {
+    dest[i] = a[i] + b[i];
+  }
+}
+/* { dg-final { scan-assembler-times {vadd\.f32 q[0-9]+, q[0-9]+, q[0-9]+} 1 } } */
+
+void test_vadd_f16 (__fp16 * dest, __fp16 * a, __fp16 * b) {
+  int i;
+  for (i=0; i<8; i++) {
+    dest[i] = a[i] + b[i];
+  }
+}
+/* { dg-final { scan-assembler-times {vadd\.f16 q[0-9]+, q[0-9]+, q[0-9]+} 1 } } */
-- 
2.7.4

Re: [PATCH] testsuite/arm: Add mve-vadd-1.c test

[Prathamesh Kulkarni]

On Tue, 27 Apr 2021 at 17:02, Christophe Lyon via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> Support for vadd has been present for a while, but it was lacking a
> test.
>
> 2021-04-22  Christophe Lyon  <christophe.lyon@linaro.org>
>
>         gcc/testsuite/
>         * gcc.target/arm/simd/mve-vadd-1.c: New.
> ---
>  gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c | 43 ++++++++++++++++++++++++++
>  1 file changed, 43 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c
>
> diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c b/gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c
> new file mode 100644
> index 0000000..15a9daa
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c
> @@ -0,0 +1,43 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> +/* { dg-add-options arm_v8_1m_mve_fp } */
> +/* { dg-additional-options "-O3" } */
> +
> +#include <stdint.h>
> +
> +#define FUNC(SIGN, TYPE, BITS, NB, OP, NAME)                           \
> +  void test_ ## NAME ##_ ## SIGN ## BITS ## x ## NB (TYPE##BITS##_t * __restrict__ dest, \
> +                                                    TYPE##BITS##_t *a, TYPE##BITS##_t *b) { \
> +    int i;                                                             \
> +    for (i=0; i<NB; i++) {                                             \
> +      dest[i] = a[i] OP b[i];                                          \
> +    }                                                                  \
> +}
> +
> +/* 128-bit vectors.  */
> +FUNC(s, int, 32, 4, +, vadd)
> +FUNC(u, uint, 32, 4, +, vadd)
> +FUNC(s, int, 16, 8, +, vadd)
> +FUNC(u, uint, 16, 8, +, vadd)
> +FUNC(s, int, 8, 16, +, vadd)
> +FUNC(u, uint, 8, 16, +, vadd)
Sorry to nitpick -- just wondering if it'd be slightly better to add
another macro that will generate calls to FUNC with s, u variants ?

Sth like:
#define FUNC2(BITS, NB, OP, NAME) \
  FUNC(s, int, BITS, NB, OP, NAME) \
  FUNC(u, uint, BITS, NB, OP, NAME)

and use:
FUNC2(int, 32, 4, +, vadd)
FUNC2(int, 16, 8, + vadd)
FUNC2(int, 8, 16, +, vadd)

Thanks,
Prathamesh
> +
> +/* { dg-final { scan-assembler-times {vadd\.i32  q[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vadd\.i16  q[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vadd\.i8  q[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
> +
> +void test_vadd_f32 (float * dest, float * a, float * b) {
> +  int i;
> +  for (i=0; i<4; i++) {
> +    dest[i] = a[i] + b[i];
> +  }
> +}
> +/* { dg-final { scan-assembler-times {vadd\.f32 q[0-9]+, q[0-9]+, q[0-9]+} 1 } } */
> +
> +void test_vadd_f16 (__fp16 * dest, __fp16 * a, __fp16 * b) {
> +  int i;
> +  for (i=0; i<8; i++) {
> +    dest[i] = a[i] + b[i];
> +  }
> +}
> +/* { dg-final { scan-assembler-times {vadd\.f16 q[0-9]+, q[0-9]+, q[0-9]+} 1 } } */
> --
> 2.7.4
>

Re: [PATCH] testsuite/arm: Add mve-vadd-1.c test

[Christophe Lyon]

On Tue, 27 Apr 2021 at 14:04, Prathamesh Kulkarni
<prathamesh.kulkarni@linaro.org> wrote:
>
> On Tue, 27 Apr 2021 at 17:02, Christophe Lyon via Gcc-patches
> <gcc-patches@gcc.gnu.org> wrote:
> >
> > Support for vadd has been present for a while, but it was lacking a
> > test.
> >
> > 2021-04-22  Christophe Lyon  <christophe.lyon@linaro.org>
> >
> >         gcc/testsuite/
> >         * gcc.target/arm/simd/mve-vadd-1.c: New.
> > ---
> >  gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c | 43 ++++++++++++++++++++++++++
> >  1 file changed, 43 insertions(+)
> >  create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c
> >
> > diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c b/gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c
> > new file mode 100644
> > index 0000000..15a9daa
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c
> > @@ -0,0 +1,43 @@
> > +/* { dg-do compile } */
> > +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> > +/* { dg-add-options arm_v8_1m_mve_fp } */
> > +/* { dg-additional-options "-O3" } */
> > +
> > +#include <stdint.h>
> > +
> > +#define FUNC(SIGN, TYPE, BITS, NB, OP, NAME)                           \
> > +  void test_ ## NAME ##_ ## SIGN ## BITS ## x ## NB (TYPE##BITS##_t * __restrict__ dest, \
> > +                                                    TYPE##BITS##_t *a, TYPE##BITS##_t *b) { \
> > +    int i;                                                             \
> > +    for (i=0; i<NB; i++) {                                             \
> > +      dest[i] = a[i] OP b[i];                                          \
> > +    }                                                                  \
> > +}
> > +
> > +/* 128-bit vectors.  */
> > +FUNC(s, int, 32, 4, +, vadd)
> > +FUNC(u, uint, 32, 4, +, vadd)
> > +FUNC(s, int, 16, 8, +, vadd)
> > +FUNC(u, uint, 16, 8, +, vadd)
> > +FUNC(s, int, 8, 16, +, vadd)
> > +FUNC(u, uint, 8, 16, +, vadd)
> Sorry to nitpick -- just wondering if it'd be slightly better to add
> another macro that will generate calls to FUNC with s, u variants ?
>
> Sth like:
> #define FUNC2(BITS, NB, OP, NAME) \
>   FUNC(s, int, BITS, NB, OP, NAME) \
>   FUNC(u, uint, BITS, NB, OP, NAME)
>
> and use:
> FUNC2(int, 32, 4, +, vadd)
> FUNC2(int, 16, 8, + vadd)
> FUNC2(int, 8, 16, +, vadd)
>

Indeed we could do that, but several other mve-* tests use the same
pattern I used here.
Well, the ones I committed some time ago :-)
The advantage is that when suitable we can use the same FUNC to expand
the fp16 version.

I tend to prefer my proposal because it's more obvious to me which
types are used.

Christophe

> Thanks,
> Prathamesh
> > +
> > +/* { dg-final { scan-assembler-times {vadd\.i32  q[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
> > +/* { dg-final { scan-assembler-times {vadd\.i16  q[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
> > +/* { dg-final { scan-assembler-times {vadd\.i8  q[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
> > +
> > +void test_vadd_f32 (float * dest, float * a, float * b) {
> > +  int i;
> > +  for (i=0; i<4; i++) {
> > +    dest[i] = a[i] + b[i];
> > +  }
> > +}
> > +/* { dg-final { scan-assembler-times {vadd\.f32 q[0-9]+, q[0-9]+, q[0-9]+} 1 } } */
> > +
> > +void test_vadd_f16 (__fp16 * dest, __fp16 * a, __fp16 * b) {
> > +  int i;
> > +  for (i=0; i<8; i++) {
> > +    dest[i] = a[i] + b[i];
> > +  }
> > +}
> > +/* { dg-final { scan-assembler-times {vadd\.f16 q[0-9]+, q[0-9]+, q[0-9]+} 1 } } */
> > --
> > 2.7.4
> >

Re: [PATCH] gcc/genflags.c: Improve error message

[Richard Sandiford]

Christophe Lyon via Gcc-patches <gcc-patches@gcc.gnu.org> writes:
> When an iterator cannot be expanded, it is helpful to see the expanded
> name which is causing problems.  It would be better to also print the
> current iterator value (which couldn't match), but I couldn't find
> how.
>
> 2021-03-01  Christophe Lyon  <christophe.lyon@linaro.org>
>
> 	gcc/
> 	* genflags.c (gen_insn): Print failed expansion string.

OK, thanks.

Richard

> ---
>  gcc/genflags.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/genflags.c b/gcc/genflags.c
> index f65b16a..a154b85 100644
> --- a/gcc/genflags.c
> +++ b/gcc/genflags.c
> @@ -152,7 +152,7 @@ gen_insn (md_rtx_info *info)
>    lt = strchr (name, '<');
>    if (lt && strchr (lt + 1, '>'))
>      {
> -      error_at (info->loc, "unresolved iterator");
> +      error_at (info->loc, "unresolved iterator in %s", name);
>        return;
>      }
>  
> @@ -160,7 +160,7 @@ gen_insn (md_rtx_info *info)
>    if (lt || gt)
>      {
>        error_at (info->loc, "unmatched angle brackets, likely "
> -		"an error in iterator syntax");
> +		"an error in iterator syntax in %s", name);
>        return;
>      }

Re: [PATCH] gcc/genflags.c: Improve error message

[Jeff Law]

On 4/27/2021 5:32 AM, Christophe Lyon via Gcc-patches wrote:
> When an iterator cannot be expanded, it is helpful to see the expanded
> name which is causing problems.  It would be better to also print the
> current iterator value (which couldn't match), but I couldn't find
> how.
>
> 2021-03-01  Christophe Lyon  <christophe.lyon@linaro.org>
>
> 	gcc/
> 	* genflags.c (gen_insn): Print failed expansion string.

OK

jeff

Re: [PATCH] testsuite/arm: Add mve-vadd-1.c test

[Christophe Lyon]

Ping?

On Tue, 27 Apr 2021 at 13:32, Christophe Lyon
<christophe.lyon@linaro.org> wrote:
>
> Support for vadd has been present for a while, but it was lacking a
> test.
>
> 2021-04-22  Christophe Lyon  <christophe.lyon@linaro.org>
>
>         gcc/testsuite/
>         * gcc.target/arm/simd/mve-vadd-1.c: New.
> ---
>  gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c | 43 ++++++++++++++++++++++++++
>  1 file changed, 43 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c
>
> diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c b/gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c
> new file mode 100644
> index 0000000..15a9daa
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c
> @@ -0,0 +1,43 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> +/* { dg-add-options arm_v8_1m_mve_fp } */
> +/* { dg-additional-options "-O3" } */
> +
> +#include <stdint.h>
> +
> +#define FUNC(SIGN, TYPE, BITS, NB, OP, NAME)                           \
> +  void test_ ## NAME ##_ ## SIGN ## BITS ## x ## NB (TYPE##BITS##_t * __restrict__ dest, \
> +                                                    TYPE##BITS##_t *a, TYPE##BITS##_t *b) { \
> +    int i;                                                             \
> +    for (i=0; i<NB; i++) {                                             \
> +      dest[i] = a[i] OP b[i];                                          \
> +    }                                                                  \
> +}
> +
> +/* 128-bit vectors.  */
> +FUNC(s, int, 32, 4, +, vadd)
> +FUNC(u, uint, 32, 4, +, vadd)
> +FUNC(s, int, 16, 8, +, vadd)
> +FUNC(u, uint, 16, 8, +, vadd)
> +FUNC(s, int, 8, 16, +, vadd)
> +FUNC(u, uint, 8, 16, +, vadd)
> +
> +/* { dg-final { scan-assembler-times {vadd\.i32  q[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vadd\.i16  q[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vadd\.i8  q[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
> +
> +void test_vadd_f32 (float * dest, float * a, float * b) {
> +  int i;
> +  for (i=0; i<4; i++) {
> +    dest[i] = a[i] + b[i];
> +  }
> +}
> +/* { dg-final { scan-assembler-times {vadd\.f32 q[0-9]+, q[0-9]+, q[0-9]+} 1 } } */
> +
> +void test_vadd_f16 (__fp16 * dest, __fp16 * a, __fp16 * b) {
> +  int i;
> +  for (i=0; i<8; i++) {
> +    dest[i] = a[i] + b[i];
> +  }
> +}
> +/* { dg-final { scan-assembler-times {vadd\.f16 q[0-9]+, q[0-9]+, q[0-9]+} 1 } } */
> --
> 2.7.4
>

Re: [PATCH] testsuite/arm: Factorize and increase coverage in mve-sub_1.c

[Christophe Lyon]

Ping?

On Tue, 27 Apr 2021 at 13:32, Christophe Lyon
<christophe.lyon@linaro.org> wrote:
>
> Use a template macro to factorize the existing test functions.
>
> This patch also adds a version to check subtraction with __fp16 type.
>
> 2021-04-26  Christophe Lyon  <christophe.lyon@linaro.org>
>
>         gcc/testsuite/
>         * gcc.target/arm/simd/mve-vsub_1.c: Factorize and add __fp16 test.
> ---
>  gcc/testsuite/gcc.target/arm/simd/mve-vsub_1.c | 60 +++++++++-----------------
>  1 file changed, 21 insertions(+), 39 deletions(-)
>
> diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vsub_1.c b/gcc/testsuite/gcc.target/arm/simd/mve-vsub_1.c
> index 842e5c6..5a6c345 100644
> --- a/gcc/testsuite/gcc.target/arm/simd/mve-vsub_1.c
> +++ b/gcc/testsuite/gcc.target/arm/simd/mve-vsub_1.c
> @@ -5,60 +5,42 @@
>
>  #include <stdint.h>
>
> -void test_vsub_i32 (int32_t * dest, int32_t * a, int32_t * b) {
> -  int i;
> -  for (i=0; i<4; i++) {
> -    dest[i] = a[i] - b[i];
> -  }
> +#define FUNC(SIGN, TYPE, BITS, NB, OP, NAME)                           \
> +  void test_ ## NAME ##_ ## SIGN ## BITS ## x ## NB (TYPE##BITS##_t * __restrict__ dest, \
> +                                                    TYPE##BITS##_t *a, TYPE##BITS##_t *b) { \
> +    int i;                                                             \
> +    for (i=0; i<NB; i++) {                                             \
> +      dest[i] = a[i] OP b[i];                                          \
> +    }                                                                  \
>  }
>
> -void test_vsub_i32_u (uint32_t * dest, uint32_t * a, uint32_t * b) {
> -  int i;
> -  for (i=0; i<4; i++) {
> -    dest[i] = a[i] - b[i];
> -  }
> -}
> +/* 128-bit vectors.  */
> +FUNC(s, int, 32, 4, -, vsub)
> +FUNC(u, uint, 32, 4, -, vsub)
> +FUNC(s, int, 16, 8, -, vsub)
> +FUNC(u, uint, 16, 8, -, vsub)
> +FUNC(s, int, 8, 16, -, vsub)
> +FUNC(u, uint, 8, 16, -, vsub)
>
>  /* { dg-final { scan-assembler-times {vsub\.i32\tq[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
> -
> -void test_vsub_i16 (int16_t * dest, int16_t * a, int16_t * b) {
> -  int i;
> -  for (i=0; i<8; i++) {
> -    dest[i] = a[i] - b[i];
> -  }
> -}
> -
> -void test_vsub_i16_u (uint16_t * dest, uint16_t * a, uint16_t * b) {
> -  int i;
> -  for (i=0; i<8; i++) {
> -    dest[i] = a[i] - b[i];
> -  }
> -}
> -
>  /* { dg-final { scan-assembler-times {vsub\.i16\tq[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsub\.i8\tq[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
>
> -void test_vsub_i8 (int8_t * dest, int8_t * a, int8_t * b) {
> -  int i;
> -  for (i=0; i<16; i++) {
> -    dest[i] = a[i] - b[i];
> -  }
> -}
> -
> -void test_vsub_i8_u (uint8_t * dest, uint8_t * a, uint8_t * b) {
> +void test_vsub_f32 (float * dest, float * a, float * b) {
>    int i;
> -  for (i=0; i<16; i++) {
> +  for (i=0; i<4; i++) {
>      dest[i] = a[i] - b[i];
>    }
>  }
> +/* { dg-final { scan-assembler-times {vsub\.f32\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } } */
>
> -/* { dg-final { scan-assembler-times {vsub\.i8\tq[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
>
> -void test_vsub_f32 (float * dest, float * a, float * b) {
> +void test_vsub_f16 (__fp16 * dest, __fp16 * a, __fp16 * b) {
>    int i;
> -  for (i=0; i<4; i++) {
> +  for (i=0; i<8; i++) {
>      dest[i] = a[i] - b[i];
>    }
>  }
>
> -/* { dg-final { scan-assembler-times {vsub\.f32\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsub\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } } */
>
> --
> 2.7.4
>

Re: [PATCH] testsuite/arm: Improve mve-vshr.c

[Christophe Lyon]

Ping?

On Tue, 27 Apr 2021 at 13:32, Christophe Lyon
<christophe.lyon@linaro.org> wrote:
>
> Vector right shifts by immediate use vshr, while right shifts by
> vectors instead use vneg and vshl.
>
> This patch adds the corresponding scan-assembler-times that were
> missing.
>
> 2021-04-22  Christophe Lyon  <christophe.lyon@linaro.org>
>
>         gcc/testsuite/
>         * gcc.target/arm/simd/mve-vshr.c: Add more scan-assembler-times.
> ---
>  gcc/testsuite/gcc.target/arm/simd/mve-vshr.c | 7 +++++++
>  1 file changed, 7 insertions(+)
>
> diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c b/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c
> index d4e658c..d4258e9 100644
> --- a/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c
> +++ b/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c
> @@ -55,5 +55,12 @@ FUNC_IMM(u, uint, 8, 16, >>, vshrimm)
>
>  /* MVE has only 128-bit vectors, so we can vectorize only half of the
>     functions above.  */
> +/* Vector right shifts use vneg and left shifts.  */
> +/* { dg-final { scan-assembler-times {vshl.s[0-9]+\tq[0-9]+, q[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vshl.u[0-9]+\tq[0-9]+, q[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vneg.s[0-9]+  q[0-9]+, q[0-9]+} 6 } } */
> +
> +
> +/* Shift by immediate.  */
>  /* { dg-final { scan-assembler-times {vshr.s[0-9]+\tq[0-9]+, q[0-9]+} 3 } } */
>  /* { dg-final { scan-assembler-times {vshr.u[0-9]+\tq[0-9]+, q[0-9]+} 3 } } */
> --
> 2.7.4
>

Re: [PATCH] testsuite/arm: Improve mve-vshr.c

[Christophe Lyon]

ping?

On Mon, 10 May 2021 at 13:22, Christophe Lyon
<christophe.lyon@linaro.org> wrote:
>
> Ping?
>
> On Tue, 27 Apr 2021 at 13:32, Christophe Lyon
> <christophe.lyon@linaro.org> wrote:
> >
> > Vector right shifts by immediate use vshr, while right shifts by
> > vectors instead use vneg and vshl.
> >
> > This patch adds the corresponding scan-assembler-times that were
> > missing.
> >
> > 2021-04-22  Christophe Lyon  <christophe.lyon@linaro.org>
> >
> >         gcc/testsuite/
> >         * gcc.target/arm/simd/mve-vshr.c: Add more scan-assembler-times.
> > ---
> >  gcc/testsuite/gcc.target/arm/simd/mve-vshr.c | 7 +++++++
> >  1 file changed, 7 insertions(+)
> >
> > diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c b/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c
> > index d4e658c..d4258e9 100644
> > --- a/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c
> > +++ b/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c
> > @@ -55,5 +55,12 @@ FUNC_IMM(u, uint, 8, 16, >>, vshrimm)
> >
> >  /* MVE has only 128-bit vectors, so we can vectorize only half of the
> >     functions above.  */
> > +/* Vector right shifts use vneg and left shifts.  */
> > +/* { dg-final { scan-assembler-times {vshl.s[0-9]+\tq[0-9]+, q[0-9]+} 3 } } */
> > +/* { dg-final { scan-assembler-times {vshl.u[0-9]+\tq[0-9]+, q[0-9]+} 3 } } */
> > +/* { dg-final { scan-assembler-times {vneg.s[0-9]+  q[0-9]+, q[0-9]+} 6 } } */
> > +
> > +
> > +/* Shift by immediate.  */
> >  /* { dg-final { scan-assembler-times {vshr.s[0-9]+\tq[0-9]+, q[0-9]+} 3 } } */
> >  /* { dg-final { scan-assembler-times {vshr.u[0-9]+\tq[0-9]+, q[0-9]+} 3 } } */
> > --
> > 2.7.4
> >

Re: [PATCH] testsuite/arm: Factorize and increase coverage in mve-sub_1.c

[Christophe Lyon]

ping?

On Mon, 10 May 2021 at 13:22, Christophe Lyon
<christophe.lyon@linaro.org> wrote:
>
> Ping?
>
> On Tue, 27 Apr 2021 at 13:32, Christophe Lyon
> <christophe.lyon@linaro.org> wrote:
> >
> > Use a template macro to factorize the existing test functions.
> >
> > This patch also adds a version to check subtraction with __fp16 type.
> >
> > 2021-04-26  Christophe Lyon  <christophe.lyon@linaro.org>
> >
> >         gcc/testsuite/
> >         * gcc.target/arm/simd/mve-vsub_1.c: Factorize and add __fp16 test.
> > ---
> >  gcc/testsuite/gcc.target/arm/simd/mve-vsub_1.c | 60 +++++++++-----------------
> >  1 file changed, 21 insertions(+), 39 deletions(-)
> >
> > diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vsub_1.c b/gcc/testsuite/gcc.target/arm/simd/mve-vsub_1.c
> > index 842e5c6..5a6c345 100644
> > --- a/gcc/testsuite/gcc.target/arm/simd/mve-vsub_1.c
> > +++ b/gcc/testsuite/gcc.target/arm/simd/mve-vsub_1.c
> > @@ -5,60 +5,42 @@
> >
> >  #include <stdint.h>
> >
> > -void test_vsub_i32 (int32_t * dest, int32_t * a, int32_t * b) {
> > -  int i;
> > -  for (i=0; i<4; i++) {
> > -    dest[i] = a[i] - b[i];
> > -  }
> > +#define FUNC(SIGN, TYPE, BITS, NB, OP, NAME)                           \
> > +  void test_ ## NAME ##_ ## SIGN ## BITS ## x ## NB (TYPE##BITS##_t * __restrict__ dest, \
> > +                                                    TYPE##BITS##_t *a, TYPE##BITS##_t *b) { \
> > +    int i;                                                             \
> > +    for (i=0; i<NB; i++) {                                             \
> > +      dest[i] = a[i] OP b[i];                                          \
> > +    }                                                                  \
> >  }
> >
> > -void test_vsub_i32_u (uint32_t * dest, uint32_t * a, uint32_t * b) {
> > -  int i;
> > -  for (i=0; i<4; i++) {
> > -    dest[i] = a[i] - b[i];
> > -  }
> > -}
> > +/* 128-bit vectors.  */
> > +FUNC(s, int, 32, 4, -, vsub)
> > +FUNC(u, uint, 32, 4, -, vsub)
> > +FUNC(s, int, 16, 8, -, vsub)
> > +FUNC(u, uint, 16, 8, -, vsub)
> > +FUNC(s, int, 8, 16, -, vsub)
> > +FUNC(u, uint, 8, 16, -, vsub)
> >
> >  /* { dg-final { scan-assembler-times {vsub\.i32\tq[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
> > -
> > -void test_vsub_i16 (int16_t * dest, int16_t * a, int16_t * b) {
> > -  int i;
> > -  for (i=0; i<8; i++) {
> > -    dest[i] = a[i] - b[i];
> > -  }
> > -}
> > -
> > -void test_vsub_i16_u (uint16_t * dest, uint16_t * a, uint16_t * b) {
> > -  int i;
> > -  for (i=0; i<8; i++) {
> > -    dest[i] = a[i] - b[i];
> > -  }
> > -}
> > -
> >  /* { dg-final { scan-assembler-times {vsub\.i16\tq[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
> > +/* { dg-final { scan-assembler-times {vsub\.i8\tq[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
> >
> > -void test_vsub_i8 (int8_t * dest, int8_t * a, int8_t * b) {
> > -  int i;
> > -  for (i=0; i<16; i++) {
> > -    dest[i] = a[i] - b[i];
> > -  }
> > -}
> > -
> > -void test_vsub_i8_u (uint8_t * dest, uint8_t * a, uint8_t * b) {
> > +void test_vsub_f32 (float * dest, float * a, float * b) {
> >    int i;
> > -  for (i=0; i<16; i++) {
> > +  for (i=0; i<4; i++) {
> >      dest[i] = a[i] - b[i];
> >    }
> >  }
> > +/* { dg-final { scan-assembler-times {vsub\.f32\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } } */
> >
> > -/* { dg-final { scan-assembler-times {vsub\.i8\tq[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
> >
> > -void test_vsub_f32 (float * dest, float * a, float * b) {
> > +void test_vsub_f16 (__fp16 * dest, __fp16 * a, __fp16 * b) {
> >    int i;
> > -  for (i=0; i<4; i++) {
> > +  for (i=0; i<8; i++) {
> >      dest[i] = a[i] - b[i];
> >    }
> >  }
> >
> > -/* { dg-final { scan-assembler-times {vsub\.f32\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } } */
> > +/* { dg-final { scan-assembler-times {vsub\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } } */
> >
> > --
> > 2.7.4
> >

Re: [PATCH] testsuite/arm: Add mve-vadd-1.c test

[Christophe Lyon]

ping?

On Mon, 10 May 2021 at 13:22, Christophe Lyon
<christophe.lyon@linaro.org> wrote:
>
> Ping?
>
> On Tue, 27 Apr 2021 at 13:32, Christophe Lyon
> <christophe.lyon@linaro.org> wrote:
> >
> > Support for vadd has been present for a while, but it was lacking a
> > test.
> >
> > 2021-04-22  Christophe Lyon  <christophe.lyon@linaro.org>
> >
> >         gcc/testsuite/
> >         * gcc.target/arm/simd/mve-vadd-1.c: New.
> > ---
> >  gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c | 43 ++++++++++++++++++++++++++
> >  1 file changed, 43 insertions(+)
> >  create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c
> >
> > diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c b/gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c
> > new file mode 100644
> > index 0000000..15a9daa
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c
> > @@ -0,0 +1,43 @@
> > +/* { dg-do compile } */
> > +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> > +/* { dg-add-options arm_v8_1m_mve_fp } */
> > +/* { dg-additional-options "-O3" } */
> > +
> > +#include <stdint.h>
> > +
> > +#define FUNC(SIGN, TYPE, BITS, NB, OP, NAME)                           \
> > +  void test_ ## NAME ##_ ## SIGN ## BITS ## x ## NB (TYPE##BITS##_t * __restrict__ dest, \
> > +                                                    TYPE##BITS##_t *a, TYPE##BITS##_t *b) { \
> > +    int i;                                                             \
> > +    for (i=0; i<NB; i++) {                                             \
> > +      dest[i] = a[i] OP b[i];                                          \
> > +    }                                                                  \
> > +}
> > +
> > +/* 128-bit vectors.  */
> > +FUNC(s, int, 32, 4, +, vadd)
> > +FUNC(u, uint, 32, 4, +, vadd)
> > +FUNC(s, int, 16, 8, +, vadd)
> > +FUNC(u, uint, 16, 8, +, vadd)
> > +FUNC(s, int, 8, 16, +, vadd)
> > +FUNC(u, uint, 8, 16, +, vadd)
> > +
> > +/* { dg-final { scan-assembler-times {vadd\.i32  q[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
> > +/* { dg-final { scan-assembler-times {vadd\.i16  q[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
> > +/* { dg-final { scan-assembler-times {vadd\.i8  q[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
> > +
> > +void test_vadd_f32 (float * dest, float * a, float * b) {
> > +  int i;
> > +  for (i=0; i<4; i++) {
> > +    dest[i] = a[i] + b[i];
> > +  }
> > +}
> > +/* { dg-final { scan-assembler-times {vadd\.f32 q[0-9]+, q[0-9]+, q[0-9]+} 1 } } */
> > +
> > +void test_vadd_f16 (__fp16 * dest, __fp16 * a, __fp16 * b) {
> > +  int i;
> > +  for (i=0; i<8; i++) {
> > +    dest[i] = a[i] + b[i];
> > +  }
> > +}
> > +/* { dg-final { scan-assembler-times {vadd\.f16 q[0-9]+, q[0-9]+, q[0-9]+} 1 } } */
> > --
> > 2.7.4
> >

RE: [PATCH] testsuite/arm: Improve mve-vshr.c

[Kyrylo Tkachov]

> -----Original Message-----
> From: Gcc-patches <gcc-patches-bounces@gcc.gnu.org> On Behalf Of
> Christophe Lyon via Gcc-patches
> Sent: 17 May 2021 10:54
> To: gcc Patches <gcc-patches@gcc.gnu.org>
> Subject: Re: [PATCH] testsuite/arm: Improve mve-vshr.c
> 
> ping?
> 
> On Mon, 10 May 2021 at 13:22, Christophe Lyon
> <christophe.lyon@linaro.org> wrote:
> >
> > Ping?
> >
> > On Tue, 27 Apr 2021 at 13:32, Christophe Lyon
> > <christophe.lyon@linaro.org> wrote:
> > >
> > > Vector right shifts by immediate use vshr, while right shifts by
> > > vectors instead use vneg and vshl.
> > >
> > > This patch adds the corresponding scan-assembler-times that were
> > > missing.
> > >

Ok.
Thanks,
Kyrill

> > > 2021-04-22  Christophe Lyon  <christophe.lyon@linaro.org>
> > >
> > >         gcc/testsuite/
> > >         * gcc.target/arm/simd/mve-vshr.c: Add more scan-assembler-times.
> > > ---
> > >  gcc/testsuite/gcc.target/arm/simd/mve-vshr.c | 7 +++++++
> > >  1 file changed, 7 insertions(+)
> > >
> > > diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c
> b/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c
> > > index d4e658c..d4258e9 100644
> > > --- a/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c
> > > +++ b/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c
> > > @@ -55,5 +55,12 @@ FUNC_IMM(u, uint, 8, 16, >>, vshrimm)
> > >
> > >  /* MVE has only 128-bit vectors, so we can vectorize only half of the
> > >     functions above.  */
> > > +/* Vector right shifts use vneg and left shifts.  */
> > > +/* { dg-final { scan-assembler-times {vshl.s[0-9]+\tq[0-9]+, q[0-9]+} 3 } }
> */
> > > +/* { dg-final { scan-assembler-times {vshl.u[0-9]+\tq[0-9]+, q[0-9]+} 3 } }
> */
> > > +/* { dg-final { scan-assembler-times {vneg.s[0-9]+  q[0-9]+, q[0-9]+} 6 } }
> */
> > > +
> > > +
> > > +/* Shift by immediate.  */
> > >  /* { dg-final { scan-assembler-times {vshr.s[0-9]+\tq[0-9]+, q[0-9]+} 3 } }
> */
> > >  /* { dg-final { scan-assembler-times {vshr.u[0-9]+\tq[0-9]+, q[0-9]+} 3 } }
> */
> > > --
> > > 2.7.4
> > >

RE: [PATCH] testsuite/arm: Factorize and increase coverage in mve-sub_1.c

[Kyrylo Tkachov]

> -----Original Message-----
> From: Gcc-patches <gcc-patches-bounces@gcc.gnu.org> On Behalf Of
> Christophe Lyon via Gcc-patches
> Sent: 17 May 2021 10:54
> To: gcc Patches <gcc-patches@gcc.gnu.org>
> Subject: Re: [PATCH] testsuite/arm: Factorize and increase coverage in mve-
> sub_1.c
> 
> ping?
> 
> On Mon, 10 May 2021 at 13:22, Christophe Lyon
> <christophe.lyon@linaro.org> wrote:
> >
> > Ping?
> >
> > On Tue, 27 Apr 2021 at 13:32, Christophe Lyon
> > <christophe.lyon@linaro.org> wrote:
> > >
> > > Use a template macro to factorize the existing test functions.
> > >
> > > This patch also adds a version to check subtraction with __fp16 type.
> > >

Ok.
Thanks,
Kyrill

> > > 2021-04-26  Christophe Lyon  <christophe.lyon@linaro.org>
> > >
> > >         gcc/testsuite/
> > >         * gcc.target/arm/simd/mve-vsub_1.c: Factorize and add __fp16 test.
> > > ---
> > >  gcc/testsuite/gcc.target/arm/simd/mve-vsub_1.c | 60 +++++++++--------
> ---------
> > >  1 file changed, 21 insertions(+), 39 deletions(-)
> > >
> > > diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vsub_1.c
> b/gcc/testsuite/gcc.target/arm/simd/mve-vsub_1.c
> > > index 842e5c6..5a6c345 100644
> > > --- a/gcc/testsuite/gcc.target/arm/simd/mve-vsub_1.c
> > > +++ b/gcc/testsuite/gcc.target/arm/simd/mve-vsub_1.c
> > > @@ -5,60 +5,42 @@
> > >
> > >  #include <stdint.h>
> > >
> > > -void test_vsub_i32 (int32_t * dest, int32_t * a, int32_t * b) {
> > > -  int i;
> > > -  for (i=0; i<4; i++) {
> > > -    dest[i] = a[i] - b[i];
> > > -  }
> > > +#define FUNC(SIGN, TYPE, BITS, NB, OP, NAME)                           \
> > > +  void test_ ## NAME ##_ ## SIGN ## BITS ## x ## NB (TYPE##BITS##_t *
> __restrict__ dest, \
> > > +                                                    TYPE##BITS##_t *a, TYPE##BITS##_t *b) { \
> > > +    int i;                                                             \
> > > +    for (i=0; i<NB; i++) {                                             \
> > > +      dest[i] = a[i] OP b[i];                                          \
> > > +    }                                                                  \
> > >  }
> > >
> > > -void test_vsub_i32_u (uint32_t * dest, uint32_t * a, uint32_t * b) {
> > > -  int i;
> > > -  for (i=0; i<4; i++) {
> > > -    dest[i] = a[i] - b[i];
> > > -  }
> > > -}
> > > +/* 128-bit vectors.  */
> > > +FUNC(s, int, 32, 4, -, vsub)
> > > +FUNC(u, uint, 32, 4, -, vsub)
> > > +FUNC(s, int, 16, 8, -, vsub)
> > > +FUNC(u, uint, 16, 8, -, vsub)
> > > +FUNC(s, int, 8, 16, -, vsub)
> > > +FUNC(u, uint, 8, 16, -, vsub)
> > >
> > >  /* { dg-final { scan-assembler-times {vsub\.i32\tq[0-9]+, q[0-9]+, q[0-9]+}
> 2 } } */
> > > -
> > > -void test_vsub_i16 (int16_t * dest, int16_t * a, int16_t * b) {
> > > -  int i;
> > > -  for (i=0; i<8; i++) {
> > > -    dest[i] = a[i] - b[i];
> > > -  }
> > > -}
> > > -
> > > -void test_vsub_i16_u (uint16_t * dest, uint16_t * a, uint16_t * b) {
> > > -  int i;
> > > -  for (i=0; i<8; i++) {
> > > -    dest[i] = a[i] - b[i];
> > > -  }
> > > -}
> > > -
> > >  /* { dg-final { scan-assembler-times {vsub\.i16\tq[0-9]+, q[0-9]+, q[0-9]+}
> 2 } } */
> > > +/* { dg-final { scan-assembler-times {vsub\.i8\tq[0-9]+, q[0-9]+, q[0-9]+}
> 2 } } */
> > >
> > > -void test_vsub_i8 (int8_t * dest, int8_t * a, int8_t * b) {
> > > -  int i;
> > > -  for (i=0; i<16; i++) {
> > > -    dest[i] = a[i] - b[i];
> > > -  }
> > > -}
> > > -
> > > -void test_vsub_i8_u (uint8_t * dest, uint8_t * a, uint8_t * b) {
> > > +void test_vsub_f32 (float * dest, float * a, float * b) {
> > >    int i;
> > > -  for (i=0; i<16; i++) {
> > > +  for (i=0; i<4; i++) {
> > >      dest[i] = a[i] - b[i];
> > >    }
> > >  }
> > > +/* { dg-final { scan-assembler-times {vsub\.f32\tq[0-9]+, q[0-9]+, q[0-
> 9]+} 1 } } */
> > >
> > > -/* { dg-final { scan-assembler-times {vsub\.i8\tq[0-9]+, q[0-9]+, q[0-9]+}
> 2 } } */
> > >
> > > -void test_vsub_f32 (float * dest, float * a, float * b) {
> > > +void test_vsub_f16 (__fp16 * dest, __fp16 * a, __fp16 * b) {
> > >    int i;
> > > -  for (i=0; i<4; i++) {
> > > +  for (i=0; i<8; i++) {
> > >      dest[i] = a[i] - b[i];
> > >    }
> > >  }
> > >
> > > -/* { dg-final { scan-assembler-times {vsub\.f32\tq[0-9]+, q[0-9]+, q[0-9]+}
> 1 } } */
> > > +/* { dg-final { scan-assembler-times {vsub\.f16\tq[0-9]+, q[0-9]+, q[0-
> 9]+} 1 } } */
> > >
> > > --
> > > 2.7.4
> > >

RE: [PATCH] testsuite/arm: Add mve-vadd-1.c test

[Kyrylo Tkachov]

> -----Original Message-----
> From: Gcc-patches <gcc-patches-bounces@gcc.gnu.org> On Behalf Of
> Christophe Lyon via Gcc-patches
> Sent: 17 May 2021 10:54
> To: gcc Patches <gcc-patches@gcc.gnu.org>
> Subject: Re: [PATCH] testsuite/arm: Add mve-vadd-1.c test
> 
> ping?
> 
> On Mon, 10 May 2021 at 13:22, Christophe Lyon
> <christophe.lyon@linaro.org> wrote:
> >
> > Ping?
> >
> > On Tue, 27 Apr 2021 at 13:32, Christophe Lyon
> > <christophe.lyon@linaro.org> wrote:
> > >
> > > Support for vadd has been present for a while, but it was lacking a
> > > test.
> > >

Ok.
Thanks,
Kyrill

> > > 2021-04-22  Christophe Lyon  <christophe.lyon@linaro.org>
> > >
> > >         gcc/testsuite/
> > >         * gcc.target/arm/simd/mve-vadd-1.c: New.
> > > ---
> > >  gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c | 43
> ++++++++++++++++++++++++++
> > >  1 file changed, 43 insertions(+)
> > >  create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c
> > >
> > > diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c
> b/gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c
> > > new file mode 100644
> > > index 0000000..15a9daa
> > > --- /dev/null
> > > +++ b/gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c
> > > @@ -0,0 +1,43 @@
> > > +/* { dg-do compile } */
> > > +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> > > +/* { dg-add-options arm_v8_1m_mve_fp } */
> > > +/* { dg-additional-options "-O3" } */
> > > +
> > > +#include <stdint.h>
> > > +
> > > +#define FUNC(SIGN, TYPE, BITS, NB, OP, NAME)                           \
> > > +  void test_ ## NAME ##_ ## SIGN ## BITS ## x ## NB (TYPE##BITS##_t *
> __restrict__ dest, \
> > > +                                                    TYPE##BITS##_t *a, TYPE##BITS##_t *b) { \
> > > +    int i;                                                             \
> > > +    for (i=0; i<NB; i++) {                                             \
> > > +      dest[i] = a[i] OP b[i];                                          \
> > > +    }                                                                  \
> > > +}
> > > +
> > > +/* 128-bit vectors.  */
> > > +FUNC(s, int, 32, 4, +, vadd)
> > > +FUNC(u, uint, 32, 4, +, vadd)
> > > +FUNC(s, int, 16, 8, +, vadd)
> > > +FUNC(u, uint, 16, 8, +, vadd)
> > > +FUNC(s, int, 8, 16, +, vadd)
> > > +FUNC(u, uint, 8, 16, +, vadd)
> > > +
> > > +/* { dg-final { scan-assembler-times {vadd\.i32  q[0-9]+, q[0-9]+, q[0-9]+}
> 2 } } */
> > > +/* { dg-final { scan-assembler-times {vadd\.i16  q[0-9]+, q[0-9]+, q[0-9]+}
> 2 } } */
> > > +/* { dg-final { scan-assembler-times {vadd\.i8  q[0-9]+, q[0-9]+, q[0-9]+}
> 2 } } */
> > > +
> > > +void test_vadd_f32 (float * dest, float * a, float * b) {
> > > +  int i;
> > > +  for (i=0; i<4; i++) {
> > > +    dest[i] = a[i] + b[i];
> > > +  }
> > > +}
> > > +/* { dg-final { scan-assembler-times {vadd\.f32 q[0-9]+, q[0-9]+, q[0-9]+}
> 1 } } */
> > > +
> > > +void test_vadd_f16 (__fp16 * dest, __fp16 * a, __fp16 * b) {
> > > +  int i;
> > > +  for (i=0; i<8; i++) {
> > > +    dest[i] = a[i] + b[i];
> > > +  }
> > > +}
> > > +/* { dg-final { scan-assembler-times {vadd\.f16 q[0-9]+, q[0-9]+, q[0-9]+}
> 1 } } */
> > > --
> > > 2.7.4
> > >