From: Christophe Lyon <christophe.lyon@linaro.org>
To: gcc Patches <gcc-patches@gcc.gnu.org>,
nick clifton <nickc@redhat.com>,
Richard Earnshaw <richard.earnshaw@arm.com>,
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>,
Kyrylo Tkachov <kyrylo.tkachov@arm.com>,
Richard Sandiford <richard.sandiford@arm.com>
Subject: Re: [PATCH] arm: Add a couple of extra stack-protector tests
Date: Mon, 28 Sep 2020 21:57:14 +0200 [thread overview]
Message-ID: <CAKdteOZp51Hw_wyQ4tHaBS3Ca2oS9g1xD1ksYXG_p=sDbqTo5g@mail.gmail.com> (raw)
In-Reply-To: <mptr1qse41l.fsf@arm.com>
On Wed, 23 Sep 2020 at 20:33, Richard Sandiford
<richard.sandiford@arm.com> wrote:
>
> These tests were inspired by the corresponding aarch64 ones that I just
> committed. They already pass.
>
> Tested on arm-linux-gnueabi, arm-linux-gnueabihf and armeb-eabi.
> OK for trunk?
>
> Richard
>
>
> gcc/testsuite/
> * gcc.target/arm/stack-protector-5.c: New test.
> * gcc.target/arm/stack-protector-6.c: Likewise.
> ---
Hi Richard,
These new tests fail when compiling for cortex-a15 and cortex-a57...
There are 2 "str" instructions generated, the code is much longer than
for cortex-a9 for instance.
They pass with cortex-a9, cortex-a5 and arm10tdmi.
Christophe
> .../gcc.target/arm/stack-protector-5.c | 21 +++++++++++++++++++
> .../gcc.target/arm/stack-protector-6.c | 8 +++++++
> 2 files changed, 29 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/arm/stack-protector-5.c
> create mode 100644 gcc/testsuite/gcc.target/arm/stack-protector-6.c
>
> diff --git a/gcc/testsuite/gcc.target/arm/stack-protector-5.c b/gcc/testsuite/gcc.target/arm/stack-protector-5.c
> new file mode 100644
> index 00000000000..b808b11aa3d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/stack-protector-5.c
> @@ -0,0 +1,21 @@
> +/* { dg-do compile } */
> +/* { dg-options "-fstack-protector-all -O2" } */
> +
> +void __attribute__ ((noipa))
> +f (void)
> +{
> + volatile int x;
> + asm volatile ("" :::
> + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
> + "r8", "r9", "r10", "r11", "r12", "r14");
> +}
> +
> +/* The register clobbers above should not generate any single LDRs or STRs;
> + all registers should be pushed and popped using register lists. The only
> + STRs should therefore be those associated with the stack protector tests
> + themselves.
> +
> + Make sure the address of the canary is not spilled and reloaded,
> + since that would give the attacker an opportunity to change the
> + canary value. */
> +/* { dg-final { scan-assembler-times {\tstr\t} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/arm/stack-protector-6.c b/gcc/testsuite/gcc.target/arm/stack-protector-6.c
> new file mode 100644
> index 00000000000..f8eec878bd6
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/stack-protector-6.c
> @@ -0,0 +1,8 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target fpic } */
> +/* { dg-options "-fstack-protector-all -O2 -fpic" } */
> +
> +#include "stack-protector-5.c"
> +
> +/* See the comment in stack-protector-5.c. */
> +/* { dg-final { scan-assembler-times {\tstr\t} 1 } } */
next prev parent reply other threads:[~2020-09-28 19:57 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-23 18:33 Richard Sandiford
2020-09-24 8:29 ` Kyrylo Tkachov
2020-09-24 9:00 ` Richard Sandiford
2020-09-28 19:57 ` Christophe Lyon [this message]
2020-10-13 13:51 ` Richard Sandiford
2020-10-13 14:01 ` Christophe Lyon
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