From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 59094 invoked by alias); 8 Jun 2016 09:08:40 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 59074 invoked by uid 89); 8 Jun 2016 09:08:39 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=0.2 required=5.0 tests=AWL,BAYES_50,GAPPY_SUBJECT,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=no version=3.3.2 spammy=sk:advsimd, amnpx, WilcoDijkstraarmcom, nonARMv8 X-HELO: mail-qk0-f171.google.com Received: from mail-qk0-f171.google.com (HELO mail-qk0-f171.google.com) (209.85.220.171) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Wed, 08 Jun 2016 09:08:29 +0000 Received: by mail-qk0-f171.google.com with SMTP id p22so806565qka.2 for ; Wed, 08 Jun 2016 02:08:29 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=lg1DxLtnEg04Tl0lIWQFSaFmdpiXnFrwMFRgxRshwqg=; b=Ax0plGd8nZoW/PBdGr7v+QoU7Zg20cY9ebFrEvMKtFK+LDMQNsGWAOY5iBAzJOf/gX PoHbgDwhQaX443cPCB4SNorReUGP118H/2ms5u6BGZyAAz89KvzeEWKvHwpvIjZCOYrq CzwyNVeOG5/GIytrROfgssr8nfxr8UoVCx0emcE8EAvWk8az3pJuWXQrYzWabtDOoJYB mBxKu3b0dKY1RRPRJpxXLXRUBuW0LVMM2svoOjY0c7RKkfcHBO6QOZAvNzKciZk8ASCc l2s86lZ0q1DxGbSm+Te/6UAjaBP9by/AFqB9fHs+OdjrkXwG+InNCeXY29MQ/gfrT9+/ mnYQ== X-Gm-Message-State: ALyK8tJaRzVucg48op1FMsiMOAL8vw1KOVLUqyM63Ydi9rG6N/vQXSfEandxSQu0mzQx47V83thxFlZRGdByLuRM X-Received: by 10.55.126.7 with SMTP id z7mr3438043qkc.137.1465376907310; Wed, 08 Jun 2016 02:08:27 -0700 (PDT) MIME-Version: 1.0 Received: by 10.140.39.47 with HTTP; Wed, 8 Jun 2016 02:08:26 -0700 (PDT) In-Reply-To: References: <20160607154025.GC6963@e103625-lin.cambridge.arm.com> From: Christophe Lyon Date: Wed, 08 Jun 2016 09:08:00 -0000 Message-ID: Subject: Re: [Patch ARM/AArch64 09/11] Add missing vrnd{,a,m,n,p,x} tests. To: Wilco Dijkstra Cc: GCC Patches , nd Content-Type: text/plain; charset=UTF-8 X-IsSubscribed: yes X-SW-Source: 2016-06/txt/msg00551.txt.bz2 On 8 June 2016 at 10:47, Christophe Lyon wrote: > On 8 June 2016 at 09:37, Christophe Lyon wrote: >> On 7 June 2016 at 19:05, Wilco Dijkstra wrote: >>> Hi, >>> >>> >>> These new tests cause failures due to running on non-ARMv8 hardware - the >>> target check should be arm_v8_neon_hw. Also they don't run on AArch64 >>> hardware as arm_v8_neon_ok/arm_v8_neon_hw isn't true. >> >> This really makes sense. >> >> I use QEMU to run the tests, and according to my logs, the tests are compiled >> with -mfpu=neon-fp-armv8 -march=armv8-a >> and QEMU --cpu cortex-a9 (on the validation configurations intended to >> validate armv7-a). >> >> So... it looks like QEMU failed to reject the invalid instructions? >> I'm using QEMU-2.4.1. >> > Looking in more details, objdump says: > 1074c: f3fa05a0 vrintz.f32 d16, d16 > and qemu -d in_asm says: > 0x0001074c: f3fa05a0 vabal.u q8, d26, d16 > > and I've just had the same behaviour with QEMU-2.6.0 > > incorrect decoding probably means incorrect execution > (but how does the test manage to pass?). > After running QEMU in debug mode, it just seems that it fails to reject the instruction, and executes it correctly. I'm going to file a bug. Thanks for catching this. > Christophe > >>> check_effective_target_arm_v8_neon_hw in testsuite/lib/target-supports.exp >>> needs to be extended to allow running on AArch64 as well, as these tests >>> pass when I remove the dg-require-effective-target line. >> >> Probably, I didn't take AArch64 into account when added these. >> AArch64 intrinsics tests completion is still to be done. >> >> Christophe >> >>> >>> Wilco >>> >>> >>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c >>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c >>> new file mode 100644 >>> index 0000000..5f492d4 >>> --- /dev/null >>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c >>> @@ -0,0 +1,16 @@ >>> +/* { dg-require-effective-target arm_v8_neon_ok } */ >>> >>> This should be arm_v8_neon_hw (the arm_v8_neon_ok can only be used for >>> compilation). >>> >>> +/* { dg-add-options arm_v8_neon } */ >>> >>> ________________________________