From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 37276 invoked by alias); 8 Oct 2018 14:44:03 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 37260 invoked by uid 89); 8 Oct 2018 14:44:03 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-3.7 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-vk1-f178.google.com Received: from mail-vk1-f178.google.com (HELO mail-vk1-f178.google.com) (209.85.221.178) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 08 Oct 2018 14:44:01 +0000 Received: by mail-vk1-f178.google.com with SMTP id g80-v6so4560430vke.5 for ; Mon, 08 Oct 2018 07:44:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=f139d+TK8bRMRRVTO/MFbuoaojD0e0BqvizuTnR8BYs=; b=SIGfosFOrO/7hnUsuAa7n4kjtTV/IyYkCnSzi5HupI1dyVbdi1rR2dJEQyI88o1cUv 7i1MuU7R+TaTI9aiuH3ifCzkSLjRqs15Hl79mDBrllrZYSW/nrozIUnKld0Yi+KeZ3hy o45hOrggIxNjwoRt+AgKYJImR3cEEmodP3+HU= MIME-Version: 1.0 References: <616affd5-5140-8e15-9081-1635f7d4e700@redhat.com> <6ff45a7e-2415-2d18-1d53-5a50964a2174@linux.ibm.com> <14bf79ef-9db2-e76b-df10-fcb2574d5ccb@linux.ibm.com> <121ca751-fb38-d7e1-bffd-89df22a2fdd7@redhat.com> <05a29347-7a39-a1e6-42b8-16c779b97eb5@redhat.com> <703aaa46-eac5-63d1-22dc-0cd31a0e840f@redhat.com> <276824e1-6306-1ac6-b6ba-6b11eac615e7@linux.ibm.com> <191bf9ee-98c4-b87e-cc65-40e1fb5de0ea@linux.ibm.com> In-Reply-To: <191bf9ee-98c4-b87e-cc65-40e1fb5de0ea@linux.ibm.com> From: Christophe Lyon Date: Mon, 08 Oct 2018 14:46:00 -0000 Message-ID: Subject: Re: [PATCH 2/2 v3][IRA,LRA] Fix PR86939, IRA incorrectly creates an interference between a pseudo register and a hard register To: bergner@linux.ibm.com Cc: Vladimir Makarov , gcc Patches , "H.J. Lu" , Jeff Law Content-Type: text/plain; charset="UTF-8" X-IsSubscribed: yes X-SW-Source: 2018-10/txt/msg00444.txt.bz2 On Mon, 8 Oct 2018 at 16:13, Peter Bergner wrote: > > On 10/8/18 4:14 AM, Christophe Lyon wrote: > > Since r264897, we are seeing lots of regressions when bootstrapping on arm. > > There are execution errors as well as ICEs. > > A detailed list can be found at: > > https://ci.linaro.org/job/tcwg-compare-results/6498/artifact/artifacts/logs/1-diff-d05_32.tcwg-d05_32-build.txt > > > > You can also see the results posted on gcc-testresults. > > Sorry for the breakage. I'll try and build a cross compiler to fix the > ICEs. Hopefully all the other issues are related. > Note that I saw ICEs only when bootstrapping, not when testing a cross-compiler. > Peter > >