From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 12414 invoked by alias); 18 Nov 2014 10:16:15 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 12401 invoked by uid 89); 18 Nov 2014 10:16:14 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-qc0-f169.google.com Received: from mail-qc0-f169.google.com (HELO mail-qc0-f169.google.com) (209.85.216.169) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Tue, 18 Nov 2014 10:16:12 +0000 Received: by mail-qc0-f169.google.com with SMTP id w7so4165538qcr.28 for ; Tue, 18 Nov 2014 02:16:10 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type; bh=kosk4BzNVSyNHWfPutWc8PaGXe2EKo7HKmM/fpBVr5U=; b=RMR52qkLzo1cBNsz9fME32yilFcGqcO4GdvP/9L7Vb2hrim8vDuUF7/t9ANqQD4B7H 6RuKQiSVSLNzmg3TH2j6+aRvw/yBCVvxuPYqew0mWvK4tb5ufR3FjpOwPriwXyVq3Pwr 1QoH/2HSOqHgN8kidgIyzhAsEBqQ3deQQbNFhadd0shhJ1mivQ3yb7lHtgtJxEDj1cVr m1/qQN9ykdT1SHC5w/0Xk7pRYVhqnBvo4SNZLG9iNVN+SF34KnWIe62u2GkCa2Deb+5h SyS71hLQfbcc7JpXAqkLn3XekApcNMWli7L/AKh+1AnrTkipEH9wqSRmbxMjf1jRI50M /Bjw== X-Gm-Message-State: ALoCoQlrhMhpBs31NRAWIwIMjWUcyuwv74U5KchtpGeHCbSN6d55b/uBm8NXkoZy2FUtyvnbp02l MIME-Version: 1.0 X-Received: by 10.224.172.131 with SMTP id l3mr43045292qaz.32.1416305770787; Tue, 18 Nov 2014 02:16:10 -0800 (PST) Received: by 10.140.86.114 with HTTP; Tue, 18 Nov 2014 02:16:10 -0800 (PST) In-Reply-To: <000c01d00310$20bcab60$62360220$@arm.com> References: <000701cfff29$ea4fbcf0$beef36d0$@arm.com> <000b01cfff4e$aa668090$ff3381b0$@arm.com> <000c01d00310$20bcab60$62360220$@arm.com> Date: Tue, 18 Nov 2014 10:33:00 -0000 Message-ID: Subject: Re: New patch: [AArch64] [BE] [1/2] Make large opaque integer modes endianness-safe. From: Christophe Lyon To: David Sherwood Cc: "gcc-patches@gcc.gnu.org" , Alan Hayward Content-Type: text/plain; charset=UTF-8 X-IsSubscribed: yes X-SW-Source: 2014-11/txt/msg02241.txt.bz2 On 18 November 2014 10:14, David Sherwood wrote: > Hi Christophe, > > Ah sorry. My mistake - it fixes this in bugzilla: > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=59810 I did look at that PR, but since it has no testcase attached, I was unsure. And I am still not :-) PR 59810 is "[AArch64] LDn/STn implementations are not ABI-conformant for bigendian." but the advsimd-intrinsics/vldX.c and vldX_lane.c now PASS with Alan's patches on aarch64_be, so I thought Alan's patches solve PR59810. What am I missing? > > This change is needed in order to remove the CANNOT_CHANGE_MODE_CLASS > #define, which will be committed as a separate patch. > > Regards, > David Sherwood. > > -----Original Message----- > From: Christophe Lyon [mailto:christophe.lyon@linaro.org] > Sent: 17 November 2014 21:09 > To: David Sherwood > Cc: gcc-patches@gcc.gnu.org; Alan Hayward > Subject: Re: New patch: [AArch64] [BE] [1/2] Make large opaque integer modes endianness-safe. > > On 13 November 2014 15:32, David Sherwood wrote: >> Hi, >> >> I think that's because Alan Hayward's original patch had a bug in it, which he >> has fixed and should be submitting to gcc patches fairly soon. So it's probably >> best waiting until he gets a new patch up I think. >> > > I've applied both Alan's patches and the advsimd-intrinsics tests now > all pass on aarch64_be, but this doesn't need your patch. > > Which testcase does your patch actually fix? > > >> Regards, >> David. >> >> -----Original Message----- >> From: Christophe Lyon [mailto:christophe.lyon@linaro.org] >> Sent: 13 November 2014 14:22 >> To: David Sherwood >> Cc: gcc-patches@gcc.gnu.org >> Subject: Re: New patch: [AArch64] [BE] [1/2] Make large opaque integer modes endianness-safe. >> >> On 13 November 2014 11:09, David Sherwood wrote: >>> Hi All, >>> >>> I have successfully rebased this and tested in conjunction with a patch from >>> Alan Hayward ([AArch64] [BE] Fix vector load/stores to not use ld1/st1), who >>> should be submitting a new version shortly. Built and tested on: >>> >>> aarch64-none-elf >>> aarch64_be-none-elf >>> x86_64-linux-gnu >> >> I've applied both patches to recent trunk (r217483), and I still see >> ICEs on aarch64_be, when running the advsimd-intrinsics/vldX.c tests. >> >> I have them with Alan Hayward's patch alone, too. BTW, I thought that >> patch had been approved by Marcus, but it's not in trunk yet. Maybe I >> missed something. >> >> Christophe. >> >>> >>> Regards, >>> David Sherwood. >>> >>> -----Original Message----- >>> From: David Sherwood [mailto:david.sherwood@arm.com] >>> Sent: 28 October 2014 08:55 >>> To: 'gcc-patches@gcc.gnu.org' >>> Subject: RE: [AArch64] [BE] [1/2] Make large opaque integer modes endianness-safe. >>> >>> Hi, >>> >>> Sorry to bother you again. Could someone take a look at this change >>> please if they have time? >>> >>> Thanks! >>> David. >>> >>> -----Original Message----- >>> From: David Sherwood [mailto:david.sherwood@arm.com] >>> Sent: 10 October 2014 15:48 >>> To: gcc-patches@gcc.gnu.org >>> Subject: [AArch64] [BE] [1/2] Make large opaque integer modes endianness-safe. >>> >>> Hi, >>> >>> I have a fix (originally written by Tejas Belagod) for the following bug: >>> >>> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=59810 >>> >>> Could someone take a look please? >>> >>> Thanks! >>> David Sherwood. >>> >>> ChangeLog: >>> >>> gcc/: >>> 2014-11-13 David Sherwood >>> >>> * config/aarch64/aarch64-protos.h (aarch64_simd_attr_length_rglist, >>> aarch64_reverse_mask): New decls. >>> * config/aarch64/iterators.md (UNSPEC_REV_REGLIST): New enum. >>> * config/aarch64/iterators.md (insn_count): New mode_attr. >>> * config/aarch64/aarch64-simd.md (vec_store_lanes(o/c/x)i, >>> vec_load_lanes(o/c/x)i): Fixed to work for Big Endian. >>> * config/aarch64/aarch64-simd.md (aarch64_rev_reglist, >>> aarch64_simd_(ld/st)(2/3/4)): Added. >>> * config/aarch64/aarch64.c (aarch64_simd_attr_length_rglist, >>> aarch64_reverse_mask): Added. >> >> >> >> > > > >