From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 120121 invoked by alias); 19 May 2017 10:59:03 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 120101 invoked by uid 89); 19 May 2017 10:59:02 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.1 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_LOW,RCVD_IN_SORBS_SPAM,SPF_PASS autolearn=ham version=3.3.2 spammy=HX-Envelope-From:sk:christo X-HELO: mail-qt0-f179.google.com Received: from mail-qt0-f179.google.com (HELO mail-qt0-f179.google.com) (209.85.216.179) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 19 May 2017 10:59:00 +0000 Received: by mail-qt0-f179.google.com with SMTP id t26so55057230qtg.0 for ; Fri, 19 May 2017 03:59:04 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=ImSl56rNAgQCMYZQNMJXmpRLPCx3SoXluA6ooGldGIA=; b=o4+UPYu8dSMsDbfl1RReKCr/1IHdZreBsbACsbs9cXbvoEuR1BTENJPKZBZP9J8Qj9 zts6wl5lj0QPKzHuz6h67wR+hEFxrtMQRSsDBDzHgDdsMBc08Gp38DjxUioK1mdIFSJv /fb81BCfH8GSLsvm8kXfN2Rb12X37/t0r9zx21OjgHxJ85sOTktYk2D+AwSUnPuZiOSb 1YZbKayJBrMoZdWus4XV9U4+iRdW6RYOwnB0NZtyJQTGFXZc++RCTyUUqdReEe8R+8g0 sgXb5XbzbS5EKlO77r071NHhnEJN6wPVxcuZVIU6+IxFEku3YgPiY6VLEjw75RTsbs2L z/aA== X-Gm-Message-State: AODbwcBIGXuR2f1iutWjOIpL5mUXWitUmVHuhXNZ7Kzb4yqf/1IQW46f +LM/LHp3Hlm6xj/3/dQV9dB4XTCnu5GEL3FLFg== X-Received: by 10.237.60.74 with SMTP id u10mr7896092qte.205.1495191542297; Fri, 19 May 2017 03:59:02 -0700 (PDT) MIME-Version: 1.0 Received: by 10.140.104.85 with HTTP; Fri, 19 May 2017 03:59:01 -0700 (PDT) In-Reply-To: References: From: Christophe Lyon Date: Fri, 19 May 2017 11:00:00 -0000 Message-ID: Subject: Re: [PATCH][Aarch64] Add support for overflow add and sub operations To: Michael Collison Cc: "gcc-patches@gcc.gnu.org" , nd Content-Type: text/plain; charset="UTF-8" X-IsSubscribed: yes X-SW-Source: 2017-05/txt/msg01547.txt.bz2 Hi Michael, On 19 May 2017 at 07:12, Michael Collison wrote: > Hi, > > This patch improves code generations for builtin arithmetic overflow operations for the aarch64 backend. As an example for a simple test case such as: > > Sure for a simple test case such as: > > int > f (int x, int y, int *ovf) > { > int res; > *ovf = __builtin_sadd_overflow (x, y, &res); > return res; > } > > Current trunk at -O2 generates > > f: > mov w3, w0 > mov w4, 0 > add w0, w0, w1 > tbnz w1, #31, .L4 > cmp w0, w3 > blt .L3 > .L2: > str w4, [x2] > ret > .p2align 3 > .L4: > cmp w0, w3 > ble .L2 > .L3: > mov w4, 1 > b .L2 > > > With the patch this now generates: > > f: > adds w0, w0, w1 > cset w1, vs > str w1, [x2] > ret > > > Original patch from Richard Henderson: > > https://gcc.gnu.org/ml/gcc-patches/2016-01/msg01903.html > > > Okay for trunk? > > 2017-05-17 Michael Collison > Richard Henderson > > * config/aarch64/aarch64-modes.def (CC_V): New. > * config/aarch64/aarch64-protos.h > (aarch64_add_128bit_scratch_regs): Declare > (aarch64_add_128bit_scratch_regs): Declare. > (aarch64_expand_subvti): Declare. > (aarch64_gen_unlikely_cbranch): Declare > * config/aarch64/aarch64.c (aarch64_select_cc_mode): Test > for signed overflow using CC_Vmode. > (aarch64_get_condition_code_1): Handle CC_Vmode. > (aarch64_gen_unlikely_cbranch): New function. > (aarch64_add_128bit_scratch_regs): New function. > (aarch64_subv_128bit_scratch_regs): New function. > (aarch64_expand_subvti): New function. > * config/aarch64/aarch64.md (addv4, uaddv4): New. > (addti3): Create simpler code if low part is already known to be 0. > (addvti4, uaddvti4): New. > (*add3_compareC_cconly_imm): New. > (*add3_compareC_cconly): New. > (*add3_compareC_imm): New. > (*add3_compareC): Rename from add3_compare1; do not > handle constants within this pattern. > (*add3_compareV_cconly_imm): New. > (*add3_compareV_cconly): New. > (*add3_compareV_imm): New. > (add3_compareV): New. > (add3_carryinC, add3_carryinV): New. > (*add3_carryinC_zero, *add3_carryinV_zero): New. > (*add3_carryinC, *add3_carryinV): New. > (subv4, usubv4): New. > (subti): Handle op1 zero. > (subvti4, usub4ti4): New. > (*sub3_compare1_imm): New. > (sub3_carryinCV): New. > (*sub3_carryinCV_z1_z2, *sub3_carryinCV_z1): New. > (*sub3_carryinCV_z2, *sub3_carryinCV): New. > * testsuite/gcc.target/arm/builtin_sadd_128.c: New testcase. > * testsuite/gcc.target/arm/builtin_saddl.c: New testcase. > * testsuite/gcc.target/arm/builtin_saddll.c: New testcase. > * testsuite/gcc.target/arm/builtin_uadd_128.c: New testcase. > * testsuite/gcc.target/arm/builtin_uaddl.c: New testcase. > * testsuite/gcc.target/arm/builtin_uaddll.c: New testcase. > * testsuite/gcc.target/arm/builtin_ssub_128.c: New testcase. > * testsuite/gcc.target/arm/builtin_ssubl.c: New testcase. > * testsuite/gcc.target/arm/builtin_ssubll.c: New testcase. > * testsuite/gcc.target/arm/builtin_usub_128.c: New testcase. > * testsuite/gcc.target/arm/builtin_usubl.c: New testcase. > * testsuite/gcc.target/arm/builtin_usubll.c: New testcase. I've tried your patch, and 2 of the new tests FAIL: gcc.target/aarch64/builtin_sadd_128.c scan-assembler addcs gcc.target/aarch64/builtin_uadd_128.c scan-assembler addcs Am I missing something? Thanks, Christophe