From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-il1-x134.google.com (mail-il1-x134.google.com [IPv6:2607:f8b0:4864:20::134]) by sourceware.org (Postfix) with ESMTPS id E3067385782C for ; Thu, 16 Sep 2021 09:35:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E3067385782C Received: by mail-il1-x134.google.com with SMTP id m4so5956725ilj.9 for ; Thu, 16 Sep 2021 02:35:44 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=ncmFmKGBOawWytN+WVXZ4elTYHfBNwzpflgEbqJM9jY=; b=1IybAM9zZNbJJ3+82HFzfMEcEzRxCqpQAEXwr/kqvBWDlQYQNlXoAAKvmYKW7oUN/u 6+JfhKJBoivcQzC+3te4GdaGbScU+2ai+j63c2vnTBLKQL+GBIjkldhe+pgpw8iuA79E HACIDSyhPpJkB9U8Iwt+aL9I3+5fnQjTwQPxFEr/atWHTxr2JBCPXCdv537vaKcbZmja Jo0/lQ+32dRTK9qOIj8XfFeAAiCwUhCqCZ4WuiqqFEmAXe4cnbL9LmxMihGRQg8+HQj5 BlPGomi9msLn3KrkhqlTv5B7AlrIPgq8dkniYbV7c7rlZmuNrOrpZuJ8gQhYie/Gavzq 5YZQ== X-Gm-Message-State: AOAM53121I/+zHTFHRp2hQdl/VXSQTaOhRnPA8GFYtI1UjFI3VOk3dvI tudtEhJ03tmMcypkcfjZem6x5euT8DNBwvpSK8c= X-Google-Smtp-Source: ABdhPJySdEPs7L7nhePwF7mZmteSoaIH8WySjBd4S3B0Xk6mVbLNBPFhV+qRWYnYSchKXuAemVhoYoYnOSKOFyfr6CU= X-Received: by 2002:a92:6805:: with SMTP id d5mr3225482ilc.286.1631784944264; Thu, 16 Sep 2021 02:35:44 -0700 (PDT) MIME-Version: 1.0 References: <20210826155310.4039951-1-christophe.lyon@foss.st.com> <7788bf43-7afc-59d6-7995-c6fb4ad6eefb@foss.arm.com> <9f36198e-e341-dc91-55a1-47cdfcef9a45@foss.st.com> <6652c071-d59d-cd94-4bf7-d3b5b885b85a@foss.arm.com> <691dfbcd-d7ab-05ce-d9cc-2728bca544cb@foss.arm.com> <0d56e21c-7907-a515-4c36-0b908d75287c@foss.st.com> In-Reply-To: From: Christophe Lyon Date: Thu, 16 Sep 2021 11:35:33 +0200 Message-ID: Subject: Re: [PATCH] testsuite: Make sure double-precision is supported in g++.dg/eh/arm-vfp-unwind.C To: Richard Earnshaw Cc: Christophe LYON , GCC Patches X-Spam-Status: No, score=-8.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, HTML_MESSAGE, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org Content-Type: text/plain; charset="UTF-8" X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 16 Sep 2021 09:35:46 -0000 On Thu, Sep 16, 2021 at 11:21 AM Richard Earnshaw via Gcc-patches < gcc-patches@gcc.gnu.org> wrote: > > > On 16/09/2021 10:12, Christophe LYON via Gcc-patches wrote: > > > > On 15/09/2021 18:43, Richard Earnshaw via Gcc-patches wrote: > >> > >> > >> On 15/09/2021 17:13, Christophe Lyon via Gcc-patches wrote: > >>> On Wed, Sep 15, 2021 at 2:49 PM Richard Earnshaw via Gcc-patches < > >>> gcc-patches@gcc.gnu.org> wrote: > >>> > >>>> > >>>> > >>>> On 15/09/2021 13:26, Christophe LYON via Gcc-patches wrote: > >>>>> > >>>>> On 15/09/2021 13:02, Richard Earnshaw wrote: > >>>>>> > >>>>>> > >>>>>> On 26/08/2021 16:53, Christophe Lyon via Gcc-patches wrote: > >>>>>>> g++.dg/eh/arm-vfp-unwind.C uses an asm statement relying on > >>>>>>> double-precision FPU support, but does not make sure it is actually > >>>>>>> supported by the target. > >>>>>>> Check (__ARM_FP & 8) to ensure this. > >>>>>>> > >>>>>>> 2021-08-26 Christophe Lyon > >>>>>>> > >>>>>>> gcc/testsuite/ > >>>>>>> * g++.dg/eh/arm-vfp-unwind.C: Check __ARM_FP. > >>>>>>> --- > >>>>>>> gcc/testsuite/g++.dg/eh/arm-vfp-unwind.C | 2 +- > >>>>>>> 1 file changed, 1 insertion(+), 1 deletion(-) > >>>>>>> > >>>>>>> diff --git a/gcc/testsuite/g++.dg/eh/arm-vfp-unwind.C > >>>>>>> b/gcc/testsuite/g++.dg/eh/arm-vfp-unwind.C > >>>>>>> index 62263c0c3b0..90d20081d78 100644 > >>>>>>> --- a/gcc/testsuite/g++.dg/eh/arm-vfp-unwind.C > >>>>>>> +++ b/gcc/testsuite/g++.dg/eh/arm-vfp-unwind.C > >>>>>>> @@ -3,7 +3,7 @@ > >>>>>>> /* Test to catch off-by-one errors in arm/pr-support.c. */ > >>>>>>> -#if defined (__VFP_FP__) && !defined (__SOFTFP__) > >>>>>>> +#if defined (__VFP_FP__) && !defined (__SOFTFP__) && (__ARM_FP & > 8) > >>>>>>> #include > >>>>>>> #include > >>>>>>> > >>>>>> > >>>>>> Wouldn't it be better to have an alternate to the asm for the case > >>>>>> where we only have single-precision float? Something like > >>>>>> (untested): > >>>>>> > >>>>>> static void donkey () > >>>>>> { > >>>>>> #if __ARM_FP & 8 > >>>>>> asm volatile ("fcpyd d9, %P0" : : "w" (1.2345) : "d9"); > >>>>>> #else > >>>>>> asm volatile ("fcpys s18, %P0" : : "w" (1.2345f) : "s18"); > >>>>>> #endif > >>>>>> throw 1; > >>>>>> } > >>>>> > >>>>> > >>>>> I tried similar things but they failed on some testing > configurations. > >>>>> > >>>>> Let me try your version, I'll let you know if there is any fallout. > >>>> > >>>> Of course, the asm syntax should be converted to the new 'unified > >>>> syntax' form ie vmov.f{32,64}. > >>>> > >>>> > >>> The problem is that %P expects a double-precision register. > >>> It seems there's nothing to print a single-precision register, or > >>> rather %p > >>> (small p) > >>> rejects s18 too. > >>> > >>> > >> I said it was untested :) > > > > In fact, I now remember I tried similar things and everything failed, > > hence my proposal at the start of this thread :-) > > > > > >> > >> You want something like > >> > >> #if __ARM_FP & 8 > >> asm volatile ("vmov.f64 d9, %P0" : : "w" (1.2345) : "d9"); > >> #else > >> asm volatile ("vmov.f32 s18, %0" : : "t" (1.2345f) : "s18"); > >> #endif > >> > >> (there's no need for a modifier on the single-precision register name). > > > > Ha! I missed the magic "t". > > > > I confirm this fixes the issues that motivated my original patch. > > > > Do you want me to commit it? > > Yes, please. > > Ack, done as r12-3571-g8e2c293f02745d47948fff19615064e4b34c1776 R. > > > > > > > Thanks > > > > Christophe > > > > > >> > >>> > >>>> R. > >>>> > >>>>> > >>>>> Christophe > >>>>> > >>>>> > >>>>>> > >>>>>> R. > >>>> >