From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-io1-xd33.google.com (mail-io1-xd33.google.com [IPv6:2607:f8b0:4864:20::d33]) by sourceware.org (Postfix) with ESMTPS id 93F063858403 for ; Wed, 15 Sep 2021 16:13:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 93F063858403 Received: by mail-io1-xd33.google.com with SMTP id b200so4100082iof.13 for ; Wed, 15 Sep 2021 09:13:15 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=LPci50D0CeuC3wIwVjGof4uJva/8KlUgksQ0asaDQpY=; b=XqLAXRU2Ycf+cSEg5Ra+PKziMnYoPpCEKig71Ju/+5Oxfieljif6zP/Ftt25DjbtEE lpOyfdc2LtmdG9RdURZoWdVonhsUuVL1KxCO3SI5lDe+QzVFqr5M+iNyIDbuN4u4K1zG UJm/k61xFL/ZGFjnUNHGTzlDi7k3Qrpep4SWpjb0TwQLEPRpBew/v90v0QOKAIHtCUz+ g0qpzqPYH0g3LyeNE8a4Chxx3ter/Gsvtp+VAJrsHg9vHgFEX6MWk55IamrkKrU0n1Vk fPMRQjHDb5Rr4Y+uBOGA8gQ6XY/5BICiiYplfmWzmkEM57xNAAzwE9qWE6lyMYNyuAW5 xEbA== X-Gm-Message-State: AOAM530SY6OzZUTI14pgAPB3HO2HMGvM1w5pkYdjBDRGNBUgTYAp3vgF fswVowbHT5Y+q09LEsWpY9Dv/2yKIB9f79w1L6c= X-Google-Smtp-Source: ABdhPJwfCgquI5J2vsdCdOiyvILimbgjS5CgEfIEv2lxoP/ELDd8SQvSfislNFr8Kxf+eqKM4frQzxlaC6y7p6bIirg= X-Received: by 2002:a6b:dc1a:: with SMTP id s26mr649880ioc.191.1631722394960; Wed, 15 Sep 2021 09:13:14 -0700 (PDT) MIME-Version: 1.0 References: <20210826155310.4039951-1-christophe.lyon@foss.st.com> <7788bf43-7afc-59d6-7995-c6fb4ad6eefb@foss.arm.com> <9f36198e-e341-dc91-55a1-47cdfcef9a45@foss.st.com> <6652c071-d59d-cd94-4bf7-d3b5b885b85a@foss.arm.com> In-Reply-To: <6652c071-d59d-cd94-4bf7-d3b5b885b85a@foss.arm.com> From: Christophe Lyon Date: Wed, 15 Sep 2021 18:13:04 +0200 Message-ID: Subject: Re: [PATCH] testsuite: Make sure double-precision is supported in g++.dg/eh/arm-vfp-unwind.C To: Richard Earnshaw Cc: Christophe LYON , GCC Patches X-Spam-Status: No, score=-8.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, HTML_MESSAGE, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org Content-Type: text/plain; charset="UTF-8" X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 15 Sep 2021 16:13:17 -0000 On Wed, Sep 15, 2021 at 2:49 PM Richard Earnshaw via Gcc-patches < gcc-patches@gcc.gnu.org> wrote: > > > On 15/09/2021 13:26, Christophe LYON via Gcc-patches wrote: > > > > On 15/09/2021 13:02, Richard Earnshaw wrote: > >> > >> > >> On 26/08/2021 16:53, Christophe Lyon via Gcc-patches wrote: > >>> g++.dg/eh/arm-vfp-unwind.C uses an asm statement relying on > >>> double-precision FPU support, but does not make sure it is actually > >>> supported by the target. > >>> Check (__ARM_FP & 8) to ensure this. > >>> > >>> 2021-08-26 Christophe Lyon > >>> > >>> gcc/testsuite/ > >>> * g++.dg/eh/arm-vfp-unwind.C: Check __ARM_FP. > >>> --- > >>> gcc/testsuite/g++.dg/eh/arm-vfp-unwind.C | 2 +- > >>> 1 file changed, 1 insertion(+), 1 deletion(-) > >>> > >>> diff --git a/gcc/testsuite/g++.dg/eh/arm-vfp-unwind.C > >>> b/gcc/testsuite/g++.dg/eh/arm-vfp-unwind.C > >>> index 62263c0c3b0..90d20081d78 100644 > >>> --- a/gcc/testsuite/g++.dg/eh/arm-vfp-unwind.C > >>> +++ b/gcc/testsuite/g++.dg/eh/arm-vfp-unwind.C > >>> @@ -3,7 +3,7 @@ > >>> /* Test to catch off-by-one errors in arm/pr-support.c. */ > >>> -#if defined (__VFP_FP__) && !defined (__SOFTFP__) > >>> +#if defined (__VFP_FP__) && !defined (__SOFTFP__) && (__ARM_FP & 8) > >>> #include > >>> #include > >>> > >> > >> Wouldn't it be better to have an alternate to the asm for the case > >> where we only have single-precision float? Something like (untested): > >> > >> static void donkey () > >> { > >> #if __ARM_FP & 8 > >> asm volatile ("fcpyd d9, %P0" : : "w" (1.2345) : "d9"); > >> #else > >> asm volatile ("fcpys s18, %P0" : : "w" (1.2345f) : "s18"); > >> #endif > >> throw 1; > >> } > > > > > > I tried similar things but they failed on some testing configurations. > > > > Let me try your version, I'll let you know if there is any fallout. > > Of course, the asm syntax should be converted to the new 'unified > syntax' form ie vmov.f{32,64}. > > The problem is that %P expects a double-precision register. It seems there's nothing to print a single-precision register, or rather %p (small p) rejects s18 too. > R. > > > > > Christophe > > > > > >> > >> R. >