From 912581f71ad37b415aec06d23210109e1c778296 Mon Sep 17 00:00:00 2001 From: Chenghua Xu Date: Mon, 17 Jun 2019 14:36:37 +0800 Subject: [PATCH] [MIPS][Testsuite] specify msa-fmadd.c abis. gcc/testsuite/ * gcc.target/mips/mips-fmadd.c: Rename to ... * gcc.target/mips/mips-fmadd-o32.c: ... Here; add abi=32. * gcc.target/mips/mips-fmadd-n64.c: New. --- gcc/testsuite/gcc.target/mips/msa-fmadd-n64.c | 101 +++++++++++++++++++++ .../mips/{msa-fmadd.c => msa-fmadd-o32.c} | 2 +- 2 files changed, 102 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/mips/msa-fmadd-n64.c rename gcc/testsuite/gcc.target/mips/{msa-fmadd.c => msa-fmadd-o32.c} (96%) diff --git a/gcc/testsuite/gcc.target/mips/msa-fmadd-n64.c b/gcc/testsuite/gcc.target/mips/msa-fmadd-n64.c new file mode 100644 index 00000000000..199b366512c --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/msa-fmadd-n64.c @@ -0,0 +1,101 @@ +/* { dg-do compile } */ +/* { dg-options "-mabi=64 -mfp64 -mhard-float -mmsa -EL -flax-vector-conversions" } */ +/* { dg-skip-if "uses global registers" { *-*-* } { "-O0" } { "" } } */ + +typedef int v4i32 __attribute__ ((vector_size(16))); +typedef float v4f32 __attribute__ ((vector_size(16))); +typedef double v2f64 __attribute__ ((vector_size(16))); + +/* Test that MSA FMADD-like intrinsics do not use first operand for multiplication. */ + +register v4i32 a __asm__("$f24"); +register v4i32 b __asm__("$f25"); +register v4f32 c __asm__("$f26"); +register v4f32 d __asm__("$f27"); +register v2f64 e __asm__("$f28"); +register v2f64 f __asm__("$f29"); + +void +maddv_b_msa (void) +{ + a = __builtin_msa_maddv_b (a, b, b); +} +/* { dg-final { scan-assembler "maddv\\\.b\t\\\$w24,\\\$w25,\\\$w25" } } */ + +void +maddv_h_msa (void) +{ + a = __builtin_msa_maddv_h (a, b, b); +} +/* { dg-final { scan-assembler "maddv\\\.h\t\\\$w24,\\\$w25,\\\$w25" } } */ + +void +maddv_w_msa (void) +{ + a = __builtin_msa_maddv_w (a, b, b); +} +/* { dg-final { scan-assembler "maddv\\\.w\t\\\$w24,\\\$w25,\\\$w25" } } */ + +void +maddv_d_msa (void) +{ + a = __builtin_msa_maddv_d (a, b, b); +} +/* { dg-final { scan-assembler "maddv\\\.d\t\\\$w24,\\\$w25,\\\$w25" } } */ + +void +msubv_b_msa (void) +{ + a = __builtin_msa_msubv_b (a, b, b); +} +/* { dg-final { scan-assembler "msubv\\\.b\t\\\$w24,\\\$w25,\\\$w25" } } */ + +void +msubv_h_msa (void) +{ + a = __builtin_msa_msubv_h (a, b, b); +} +/* { dg-final { scan-assembler "msubv\\\.h\t\\\$w24,\\\$w25,\\\$w25" } } */ + +void +msubv_w_msa (void) +{ + a = __builtin_msa_msubv_w (a, b, b); +} +/* { dg-final { scan-assembler "msubv\\\.w\t\\\$w24,\\\$w25,\\\$w25" } } */ + +void +msubv_d_msa (void) +{ + a = __builtin_msa_msubv_d (a, b, b); +} +/* { dg-final { scan-assembler "msubv\\\.d\t\\\$w24,\\\$w25,\\\$w25" } } */ + +void +fmadd_w_msa (void) +{ + c = __builtin_msa_fmadd_w (c, d, d); +} +/* { dg-final { scan-assembler "fmadd\\\.w\t\\\$w26,\\\$w27,\\\$w27" } } */ + +void +fmadd_d_msa (void) +{ + e = __builtin_msa_fmadd_d (e, f, f); +} +/* { dg-final { scan-assembler "fmadd\\\.d\t\\\$w28,\\\$w29,\\\$w29" } } */ + +void +fmsub_w_msa (void) +{ + c = __builtin_msa_fmsub_w (c, d, d); +} +/* { dg-final { scan-assembler "fmsub\\\.w\t\\\$w26,\\\$w27,\\\$w27" } } */ + +void +fmsub_d_msa (void) +{ + e = __builtin_msa_fmsub_d (e, f, f); +} +/* { dg-final { scan-assembler "fmsub\\\.d\t\\\$w28,\\\$w29,\\\$w29" } } */ + diff --git a/gcc/testsuite/gcc.target/mips/msa-fmadd.c b/gcc/testsuite/gcc.target/mips/msa-fmadd-o32.c similarity index 96% rename from gcc/testsuite/gcc.target/mips/msa-fmadd.c rename to gcc/testsuite/gcc.target/mips/msa-fmadd-o32.c index 9265c04ff9c..843336990e4 100644 --- a/gcc/testsuite/gcc.target/mips/msa-fmadd.c +++ b/gcc/testsuite/gcc.target/mips/msa-fmadd-o32.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mfp64 -mhard-float -mmsa -EL -flax-vector-conversions" } */ +/* { dg-options "-mabi=32 -mfp64 -mhard-float -mmsa -EL -flax-vector-conversions" } */ /* { dg-skip-if "uses global registers" { *-*-* } { "-O0" } { "" } } */ typedef int v4i32 __attribute__ ((vector_size(16))); -- 2.11.0