From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 91125 invoked by alias); 14 Dec 2018 21:16:03 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 90964 invoked by uid 89); 14 Dec 2018 21:16:02 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.4 required=5.0 tests=BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,KAM_NUMSUBJECT,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy=2018-11-28, 20181128, Force X-HELO: mail-it1-f194.google.com Received: from mail-it1-f194.google.com (HELO mail-it1-f194.google.com) (209.85.166.194) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 14 Dec 2018 21:15:57 +0000 Received: by mail-it1-f194.google.com with SMTP id h193so11570809ita.5 for ; Fri, 14 Dec 2018 13:15:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=cKkZL3ItLKoylMbya0OfU/LCJYwdmaBofQ4eybfzc04=; b=O79rqPSa033oaQMYioKQYmu9xt6NF5LTnKSi79nlZ0QNcvJncUbF0mlLGIvJHScYIq 43Qdw+V45oDkU2MzP81fXdTwBhB3zGYN7vhQxsD1tdB7Q70URUlE4Rl5V6wyPp8Qj6nr dEVERTFIkEn7nq8l00wYc53Fa0bLf5SxbIT0E= MIME-Version: 1.0 References: <0be4bbb0-3c3e-3919-64f8-646c3f9611ff@arm.com> In-Reply-To: <0be4bbb0-3c3e-3919-64f8-646c3f9611ff@arm.com> From: Thomas Preudhomme Date: Fri, 14 Dec 2018 21:16:00 -0000 Message-ID: Subject: Re: [PATCH, ARM] Do softfloat when -mfpu set, -mfloat-abi=softfp and targeting Thumb-1 To: Richard Earnshaw Cc: kyrylo.tkachov@foss.arm.com, Ramana Radhakrishnan , gcc-patches@gcc.gnu.org Content-Type: multipart/mixed; boundary="000000000000d9f22f057d01efd6" X-IsSubscribed: yes X-SW-Source: 2018-12/txt/msg01102.txt.bz2 --000000000000d9f22f057d01efd6 Content-Type: text/plain; charset="UTF-8" Content-length: 6978 Hi Richard, Thanks for catching the problem with this approach. Hopefully this version should solve the real problem: FP instructions are only enabled for TARGET_32BIT and TARGET_HARD_FLOAT but GCC only gives an error when TARGET_HARD_FLOAT is true and -mfpu is not set. Among other things, it makes some of the cmse tests (eg. gcc.target/arm/cmse/baseline/softfp.c) fail when targeting -march=armv8-m.base -mcmse -mfpu= -mfloat-abi=softfp. This patch adds an extra check for TARGET_32BIT to TARGET_HARD_FLOAT such that it is false on TARGET_THUMB1 targets even when a FPU is specified. ChangeLog entries are as follows: *** gcc/ChangeLog *** 2018-12-14 thomas Preud'homme * config/arm/arm.h (TARGET_HARD_FLOAT): Restrict to TARGET_32BIT targets. *** gcc/testsuite/ChangeLog *** 2018-12-14 thomas Preud'homme * gcc.target/arm/cmse/baseline/softfp.c: Force an FPU. Testing: No testsuite regression when targeting arm-none-eabi Armv6S-M with -mfloat-abi=softfp Is this ok for stage3? Best regards, Thomas On Thu, 29 Nov 2018 at 14:52, Richard Earnshaw (lists) wrote: > > On 29/11/2018 10:51, Thomas Preudhomme wrote: > > Hi, > > > > FP instructions are only enabled for TARGET_32BIT and TARGET_HARD_FLOAT > > but GCC only gives an error when TARGET_HARD_FLOAT is true and -mfpu is > > not set. Among other things, it makes some of the cmse tests (eg. > > gcc.target/arm/cmse/baseline/softfp.c) fail when targeting > > -march=armv8-m.base -mfpu= -mfloat-abi=softfp. This patch > > errors out when a Thumb-1 -like target is selected and a FPU is > > specified, thus making such tests being skipped. > > > > ChangeLog entries are as follows: > > > > *** gcc/ChangeLog *** > > > > 2018-11-28 thomas Preud'homme > > > > * config/arm/arm.c (arm_options_perform_arch_sanity_checks): Error out > > if targeting Thumb-1 with an FPU specified. > > > > *** gcc/testsuite/ChangeLog *** > > > > 2018-11-28 thomas Preud'homme > > > > * gcc.target/arm/thumb1_mfpu-1.c: New testcase. > > * gcc.target/arm/thumb1_mfpu-2.c: Likewise. > > > > Testing: No testsuite regression when targeting arm-none-eabi Armv6S-M. > > Fails as expected when targeting Armv6-M with an -mfpu or a default FPU. > > Succeeds without. > > > > Is this ok for stage3? > > > > This doesn't sound right. Specifically this bit... > > + else if (TARGET_THUMB1 > + && bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv2)) > + error ("Thumb-1 does not allow FP instructions"); > > If I use > > -mcpu=arm1176jzf-s -mfpu=auto -mfloat-abi=softfp -mthumb > > then that shouldn't error, since softfp and thumb is, in reality, just > float-abi=soft (as there are no fp instructions in thumb). We also want > it to work this way so that I can add the thumb/arm attribute to > specific functions and have the compiler use HW float instructions when > they are suitable. > > > R. > > > Best regards, > > > > Thomas > > > > > > thumb1_mfpu_error.patch > > > > From 051e38552d7c596873e0303f6ec4272b26d50900 Mon Sep 17 00:00:00 2001 > > From: Thomas Preud'homme > > Date: Tue, 27 Nov 2018 15:52:38 +0000 > > Subject: [PATCH] [PATCH, ARM] Error out when -mfpu set and targeting Thumb-1 > > > > Hi, > > > > FP instructions are only enabled for TARGET_32BIT and TARGET_HARD_FLOAT > > but GCC only gives an error when TARGET_HARD_FLOAT is true and -mfpu is > > not set. Among other things, it makes some of the cmse tests (eg. > > gcc.target/arm/cmse/baseline/softfp.c) fail when targeting > > -march=armv8-m.base -mfpu= -mfloat-abi=softfp. This patch > > errors out when a Thumb-1 -like target is selected and a FPU is > > specified, thus making such tests being skipped. > > > > ChangeLog entries are as follows: > > > > *** gcc/ChangeLog *** > > > > 2018-11-28 thomas Preud'homme > > > > * config/arm/arm.c (arm_options_perform_arch_sanity_checks): Error out > > if targeting Thumb-1 with an FPU specified. > > > > *** gcc/testsuite/ChangeLog *** > > > > 2018-11-28 thomas Preud'homme > > > > * gcc.target/arm/thumb1_mfpu-1.c: New testcase. > > * gcc.target/arm/thumb1_mfpu-2.c: Likewise. > > > > Testing: No testsuite regression when targeting arm-none-eabi Armv6S-M. > > Fails as expected when targeting Armv6-M with an -mfpu or a default FPU. > > Succeeds without. > > > > Is this ok for stage3? > > > > Best regards, > > > > Thomas > > --- > > gcc/config/arm/arm.c | 3 +++ > > gcc/testsuite/gcc.target/arm/thumb1_mfpu-1.c | 7 +++++++ > > gcc/testsuite/gcc.target/arm/thumb1_mfpu-2.c | 8 ++++++++ > > 3 files changed, 18 insertions(+) > > create mode 100644 gcc/testsuite/gcc.target/arm/thumb1_mfpu-1.c > > create mode 100644 gcc/testsuite/gcc.target/arm/thumb1_mfpu-2.c > > > > diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c > > index 40f0574e32e..1a205123cf5 100644 > > --- a/gcc/config/arm/arm.c > > +++ b/gcc/config/arm/arm.c > > @@ -3747,6 +3747,9 @@ arm_options_perform_arch_sanity_checks (void) > > { > > if (arm_abi == ARM_ABI_IWMMXT) > > arm_pcs_default = ARM_PCS_AAPCS_IWMMXT; > > + else if (TARGET_THUMB1 > > + && bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv2)) > > + error ("Thumb-1 does not allow FP instructions"); > > else if (TARGET_HARD_FLOAT_ABI) > > { > > arm_pcs_default = ARM_PCS_AAPCS_VFP; > > diff --git a/gcc/testsuite/gcc.target/arm/thumb1_mfpu-1.c b/gcc/testsuite/gcc.target/arm/thumb1_mfpu-1.c > > new file mode 100644 > > index 00000000000..5347e63f9b6 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/arm/thumb1_mfpu-1.c > > @@ -0,0 +1,7 @@ > > +/* { dg-do compile } */ > > +/* { dg-require-effective-target arm_thumb1_ok } */ > > +/* { dg-skip-if "incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=softfp" } } */ > > +/* { dg-options "-mthumb -mfpu=vfp -mfloat-abi=softfp" } */ > > +/* { dg-error "Thumb-1 does not allow FP instructions" "" { target *-*-* } 0 } */ > > + > > +int foo; > > diff --git a/gcc/testsuite/gcc.target/arm/thumb1_mfpu-2.c b/gcc/testsuite/gcc.target/arm/thumb1_mfpu-2.c > > new file mode 100644 > > index 00000000000..941ed26ed01 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/arm/thumb1_mfpu-2.c > > @@ -0,0 +1,8 @@ > > +/* { dg-do compile } */ > > +/* { dg-require-effective-target arm_thumb1_ok } */ > > +/* { dg-skip-if "incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=softfp" } } */ > > +/* No need to skip in presence of -mfpu since arm_thumb1_ok will already fail > > + due to Thumb-1 with -mfpu which is tested by thumb1_mfpu-1 testcase. */ > > +/* { dg-options "-mthumb -mfloat-abi=softfp" } */ > > + > > +int foo; > > > --000000000000d9f22f057d01efd6 Content-Type: text/x-patch; charset="US-ASCII"; name="softfloat_mfpu_set_softfp_thumb1.patch" Content-Disposition: attachment; filename="softfloat_mfpu_set_softfp_thumb1.patch" Content-Transfer-Encoding: base64 Content-ID: X-Attachment-Id: f_jpoj7snu0 Content-length: 3543 RnJvbSA3YzA1NmYzODZkZjQ1OGYwOGMwYWUzNjdlZGM3MDUwZDUzY2Q2NjAy IE1vbiBTZXAgMTcgMDA6MDA6MDAgMjAwMQpGcm9tOiBUaG9tYXMgUHJldWQn aG9tbWUgPHRob21hcy5wcmV1ZGhvbW1lQGxpbmFyby5vcmc+CkRhdGU6IFR1 ZSwgMjcgTm92IDIwMTggMTU6NTI6MzggKzAwMDAKU3ViamVjdDogW1BBVENI XSBbUEFUQ0gsIEFSTV0gRG8gc29mdGZsb2F0IHdoZW4gLW1mcHUgc2V0LCAt bWZsb2F0LWFiaT1zb2Z0ZnAKIGFuZCB0YXJnZXRpbmcgVGh1bWItMQoKSGks CgpGUCBpbnN0cnVjdGlvbnMgYXJlIG9ubHkgZW5hYmxlZCBmb3IgVEFSR0VU XzMyQklUIGFuZCBUQVJHRVRfSEFSRF9GTE9BVApidXQgR0NDIG9ubHkgZ2l2 ZXMgYW4gZXJyb3Igd2hlbiBUQVJHRVRfSEFSRF9GTE9BVCBpcyB0cnVlIGFu ZCAtbWZwdSBpcwpub3Qgc2V0LiBBbW9uZyBvdGhlciB0aGluZ3MsIGl0IG1h a2VzIHNvbWUgb2YgdGhlIGNtc2UgdGVzdHMgKGVnLgpnY2MudGFyZ2V0L2Fy bS9jbXNlL2Jhc2VsaW5lL3NvZnRmcC5jKSBmYWlsIHdoZW4gdGFyZ2V0aW5n Ci1tYXJjaD1hcm12OC1tLmJhc2UgLW1jbXNlIC1tZnB1PTxzb21ldGhpbmc+ IC1tZmxvYXQtYWJpPXNvZnRmcC4gVGhpcwpwYXRjaCBhZGRzIGFuIGV4dHJh IGNoZWNrIGZvciBUQVJHRVRfMzJCSVQgdG8gVEFSR0VUX0hBUkRfRkxPQVQg c3VjaAp0aGF0IGl0IGlzIGZhbHNlIG9uIFRBUkdFVF9USFVNQjEgdGFyZ2V0 cyBldmVuIHdoZW4gYSBGUFUgaXMgc3BlY2lmaWVkLgoKQ2hhbmdlTG9nIGVu dHJpZXMgYXJlIGFzIGZvbGxvd3M6CgoqKiogZ2NjL0NoYW5nZUxvZyAqKioK CjIwMTgtMTItMTQgIHRob21hcyBQcmV1ZCdob21tZSAgPHRob21hcy5wcmV1 ZGhvbW1lQGxpbmFyby5vcmc+CgoJKiBjb25maWcvYXJtL2FybS5oIChUQVJH RVRfSEFSRF9GTE9BVCk6IFJlc3RyaWN0IHRvIFRBUkdFVF8zMkJJVAoJdGFy Z2V0cy4KCioqKiBnY2MvdGVzdHN1aXRlL0NoYW5nZUxvZyAqKioKCjIwMTgt MTItMTQgIHRob21hcyBQcmV1ZCdob21tZSAgPHRob21hcy5wcmV1ZGhvbW1l QGxpbmFyby5vcmc+CgoJKiBnY2MudGFyZ2V0L2FybS9jbXNlL2Jhc2VsaW5l L3NvZnRmcC5jOiBGb3JjZSBhbiBGUFUuCgpUZXN0aW5nOiBObyB0ZXN0c3Vp dGUgcmVncmVzc2lvbiB3aGVuIHRhcmdldGluZyBhcm0tbm9uZS1lYWJpIEFy bXY2Uy1NLgoKSXMgdGhpcyBvayBmb3Igc3RhZ2UzPwoKQmVzdCByZWdhcmRz LAoKVGhvbWFzCi0tLQogZ2NjL2NvbmZpZy9hcm0vYXJtLmggICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgIHwgMyArKy0KIGdjYy90ZXN0c3VpdGUv Z2NjLnRhcmdldC9hcm0vY21zZS9iYXNlbGluZS9zb2Z0ZnAuYyB8IDQgKysr LQogMiBmaWxlcyBjaGFuZ2VkLCA1IGluc2VydGlvbnMoKyksIDIgZGVsZXRp b25zKC0pCgpkaWZmIC0tZ2l0IGEvZ2NjL2NvbmZpZy9hcm0vYXJtLmggYi9n Y2MvY29uZmlnL2FybS9hcm0uaAppbmRleCA4NDcyMzEyNDg3Yi4uMTQ5MjQz ZDA5NzggMTAwNjQ0Ci0tLSBhL2djYy9jb25maWcvYXJtL2FybS5oCisrKyBi L2djYy9jb25maWcvYXJtL2FybS5oCkBAIC0xMjUsNyArMTI1LDggQEAgZXh0 ZXJuIHRyZWUgYXJtX2ZwMTZfdHlwZV9ub2RlOwogLyogVXNlIGhhcmR3YXJl IGZsb2F0aW5nIHBvaW50IGluc3RydWN0aW9ucy4gKi8KICNkZWZpbmUgVEFS R0VUX0hBUkRfRkxPQVQJKGFybV9mbG9hdF9hYmkgIT0gQVJNX0ZMT0FUX0FC SV9TT0ZUCVwKIAkJCQkgJiYgYml0bWFwX2JpdF9wIChhcm1fYWN0aXZlX3Rh cmdldC5pc2EsIFwKLQkJCQkJCSAgaXNhX2JpdF92ZnB2MikpCisJCQkJCQkg IGlzYV9iaXRfdmZwdjIpIFwKKwkJCQkgJiYgVEFSR0VUXzMyQklUKQogI2Rl ZmluZSBUQVJHRVRfU09GVF9GTE9BVAkoIVRBUkdFVF9IQVJEX0ZMT0FUKQog LyogVXNlciBoYXMgcGVybWl0dGVkIHVzZSBvZiBGUCBpbnN0cnVjdGlvbnMs IGlmIHRoZXkgZXhpc3QgZm9yIHRoaXMKICAgIHRhcmdldC4gICovCmRpZmYg LS1naXQgYS9nY2MvdGVzdHN1aXRlL2djYy50YXJnZXQvYXJtL2Ntc2UvYmFz ZWxpbmUvc29mdGZwLmMgYi9nY2MvdGVzdHN1aXRlL2djYy50YXJnZXQvYXJt L2Ntc2UvYmFzZWxpbmUvc29mdGZwLmMKaW5kZXggM2QzODNmZjZlZTEuLjMw YjNlZWMwNzhjIDEwMDY0NAotLS0gYS9nY2MvdGVzdHN1aXRlL2djYy50YXJn ZXQvYXJtL2Ntc2UvYmFzZWxpbmUvc29mdGZwLmMKKysrIGIvZ2NjL3Rlc3Rz dWl0ZS9nY2MudGFyZ2V0L2FybS9jbXNlL2Jhc2VsaW5lL3NvZnRmcC5jCkBA IC0xLDUgKzEsNyBAQAogLyogeyBkZy1kbyBjb21waWxlIH0gKi8KLS8qIHsg ZGctb3B0aW9ucyAiLW1jbXNlIC1tZmxvYXQtYWJpPXNvZnRmcCIgfSAqLwor LyogRm9yY2UgYW4gRlBVIHRvIHRlc3QgdGhhdCBpdCBpcyBpZ25vcmVkIGZv ciBUaHVtYi0xIC1saWtlIHRhcmdldHMgYW5kIHRoYXQKKyAgIG5vIGNsZWFy aW5nIG9mIFZGUCByZWdpc3RlciBvY2N1cnMuICAqLworLyogeyBkZy1vcHRp b25zICItbWNtc2UgLW1mbG9hdC1hYmk9c29mdGZwIC1tZnB1PWZwdjUtZDE2 IiB9ICovCiAKIGRvdWJsZSBfX2F0dHJpYnV0ZV9fICgoY21zZV9ub25zZWN1 cmVfY2FsbCkpICgqYmFyKSAoZmxvYXQsIGRvdWJsZSk7CiAKLS0gCjIuMTku MQoK --000000000000d9f22f057d01efd6--