From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x533.google.com (mail-ed1-x533.google.com [IPv6:2a00:1450:4864:20::533]) by sourceware.org (Postfix) with ESMTPS id C45193858D1E for ; Thu, 7 Sep 2023 10:15:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C45193858D1E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ed1-x533.google.com with SMTP id 4fb4d7f45d1cf-52a1ce529fdso1026926a12.1 for ; Thu, 07 Sep 2023 03:15:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694081724; x=1694686524; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=oBcul/dpuriLS4r+zcokeDygPQHewZtuAj7Q87B1zNY=; b=OZVNGprVLGA0TWR8/yFPvOqtjjalry/rRTDIJ3ffHnrcdxeHoeHd9praxlj6qFJGhg WRts1gdspiGYfl/f9prkeDjwTomAbL3Y69iFxMu0CO3PZ2sRB+oghWyslVLVAi9EdSup qev2Neo00X09nnely59lL2Or/cXStbXgF/v2B6ZtT3khmqXDJEq3Oj7G2n6vNvjbzoI3 HXEtbbxj4cf2eMWSCQIv4Wmms1WxDnA68leO7sA5WQ5V5Df4IDdlDbFdpbztQRT40L4B 0bQ3LC0b4yqrutcJLNkphnEKVf8E7wOuJZMhO1EHiHr1ZgG0JCDlfKz4RhyA4cR8ClT8 PU9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1694081724; x=1694686524; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oBcul/dpuriLS4r+zcokeDygPQHewZtuAj7Q87B1zNY=; b=TYWJ5cIKhDNGhsfkymRHa10/Knkgmx+dKGuj+EqJWAmxYeEfBoTnXqUeoFqBoZr9O1 MHevaPA+9wpZqUqXm/ueIS/KcloiDTIq/+xH07zQxWoToEyeo/xe+AYtdzEV4sU/V4AY 3X9PjEGfwscpTguQ+cNF0KPhnm2qFdWj+uPdEONcdzpLsRz4cYhNkWdPoG9syxsYD4aO RR4HwoQtVYzE/+RBWJGHWHAbepP+HBgfTL4YKbV4FNGi1ZSTBMZG++ARs1vixIMvVdJO 7c4NOspJx0jnmZGSd6sJXvfKx+dEmkp+fpWeYcaZxtEHq4bak6qdXSx4tNZQZ4Iv3f7z NWJQ== X-Gm-Message-State: AOJu0Yy7Q7/X6BgTScY1qT+2/F0lrBc0cl55JdISxp2zOMG4LnE4KqcO 4Bcgz//nxycgnHfb5Ge+e28kJ/V1r6rwo4u7NkU= X-Google-Smtp-Source: AGHT+IH/2ikuiK0Wa46kEGu4/2AHePWxYpRI44qEB+ecNhG5t23ZJAcxCwoxhTSHD03n7qczOJWXKMMHBLA15Sko2J4= X-Received: by 2002:aa7:da96:0:b0:522:20a0:7eb8 with SMTP id q22-20020aa7da96000000b0052220a07eb8mr4642994eds.33.1694081724145; Thu, 07 Sep 2023 03:15:24 -0700 (PDT) MIME-Version: 1.0 References: <20230906125026.16091-1-shahab@synopsys.com> In-Reply-To: <20230906125026.16091-1-shahab@synopsys.com> From: Claudiu Zissulescu Ianculescu Date: Thu, 7 Sep 2023 13:15:12 +0300 Message-ID: Subject: Re: [PATCH 1/2] ARC: Use intrinsics for __builtin_add_overflow*() To: Shahab Vahedi Cc: gcc-patches@gcc.gnu.org, Francois Bedard Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-9.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Ok. Thank you for your contribution, Claudiu On Wed, Sep 6, 2023 at 3:50=E2=80=AFPM Shahab Vahedi wrote: > > This patch covers signed and unsigned additions. The generated code > would be something along these lines: > > signed: > add.f r0, r1, r2 > b.v @label > > unsigned: > add.f r0, r1, r2 > b.c @label > > gcc/ChangeLog: > > * config/arc/arc-modes.def: Add CC_V mode. > * config/arc/predicates.md (proper_comparison_operator): Handle > E_CC_Vmode. > (equality_comparison_operator): Exclude CC_Vmode from eq/ne. > (cc_set_register): Handle CC_Vmode. > (cc_use_register): Likewise. > * config/arc/arc.md (addsi3_v): New insn. > (addvsi4): New expand. > (addsi3_c): New insn. > (uaddvsi4): New expand. > * config/arc/arc-protos.h (arc_gen_unlikely_cbranch): New. > * config/arc/arc.cc (arc_gen_unlikely_cbranch): New. > (get_arc_condition_code): Handle E_CC_Vmode. > (arc_init_reg_tables): Handle CC_Vmode. > > gcc/testsuite/ChangeLog: > > * gcc.target/arc/overflow-1.c: New. > > Signed-off-by: Shahab Vahedi > --- > gcc/config/arc/arc-modes.def | 1 + > gcc/config/arc/arc-protos.h | 1 + > gcc/config/arc/arc.cc | 26 +++++- > gcc/config/arc/arc.md | 49 +++++++++++ > gcc/config/arc/predicates.md | 14 ++- > gcc/testsuite/gcc.target/arc/overflow-1.c | 100 ++++++++++++++++++++++ > 6 files changed, 187 insertions(+), 4 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/arc/overflow-1.c > > diff --git a/gcc/config/arc/arc-modes.def b/gcc/config/arc/arc-modes.def > index 763e880317d..69eeec5935a 100644 > --- a/gcc/config/arc/arc-modes.def > +++ b/gcc/config/arc/arc-modes.def > @@ -24,6 +24,7 @@ along with GCC; see the file COPYING3. If not see > > CC_MODE (CC_ZN); > CC_MODE (CC_Z); > +CC_MODE (CC_V); > CC_MODE (CC_C); > CC_MODE (CC_FP_GT); > CC_MODE (CC_FP_GE); > diff --git a/gcc/config/arc/arc-protos.h b/gcc/config/arc/arc-protos.h > index 4f2db7ffb59..bc78fb0b370 100644 > --- a/gcc/config/arc/arc-protos.h > +++ b/gcc/config/arc/arc-protos.h > @@ -50,6 +50,7 @@ extern bool arc_check_mov_const (HOST_WIDE_INT ); > extern bool arc_split_mov_const (rtx *); > extern bool arc_can_use_return_insn (void); > extern bool arc_split_move_p (rtx *); > +extern void arc_gen_unlikely_cbranch (enum rtx_code, machine_mode, rtx); > #endif /* RTX_CODE */ > > extern bool arc_ccfsm_branch_deleted_p (void); > diff --git a/gcc/config/arc/arc.cc b/gcc/config/arc/arc.cc > index f8c9bf17e2c..ec93d40aeb9 100644 > --- a/gcc/config/arc/arc.cc > +++ b/gcc/config/arc/arc.cc > @@ -1538,6 +1538,13 @@ get_arc_condition_code (rtx comparison) > case GEU : return ARC_CC_NC; > default : gcc_unreachable (); > } > + case E_CC_Vmode: > + switch (GET_CODE (comparison)) > + { > + case EQ : return ARC_CC_NV; > + case NE : return ARC_CC_V; > + default : gcc_unreachable (); > + } > case E_CC_FP_GTmode: > if (TARGET_ARGONAUT_SET && TARGET_SPFP) > switch (GET_CODE (comparison)) > @@ -1868,7 +1875,7 @@ arc_init_reg_tables (void) > /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, s= o > we must explicitly check for them here. */ > if (i =3D=3D (int) CCmode || i =3D=3D (int) CC_ZNmode || i =3D= =3D (int) CC_Zmode > - || i =3D=3D (int) CC_Cmode > + || i =3D=3D (int) CC_Cmode || i =3D=3D (int) CC_Vmode > || i =3D=3D CC_FP_GTmode || i =3D=3D CC_FP_GEmode || i =3D= =3D CC_FP_ORDmode > || i =3D=3D CC_FPUmode || i =3D=3D CC_FPUEmode || i =3D=3D = CC_FPU_UNEQmode) > arc_mode_class[i] =3D 1 << (int) C_MODE; > @@ -11852,6 +11859,23 @@ arc_libm_function_max_error (unsigned cfn, machi= ne_mode mode, > return default_libm_function_max_error (cfn, mode, boundary_p); > } > > +/* Generate RTL for conditional branch with rtx comparison CODE in mode > + CC_MODE. */ > + > +void > +arc_gen_unlikely_cbranch (enum rtx_code cmp, machine_mode cc_mode, rtx l= abel) > +{ > + rtx cc_reg, x; > + > + cc_reg =3D gen_rtx_REG (cc_mode, CC_REG); > + label =3D gen_rtx_LABEL_REF (VOIDmode, label); > + > + x =3D gen_rtx_fmt_ee (cmp, VOIDmode, cc_reg, const0_rtx); > + x =3D gen_rtx_IF_THEN_ELSE (VOIDmode, x, label, pc_rtx); > + > + emit_unlikely_jump (gen_rtx_SET (pc_rtx, x)); > +} > + > #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P > #define TARGET_USE_ANCHORS_FOR_SYMBOL_P arc_use_anchors_for_symbol_p > > diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md > index d37ecbf4292..9d011f6b4a9 100644 > --- a/gcc/config/arc/arc.md > +++ b/gcc/config/arc/arc.md > @@ -2725,6 +2725,55 @@ archs4x, archs4xd" > } > ") > > +(define_insn "addsi3_v" > + [(set (match_operand:SI 0 "register_operand" "=3Dr,r,r, r") > + (plus:SI (match_operand:SI 1 "register_operand" "r,r,0, r") > + (match_operand:SI 2 "nonmemory_operand" "r,L,I,C32"))) > + (set (reg:CC_V CC_REG) > + (compare:CC_V (sign_extend:DI (plus:SI (match_dup 1) > + (match_dup 2))) > + (plus:DI (sign_extend:DI (match_dup 1)) > + (sign_extend:DI (match_dup 2)))))] > + "" > + "add.f\\t%0,%1,%2" > + [(set_attr "cond" "set") > + (set_attr "type" "compare") > + (set_attr "length" "4,4,4,8")]) > + > +(define_expand "addvsi4" > + [(match_operand:SI 0 "register_operand") > + (match_operand:SI 1 "register_operand") > + (match_operand:SI 2 "nonmemory_operand") > + (label_ref (match_operand 3 "" ""))] > + "" > + "emit_insn (gen_addsi3_v (operands[0], operands[1], operands[2])); > + arc_gen_unlikely_cbranch (NE, CC_Vmode, operands[3]); > + DONE;") > + > +(define_insn "addsi3_c" > + [(set (match_operand:SI 0 "register_operand" "=3Dr,r,r, r") > + (plus:SI (match_operand:SI 1 "register_operand" "r,r,0, r") > + (match_operand:SI 2 "nonmemory_operand" "r,L,I,C32"))) > + (set (reg:CC_C CC_REG) > + (compare:CC_C (plus:SI (match_dup 1) > + (match_dup 2)) > + (match_dup 1)))] > + "" > + "add.f\\t%0,%1,%2" > + [(set_attr "cond" "set") > + (set_attr "type" "compare") > + (set_attr "length" "4,4,4,8")]) > + > +(define_expand "uaddvsi4" > + [(match_operand:SI 0 "register_operand") > + (match_operand:SI 1 "register_operand") > + (match_operand:SI 2 "nonmemory_operand") > + (label_ref (match_operand 3 "" ""))] > + "" > + "emit_insn (gen_addsi3_c (operands[0], operands[1], operands[2])); > + arc_gen_unlikely_cbranch (LTU, CC_Cmode, operands[3]); > + DONE;") > + > (define_expand "adddi3" > [(set (match_operand:DI 0 "register_operand" "") > (plus:DI (match_operand:DI 1 "register_operand" "") > diff --git a/gcc/config/arc/predicates.md b/gcc/config/arc/predicates.md > index 7650e47694d..9a4ecee9bbd 100644 > --- a/gcc/config/arc/predicates.md > +++ b/gcc/config/arc/predicates.md > @@ -426,6 +426,8 @@ > return code =3D=3D EQ || code =3D=3D NE; > case E_CC_Cmode: > return code =3D=3D LTU || code =3D=3D GEU; > + case E_CC_Vmode: > + return code =3D=3D EQ || code =3D=3D NE; > case E_CC_FP_GTmode: > return code =3D=3D GT || code =3D=3D UNLE; > case E_CC_FP_GEmode: > @@ -458,7 +460,12 @@ > }) > > (define_predicate "equality_comparison_operator" > - (match_code "eq, ne")) > + (match_code "eq, ne") > + { > + machine_mode opmode =3D GET_MODE (XEXP (op, 0)); > + return opmode !=3D CC_Vmode; > + } > +) > > (define_predicate "ge_lt_comparison_operator" > (match_code "ge, lt")) > @@ -511,7 +518,8 @@ > || (mode =3D=3D CC_ZNmode && rmode =3D=3D CC_Zmode) > || (mode =3D=3D CCmode && rmode =3D=3D CC_Zmode) > || (mode =3D=3D CCmode && rmode =3D=3D CC_ZNmode) > - || (mode =3D=3D CCmode && rmode =3D=3D CC_Cmode)) > + || (mode =3D=3D CCmode && rmode =3D=3D CC_Cmode) > + || (mode =3D=3D CCmode && rmode =3D=3D CC_Vmode)) > return TRUE; > > return FALSE; > @@ -531,7 +539,7 @@ > if (GET_MODE (op) =3D=3D CC_ZNmode) > return 1; > /* Fall through. */ > - case E_CC_ZNmode: case E_CC_Cmode: > + case E_CC_ZNmode: case E_CC_Cmode: case E_CC_Vmode: > return GET_MODE (op) =3D=3D CCmode; > default: > gcc_unreachable (); > diff --git a/gcc/testsuite/gcc.target/arc/overflow-1.c b/gcc/testsuite/gc= c.target/arc/overflow-1.c > new file mode 100644 > index 00000000000..01b3e8ad0fa > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arc/overflow-1.c > @@ -0,0 +1,100 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O1" } */ > + > +#include > +#include > + > +/* > + * add.f r0,r0,r1 > + * st_s r0,[r2] > + * mov_s r0,1 > + * j_s.d [blink] > + * mov.nv r0,0 > + */ > +bool add_overflow (int32_t a, int32_t b, int32_t *res) > +{ > + return __builtin_add_overflow (a, b, res); > +} > + > +/* > + * add.f r0,r0,-1234 > + * st_s r0,[r1] > + * mov_s r0,1 > + * j_s.d [blink] > + * mov.nv r0,0 > + */ > +bool addi_overflow (int32_t a, int32_t *res) > +{ > + return __builtin_add_overflow (a, -1234, res); > +} > + > +/* > + * add.f r0,r0,r1 > + * st_s r0,[r2] > + * mov_s r0,1 > + * j_s.d [blink] > + * mov.hs r0,0 > + */ > +bool uadd_overflow (uint32_t a, uint32_t b, uint32_t *res) > +{ > + return __builtin_add_overflow (a, b, res); > +} > + > +/* > + * add.f r2,r0, 4321 > + * seths r0,r0,-4321 > + * j_s.d [blink] > + * st_s r2,[r1] > + */ > +bool uaddi_overflow (uint32_t a, uint32_t *res) > +{ > + return __builtin_add_overflow (a, 4321, res); > +} > + > +/* > + * add.f r0,r0,r1 > + * mov_s r0,1 > + * j_s.d [blink] > + * mov.nv r0,0 > + */ > +bool add_overflow_p (int32_t a, int32_t b, int32_t res) > +{ > + return __builtin_add_overflow_p (a, b, res); > +} > + > +/* > + * add.f r0,r0,-1000 > + * mov_s r0,1 > + * j_s.d [blink] > + * mov.nv r0,0 > + */ > +bool addi_overflow_p (int32_t a, int32_t res) > +{ > + return __builtin_add_overflow_p (a, -1000, res); > +} > + > +/* > + * add.f 0,r0,r1 > + * mov_s r0,1 > + * j_s.d [blink] > + * mov.hs r0,0 > + */ > +bool uadd_overflow_p (uint32_t a, uint32_t b, uint32_t res) > +{ > + return __builtin_add_overflow_p (a, b, res); > +} > + > +/* > + * j_s.d [blink] > + * seths r0,r0,-2000 > + */ > +bool uaddi_overflow_p (uint32_t a, uint32_t res) > +{ > + return __builtin_add_overflow_p (a, 2000, res); > +} > + > +/* { dg-final { scan-assembler-times "add.f\\s\+" 7 } } */ > +/* { dg-final { scan-assembler-times "mov\.nv\\s\+" 4 } } */ > +/* { dg-final { scan-assembler-times "mov\.hs\\s\+" 2 } } */ > +/* { dg-final { scan-assembler-times "seths\\s\+" 2 } } */ > +/* { dg-final { scan-assembler-not "cmp" } } */ > -- > 2.42.0 >