* [PATCH 5/5] [ARC] Refactor deprecated macros.
2019-03-06 10:20 [PATCH 0/5][ARC] Fix failing tests and use newer macros Claudiu Zissulescu
` (2 preceding siblings ...)
2019-03-06 10:20 ` [PATCH 3/5] [ARC] Define TARGET_HAVE_SPECULATION_SAFE_VALUE Claudiu Zissulescu
@ 2019-03-06 10:20 ` Claudiu Zissulescu
2019-03-16 15:06 ` Andrew Burgess
2019-03-06 10:22 ` [PATCH 4/5] [ARC] Fix tst_movb pattern Claudiu Zissulescu
2019-03-18 9:51 ` [PATCH 0/5][ARC] Fix failing tests and use newer macros Claudiu Zissulescu
5 siblings, 1 reply; 12+ messages in thread
From: Claudiu Zissulescu @ 2019-03-06 10:20 UTC (permalink / raw)
To: gcc-patches; +Cc: fbedard, andrew.burgess, claziss
xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc-protos.h (arc_register_move_cost): Remove.
* config/arc/arc.c (arc_register_move_cost): Re-purpose it to
implement target hook.
(arc_memory_move_cost): New function.
(TARGET_REGISTER_MOVE_COST): Define.
(TARGET_MEMORY_MOVE_COST): Likewise.
* config/arc/arc.h (REGISTER_MOVE_COST): Remove.
(MEMORY_MOVE_COST): Likewise.
---
gcc/config/arc/arc-protos.h | 2 --
gcc/config/arc/arc.c | 26 ++++++++++++++++++++++++--
gcc/config/arc/arc.h | 11 -----------
3 files changed, 24 insertions(+), 15 deletions(-)
diff --git a/gcc/config/arc/arc-protos.h b/gcc/config/arc/arc-protos.h
index 8f0f197f14a..ac0de6b2874 100644
--- a/gcc/config/arc/arc-protos.h
+++ b/gcc/config/arc/arc-protos.h
@@ -68,8 +68,6 @@ extern bool arc_is_shortcall_p (rtx);
extern bool valid_brcc_with_delay_p (rtx *);
extern bool arc_ccfsm_cond_exec_p (void);
struct secondary_reload_info;
-extern int arc_register_move_cost (machine_mode, enum reg_class,
- enum reg_class);
extern rtx disi_highpart (rtx);
extern int arc_adjust_insn_length (rtx_insn *, int, bool);
extern int arc_corereg_hazard (rtx, rtx);
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index a3a013e90e1..50977704c45 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -8686,9 +8686,11 @@ arc_preserve_reload_p (rtx in)
&& !((INTVAL (XEXP (in, 1)) & 511)));
}
-int
+/* Implement TARGET_REGISTER_MOVE_COST. */
+
+static int
arc_register_move_cost (machine_mode,
- enum reg_class from_class, enum reg_class to_class)
+ reg_class_t from_class, reg_class_t to_class)
{
/* Force an attempt to 'mov Dy,Dx' to spill. */
if ((TARGET_ARC700 || TARGET_EM) && TARGET_DPFP
@@ -11428,6 +11430,20 @@ arc_adjust_reg_alloc_order (void)
memcpy (reg_alloc_order, size_alloc_order, sizeof (size_alloc_order));
}
+/* Implement TARGET_MEMORY_MOVE_COST. */
+
+static int
+arc_memory_move_cost (machine_mode mode,
+ reg_class_t rclass ATTRIBUTE_UNUSED,
+ bool in ATTRIBUTE_UNUSED)
+{
+ if ((GET_MODE_SIZE (mode) <= UNITS_PER_WORD)
+ || ((GET_MODE_SIZE (mode) <= UNITS_PER_WORD * 2) && TARGET_LL64))
+ return 6;
+
+ return (2 * GET_MODE_SIZE (mode));
+}
+
#undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
#define TARGET_USE_ANCHORS_FOR_SYMBOL_P arc_use_anchors_for_symbol_p
@@ -11443,6 +11459,12 @@ arc_adjust_reg_alloc_order (void)
#undef TARGET_HAVE_SPECULATION_SAFE_VALUE
#define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed
+#undef TARGET_REGISTER_MOVE_COST
+#define TARGET_REGISTER_MOVE_COST arc_register_move_cost
+
+#undef TARGET_MEMORY_MOVE_COST
+#define TARGET_MEMORY_MOVE_COST arc_memory_move_cost
+
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-arc.h"
diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
index 90420a9d474..46ca2dde413 100644
--- a/gcc/config/arc/arc.h
+++ b/gcc/config/arc/arc.h
@@ -925,17 +925,6 @@ arc_select_cc_mode (OP, X, Y)
/* Costs. */
-/* Compute extra cost of moving data between one register class
- and another. */
-#define REGISTER_MOVE_COST(MODE, CLASS, TO_CLASS) \
- arc_register_move_cost ((MODE), (CLASS), (TO_CLASS))
-
-/* Compute the cost of moving data between registers and memory. */
-/* Memory is 3 times as expensive as registers.
- ??? Is that the right way to look at it? */
-#define MEMORY_MOVE_COST(MODE,CLASS,IN) \
-(GET_MODE_SIZE (MODE) <= UNITS_PER_WORD ? 6 : 12)
-
/* The cost of a branch insn. */
/* ??? What's the right value here? Branches are certainly more
expensive than reg->reg moves. */
--
2.20.1
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 2/5] [ARC] Enable code density frame option for elf targets.
2019-03-06 10:20 [PATCH 0/5][ARC] Fix failing tests and use newer macros Claudiu Zissulescu
2019-03-06 10:20 ` [PATCH 1/5] [ARC] Introduce ADJUST_REG_ALLOC_ORDER Claudiu Zissulescu
@ 2019-03-06 10:20 ` Claudiu Zissulescu
2019-03-16 11:35 ` Andrew Burgess
2019-03-06 10:20 ` [PATCH 3/5] [ARC] Define TARGET_HAVE_SPECULATION_SAFE_VALUE Claudiu Zissulescu
` (3 subsequent siblings)
5 siblings, 1 reply; 12+ messages in thread
From: Claudiu Zissulescu @ 2019-03-06 10:20 UTC (permalink / raw)
To: gcc-patches; +Cc: fbedard, andrew.burgess, claziss
xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.opt (mcode-density-frame): Get the inital value
from TARGET_CODE_DENSITY_FRAME_DEFAULT.
* config/arc/elf.h (TARGET_CODE_DENSITY_FRAME_DEFAULT): Define it
to 1.
* config/arc/linux.h (TARGET_CODE_DENSITY_FRAME_DEFAULT): Define
it to 0.
---
gcc/config/arc/arc.c | 5 ++++-
gcc/config/arc/arc.md | 20 ++++++++++----------
gcc/config/arc/arc.opt | 2 +-
gcc/config/arc/elf.h | 4 ++++
gcc/config/arc/linux.h | 4 ++++
5 files changed, 23 insertions(+), 12 deletions(-)
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index 0b18e677735..9e086477027 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -1292,6 +1292,9 @@ arc_override_options (void)
if (arc_size_opt_level == 3)
optimize_size = 1;
+ if (TARGET_V2 && optimize_size && (ATTRIBUTE_PCS == 2))
+ TARGET_CODE_DENSITY_FRAME = 1;
+
if (flag_pic)
{
/* If we had SDATA enabled, still don't use GP when pic is
@@ -3188,7 +3191,7 @@ arc_save_callee_enter (unsigned int gmask,
reg = gen_rtx_SET (stack_pointer_rtx,
plus_constant (Pmode,
stack_pointer_rtx,
- nregs * UNITS_PER_WORD));
+ -nregs * UNITS_PER_WORD));
RTX_FRAME_RELATED_P (reg) = 1;
XVECEXP (insn, 0, indx++) = reg;
off = nregs * UNITS_PER_WORD;
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 54d073107a8..c64a7fdb653 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -6442,7 +6442,7 @@ core_3, archs4x, archs4xd, archs4xd_slow"
(plus:SI (reg:SI SP_REG)
(match_operand 1 "immediate_operand" "")))
(set (mem:SI (plus:SI (reg:SI SP_REG)
- (match_dup 1)))
+ (match_operand 2 "immediate_operand" "")))
(reg:SI 13))])]
"TARGET_CODE_DENSITY"
{
@@ -6450,14 +6450,14 @@ core_3, archs4x, archs4xd, archs4xd_slow"
rtx tmp = XVECEXP (operands[0], 0, len - 1);
if (MEM_P (XEXP (tmp, 0)))
{
- operands[2] = XEXP (tmp, 1);
- return "enter_s\\t{r13-%2} ; sp=sp-%1";
+ operands[3] = XEXP (tmp, 1);
+ return "enter_s\\t{r13-%3} ; sp=sp+(%1)";
}
else
{
tmp = XVECEXP (operands[0], 0, len - 3);
- operands[2] = XEXP (tmp, 1);
- return "enter_s\\t{r13-%2, fp} ; sp=sp-%1";
+ operands[3] = XEXP (tmp, 1);
+ return "enter_s\\t{r13-%3, fp} ; sp=sp+(%1)";
}
}
[(set_attr "type" "call_no_delay_slot")
@@ -6469,7 +6469,7 @@ core_3, archs4x, archs4xd, archs4xd_slow"
(plus:SI (reg:SI SP_REG)
(match_operand 1 "immediate_operand" "")))
(set (mem:SI (plus:SI (reg:SI SP_REG)
- (match_dup 1)))
+ (match_operand 2 "immediate_operand" "")))
(reg:SI RETURN_ADDR_REGNUM))])]
"TARGET_CODE_DENSITY"
{
@@ -6477,14 +6477,14 @@ core_3, archs4x, archs4xd, archs4xd_slow"
rtx tmp = XVECEXP (operands[0], 0, len - 1);
if (MEM_P (XEXP (tmp, 0)))
{
- operands[2] = XEXP (tmp, 1);
- return "enter_s\\t{r13-%2, blink} ; sp=sp-%1";
+ operands[3] = XEXP (tmp, 1);
+ return "enter_s\\t{r13-%3, blink} ; sp=sp+(%1)";
}
else
{
tmp = XVECEXP (operands[0], 0, len - 3);
- operands[2] = XEXP (tmp, 1);
- return "enter_s\\t{r13-%2, fp, blink} ; sp=sp-%1";
+ operands[3] = XEXP (tmp, 1);
+ return "enter_s\\t{r13-%3, fp, blink} ; sp=sp+(%1)";
}
}
[(set_attr "type" "call_no_delay_slot")
diff --git a/gcc/config/arc/arc.opt b/gcc/config/arc/arc.opt
index a5271cbbceb..567df30951f 100644
--- a/gcc/config/arc/arc.opt
+++ b/gcc/config/arc/arc.opt
@@ -537,5 +537,5 @@ Target Report Var(TARGET_BRANCH_INDEX) Init(DEFAULT_BRANCH_INDEX)
Enable use of BI/BIH instructions when available.
mcode-density-frame
-Target Report Var(TARGET_CODE_DENSITY_FRAME)
+Target Report Var(TARGET_CODE_DENSITY_FRAME) Init(TARGET_CODE_DENSITY_FRAME_DEFAULT)
Enable ENTER_S and LEAVE_S opcodes for ARCv2.
diff --git a/gcc/config/arc/elf.h b/gcc/config/arc/elf.h
index 8f9bec05606..651741f3342 100644
--- a/gcc/config/arc/elf.h
+++ b/gcc/config/arc/elf.h
@@ -98,3 +98,7 @@ along with GCC; see the file COPYING3. If not see
fixed_regs[GP_REG] = 0; \
arc_regno_reg_class[GP_REG] = GENERAL_REGS; \
}
+
+/* Enter/Leave ops are default on for elf targets. */
+#undef TARGET_CODE_DENSITY_FRAME_DEFAULT
+#define TARGET_CODE_DENSITY_FRAME_DEFAULT 0
diff --git a/gcc/config/arc/linux.h b/gcc/config/arc/linux.h
index 6c8a7b46296..270ca907d87 100644
--- a/gcc/config/arc/linux.h
+++ b/gcc/config/arc/linux.h
@@ -133,3 +133,7 @@ along with GCC; see the file COPYING3. If not see
fun = gen_rtx_SYMBOL_REF (Pmode, "_mcount"); \
emit_library_call (fun, LCT_NORMAL, VOIDmode, rt, Pmode); \
}
+
+/* Enter/Leave ops are default off for linux targets. */
+#undef TARGET_CODE_DENSITY_FRAME_DEFAULT
+#define TARGET_CODE_DENSITY_FRAME_DEFAULT 0
--
2.20.1
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 3/5] [ARC] Define TARGET_HAVE_SPECULATION_SAFE_VALUE.
2019-03-06 10:20 [PATCH 0/5][ARC] Fix failing tests and use newer macros Claudiu Zissulescu
2019-03-06 10:20 ` [PATCH 1/5] [ARC] Introduce ADJUST_REG_ALLOC_ORDER Claudiu Zissulescu
2019-03-06 10:20 ` [PATCH 2/5] [ARC] Enable code density frame option for elf targets Claudiu Zissulescu
@ 2019-03-06 10:20 ` Claudiu Zissulescu
2019-03-16 11:37 ` Andrew Burgess
2019-03-06 10:20 ` [PATCH 5/5] [ARC] Refactor deprecated macros Claudiu Zissulescu
` (2 subsequent siblings)
5 siblings, 1 reply; 12+ messages in thread
From: Claudiu Zissulescu @ 2019-03-06 10:20 UTC (permalink / raw)
To: gcc-patches; +Cc: fbedard, andrew.burgess, claziss
xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.c (TARGET_HAVE_SPECULATION_SAFE_VALUE): Define.
---
gcc/config/arc/arc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index 9e086477027..a3a013e90e1 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -11440,6 +11440,9 @@ arc_adjust_reg_alloc_order (void)
#undef TARGET_ASM_TRAMPOLINE_TEMPLATE
#define TARGET_ASM_TRAMPOLINE_TEMPLATE arc_asm_trampoline_template
+#undef TARGET_HAVE_SPECULATION_SAFE_VALUE
+#define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed
+
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-arc.h"
--
2.20.1
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 0/5][ARC] Fix failing tests and use newer macros.
@ 2019-03-06 10:20 Claudiu Zissulescu
2019-03-06 10:20 ` [PATCH 1/5] [ARC] Introduce ADJUST_REG_ALLOC_ORDER Claudiu Zissulescu
` (5 more replies)
0 siblings, 6 replies; 12+ messages in thread
From: Claudiu Zissulescu @ 2019-03-06 10:20 UTC (permalink / raw)
To: gcc-patches; +Cc: fbedard, andrew.burgess, claziss
Hi,
Please find a set of 5 patches as this:
[ARC] Introduce ADJUST_REG_ALLOC_ORDER.
This patch just cleans the old way of changing the register allocation order and uses a gcc macro specially made for this task.
[ARC] Enable code density frame option for elf targets.
The compress instruction for frame are there for a while, but they are not enabled by default when using Os, just do it.
[ARC] Define TARGET_HAVE_SPECULATION_SAFE_VALUE.
New macro fixes a dejagnu failure.
[ARC] Fix tst_movb pattern.
Fixes dejagnu failure.
[ARC] Refactor deprecated macros.
Old macros replaced with their newer equivalent.
Thanks,
Claudiu
gcc/config/arc/arc-protos.h | 3 +-
gcc/config/arc/arc.c | 101 ++++++++++++++++++------------------
gcc/config/arc/arc.h | 44 ++++++++++------
gcc/config/arc/arc.md | 24 ++++-----
gcc/config/arc/arc.opt | 2 +-
gcc/config/arc/elf.h | 4 ++
gcc/config/arc/linux.h | 4 ++
7 files changed, 99 insertions(+), 83 deletions(-)
--
2.20.1
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 1/5] [ARC] Introduce ADJUST_REG_ALLOC_ORDER.
2019-03-06 10:20 [PATCH 0/5][ARC] Fix failing tests and use newer macros Claudiu Zissulescu
@ 2019-03-06 10:20 ` Claudiu Zissulescu
2019-03-16 11:32 ` Andrew Burgess
2019-03-06 10:20 ` [PATCH 2/5] [ARC] Enable code density frame option for elf targets Claudiu Zissulescu
` (4 subsequent siblings)
5 siblings, 1 reply; 12+ messages in thread
From: Claudiu Zissulescu @ 2019-03-06 10:20 UTC (permalink / raw)
To: gcc-patches; +Cc: fbedard, andrew.burgess, claziss
The ARC port is changing the allocation order in the
arc_conditional_register_usage function, but this is not the proper
way. Thus, we employ ADJUST_REG_ALLOC_ORDER hook for this task.
gcc/
xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc-protos.h (arc_adjust_reg_alloc_order): Declare.
* config/arc/arc.c (arc_conditional_register_usage): Remove all
reg_alloc_order references.
(size_alloc_order): Define.
(arc_adjust_reg_alloc_order): New function.
* config/arc/arc.h (REG_ALLOC_ORDER): Proper define the register
order.
(ADJUST_REG_ALLOC_ORDER): Define.
(HONOR_REG_ALLOC_ORDER): Likewise.
---
gcc/config/arc/arc-protos.h | 1 +
gcc/config/arc/arc.c | 67 +++++++++++--------------------------
gcc/config/arc/arc.h | 33 ++++++++++++++----
3 files changed, 47 insertions(+), 54 deletions(-)
diff --git a/gcc/config/arc/arc-protos.h b/gcc/config/arc/arc-protos.h
index 1362b41f101..8f0f197f14a 100644
--- a/gcc/config/arc/arc-protos.h
+++ b/gcc/config/arc/arc-protos.h
@@ -47,6 +47,7 @@ extern unsigned int arc_compute_function_type (struct function *);
extern bool arc_is_uncached_mem_p (rtx);
extern bool gen_operands_ldd_std (rtx *operands, bool load, bool commute);
extern bool arc_check_multi (rtx, bool);
+extern void arc_adjust_reg_alloc_order (void);
#endif /* RTX_CODE */
extern unsigned int arc_compute_frame_size (int);
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index 9938a774d91..0b18e677735 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -1807,54 +1807,6 @@ arc_conditional_register_usage (void)
warning (0, "multiply option implies r%d is fixed", regno);
fixed_regs [regno] = call_used_regs[regno] = 1;
}
- if (TARGET_Q_CLASS)
- {
- if (optimize_size)
- {
- reg_alloc_order[0] = 0;
- reg_alloc_order[1] = 1;
- reg_alloc_order[2] = 2;
- reg_alloc_order[3] = 3;
- reg_alloc_order[4] = 12;
- reg_alloc_order[5] = 13;
- reg_alloc_order[6] = 14;
- reg_alloc_order[7] = 15;
- reg_alloc_order[8] = 4;
- reg_alloc_order[9] = 5;
- reg_alloc_order[10] = 6;
- reg_alloc_order[11] = 7;
- reg_alloc_order[12] = 8;
- reg_alloc_order[13] = 9;
- reg_alloc_order[14] = 10;
- reg_alloc_order[15] = 11;
- }
- else
- {
- reg_alloc_order[2] = 12;
- reg_alloc_order[3] = 13;
- reg_alloc_order[4] = 14;
- reg_alloc_order[5] = 15;
- reg_alloc_order[6] = 1;
- reg_alloc_order[7] = 0;
- reg_alloc_order[8] = 4;
- reg_alloc_order[9] = 5;
- reg_alloc_order[10] = 6;
- reg_alloc_order[11] = 7;
- reg_alloc_order[12] = 8;
- reg_alloc_order[13] = 9;
- reg_alloc_order[14] = 10;
- reg_alloc_order[15] = 11;
- }
- }
- if (TARGET_SIMD_SET)
- {
- int i;
- for (i = ARC_FIRST_SIMD_VR_REG; i <= ARC_LAST_SIMD_VR_REG; i++)
- reg_alloc_order [i] = i;
- for (i = ARC_FIRST_SIMD_DMA_CONFIG_REG;
- i <= ARC_LAST_SIMD_DMA_CONFIG_REG; i++)
- reg_alloc_order [i] = i;
- }
/* Reduced configuration: don't use r4-r9, r16-r25. */
if (TARGET_RF16)
@@ -11454,6 +11406,25 @@ gen_operands_ldd_std (rtx *operands, bool load, bool commute)
return false;
}
+/* This order of allocation is used when we compile for size. It
+ allocates first the registers which are most probably to end up in
+ a short instruction. */
+static const int size_alloc_order[] =
+{
+ 0, 1, 2, 3, 12, 13, 14, 15,
+ 4, 5, 6, 7, 8, 9, 10, 11
+};
+
+/* Adjust register allocation order when compiling for size. */
+void
+arc_adjust_reg_alloc_order (void)
+{
+ const int arc_default_alloc_order[] = REG_ALLOC_ORDER;
+ memcpy (reg_alloc_order, arc_default_alloc_order, sizeof (reg_alloc_order));
+ if (optimize_size)
+ memcpy (reg_alloc_order, size_alloc_order, sizeof (size_alloc_order));
+}
+
#undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
#define TARGET_USE_ANCHORS_FOR_SYMBOL_P arc_use_anchors_for_symbol_p
diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
index fbe71278346..90420a9d474 100644
--- a/gcc/config/arc/arc.h
+++ b/gcc/config/arc/arc.h
@@ -361,7 +361,6 @@ if (GET_MODE_CLASS (MODE) == MODE_INT \
By default, the extension registers are not available. */
/* Present implementations only have VR0-VR23 only. */
-/* ??? FIXME: r27 and r31 should not be fixed registers. */
#define FIXED_REGISTERS \
{ 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, \
@@ -422,12 +421,34 @@ if (GET_MODE_CLASS (MODE) == MODE_INT \
/* If defined, an initializer for a vector of integers, containing the
numbers of hard registers in the order in which GCC should
prefer to use them (from most preferred to least). */
-#define REG_ALLOC_ORDER \
-{ 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, \
- 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, \
+#define REG_ALLOC_ORDER \
+{ \
+ /* General registers. */ \
+ 2, 3, 12, 13, 14, 15, 1, 0, 4, 5, 6, 7, 8, 9, 10, 11, \
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 30, \
+ /* Extension core registers. */ \
32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
- 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, \
- 27, 28, 29, 30, 31, 63}
+ 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \
+ /* VR regs. */ \
+ 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
+ 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
+ 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, \
+ 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, \
+ 124, 125, 126, 127, \
+ /* DMA registers. */ \
+ 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, \
+ 142, 143, \
+ /* Register not used for general use. */ \
+ 62, FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \
+ SP_REG, ILINK1_REG, RETURN_ADDR_REGNUM, LP_COUNT, CC_REG, PCL_REG \
+}
+
+/* Use different register alloc ordering for Thumb. */
+#define ADJUST_REG_ALLOC_ORDER arc_adjust_reg_alloc_order ()
+
+/* Tell IRA to use the order we define rather than messing it up with its
+ own cost calculations. */
+#define HONOR_REG_ALLOC_ORDER 1
/* Internal macros to classify a register number as to whether it's a
general purpose register for compact insns (r0-r3,r12-r15), or
--
2.20.1
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 4/5] [ARC] Fix tst_movb pattern.
2019-03-06 10:20 [PATCH 0/5][ARC] Fix failing tests and use newer macros Claudiu Zissulescu
` (3 preceding siblings ...)
2019-03-06 10:20 ` [PATCH 5/5] [ARC] Refactor deprecated macros Claudiu Zissulescu
@ 2019-03-06 10:22 ` Claudiu Zissulescu
2019-03-16 11:41 ` Andrew Burgess
2019-03-18 9:51 ` [PATCH 0/5][ARC] Fix failing tests and use newer macros Claudiu Zissulescu
5 siblings, 1 reply; 12+ messages in thread
From: Claudiu Zissulescu @ 2019-03-06 10:22 UTC (permalink / raw)
To: gcc-patches; +Cc: fbedard, andrew.burgess, claziss
xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.md (tst_movb): Fix constraint.
---
gcc/config/arc/arc.md | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index c64a7fdb653..1e64331f397 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -958,10 +958,10 @@ core_3, archs4x, archs4xd, archs4xd_slow"
(match_operand 0 "cc_register" "")
(match_operator 4 "zn_compare_operator"
[(and:SI
- (match_operand:SI 1 "register_operand" "%Rcq,Rcq, c, c, c, c,Rrq, 3, c")
+ (match_operand:SI 1 "register_operand" "%Rcq,Rcq, c, c, c, c,Rrq,Rrq, c")
(match_operand:SI 2 "nonmemory_operand" "Rcq,C0p,cI,C1p,Ccp,Chs,Cbf,Cbf,???Cal"))
(const_int 0)]))
- (clobber (match_scratch:SI 3 "=X,X,X,X,X,X,Rrq,Rrq,c"))]
+ (clobber (match_scratch:SI 3 "=X,X,X,X,X,X,Rrq,1,c"))]
"TARGET_NPS_BITOPS"
"movb.f.cl %3,%1,%p2,%p2,%s2"
"TARGET_NPS_BITOPS && reload_completed
--
2.20.1
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/5] [ARC] Introduce ADJUST_REG_ALLOC_ORDER.
2019-03-06 10:20 ` [PATCH 1/5] [ARC] Introduce ADJUST_REG_ALLOC_ORDER Claudiu Zissulescu
@ 2019-03-16 11:32 ` Andrew Burgess
0 siblings, 0 replies; 12+ messages in thread
From: Andrew Burgess @ 2019-03-16 11:32 UTC (permalink / raw)
To: Claudiu Zissulescu; +Cc: gcc-patches, fbedard, claziss
* Claudiu Zissulescu <claziss@gmail.com> [2019-03-06 12:20:01 +0200]:
> The ARC port is changing the allocation order in the
> arc_conditional_register_usage function, but this is not the proper
> way. Thus, we employ ADJUST_REG_ALLOC_ORDER hook for this task.
>
> gcc/
> xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com>
>
> * config/arc/arc-protos.h (arc_adjust_reg_alloc_order): Declare.
> * config/arc/arc.c (arc_conditional_register_usage): Remove all
> reg_alloc_order references.
> (size_alloc_order): Define.
> (arc_adjust_reg_alloc_order): New function.
> * config/arc/arc.h (REG_ALLOC_ORDER): Proper define the register
> order.
> (ADJUST_REG_ALLOC_ORDER): Define.
> (HONOR_REG_ALLOC_ORDER): Likewise.
This seems like a good improvement.
Thanks,
Andrew
> ---
> gcc/config/arc/arc-protos.h | 1 +
> gcc/config/arc/arc.c | 67 +++++++++++--------------------------
> gcc/config/arc/arc.h | 33 ++++++++++++++----
> 3 files changed, 47 insertions(+), 54 deletions(-)
>
> diff --git a/gcc/config/arc/arc-protos.h b/gcc/config/arc/arc-protos.h
> index 1362b41f101..8f0f197f14a 100644
> --- a/gcc/config/arc/arc-protos.h
> +++ b/gcc/config/arc/arc-protos.h
> @@ -47,6 +47,7 @@ extern unsigned int arc_compute_function_type (struct function *);
> extern bool arc_is_uncached_mem_p (rtx);
> extern bool gen_operands_ldd_std (rtx *operands, bool load, bool commute);
> extern bool arc_check_multi (rtx, bool);
> +extern void arc_adjust_reg_alloc_order (void);
> #endif /* RTX_CODE */
>
> extern unsigned int arc_compute_frame_size (int);
> diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
> index 9938a774d91..0b18e677735 100644
> --- a/gcc/config/arc/arc.c
> +++ b/gcc/config/arc/arc.c
> @@ -1807,54 +1807,6 @@ arc_conditional_register_usage (void)
> warning (0, "multiply option implies r%d is fixed", regno);
> fixed_regs [regno] = call_used_regs[regno] = 1;
> }
> - if (TARGET_Q_CLASS)
> - {
> - if (optimize_size)
> - {
> - reg_alloc_order[0] = 0;
> - reg_alloc_order[1] = 1;
> - reg_alloc_order[2] = 2;
> - reg_alloc_order[3] = 3;
> - reg_alloc_order[4] = 12;
> - reg_alloc_order[5] = 13;
> - reg_alloc_order[6] = 14;
> - reg_alloc_order[7] = 15;
> - reg_alloc_order[8] = 4;
> - reg_alloc_order[9] = 5;
> - reg_alloc_order[10] = 6;
> - reg_alloc_order[11] = 7;
> - reg_alloc_order[12] = 8;
> - reg_alloc_order[13] = 9;
> - reg_alloc_order[14] = 10;
> - reg_alloc_order[15] = 11;
> - }
> - else
> - {
> - reg_alloc_order[2] = 12;
> - reg_alloc_order[3] = 13;
> - reg_alloc_order[4] = 14;
> - reg_alloc_order[5] = 15;
> - reg_alloc_order[6] = 1;
> - reg_alloc_order[7] = 0;
> - reg_alloc_order[8] = 4;
> - reg_alloc_order[9] = 5;
> - reg_alloc_order[10] = 6;
> - reg_alloc_order[11] = 7;
> - reg_alloc_order[12] = 8;
> - reg_alloc_order[13] = 9;
> - reg_alloc_order[14] = 10;
> - reg_alloc_order[15] = 11;
> - }
> - }
> - if (TARGET_SIMD_SET)
> - {
> - int i;
> - for (i = ARC_FIRST_SIMD_VR_REG; i <= ARC_LAST_SIMD_VR_REG; i++)
> - reg_alloc_order [i] = i;
> - for (i = ARC_FIRST_SIMD_DMA_CONFIG_REG;
> - i <= ARC_LAST_SIMD_DMA_CONFIG_REG; i++)
> - reg_alloc_order [i] = i;
> - }
>
> /* Reduced configuration: don't use r4-r9, r16-r25. */
> if (TARGET_RF16)
> @@ -11454,6 +11406,25 @@ gen_operands_ldd_std (rtx *operands, bool load, bool commute)
> return false;
> }
>
> +/* This order of allocation is used when we compile for size. It
> + allocates first the registers which are most probably to end up in
> + a short instruction. */
> +static const int size_alloc_order[] =
> +{
> + 0, 1, 2, 3, 12, 13, 14, 15,
> + 4, 5, 6, 7, 8, 9, 10, 11
> +};
> +
> +/* Adjust register allocation order when compiling for size. */
> +void
> +arc_adjust_reg_alloc_order (void)
> +{
> + const int arc_default_alloc_order[] = REG_ALLOC_ORDER;
> + memcpy (reg_alloc_order, arc_default_alloc_order, sizeof (reg_alloc_order));
> + if (optimize_size)
> + memcpy (reg_alloc_order, size_alloc_order, sizeof (size_alloc_order));
> +}
> +
> #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
> #define TARGET_USE_ANCHORS_FOR_SYMBOL_P arc_use_anchors_for_symbol_p
>
> diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
> index fbe71278346..90420a9d474 100644
> --- a/gcc/config/arc/arc.h
> +++ b/gcc/config/arc/arc.h
> @@ -361,7 +361,6 @@ if (GET_MODE_CLASS (MODE) == MODE_INT \
>
> By default, the extension registers are not available. */
> /* Present implementations only have VR0-VR23 only. */
> -/* ??? FIXME: r27 and r31 should not be fixed registers. */
> #define FIXED_REGISTERS \
> { 0, 0, 0, 0, 0, 0, 0, 0, \
> 0, 0, 0, 0, 0, 0, 0, 0, \
> @@ -422,12 +421,34 @@ if (GET_MODE_CLASS (MODE) == MODE_INT \
> /* If defined, an initializer for a vector of integers, containing the
> numbers of hard registers in the order in which GCC should
> prefer to use them (from most preferred to least). */
> -#define REG_ALLOC_ORDER \
> -{ 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, \
> - 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, \
> +#define REG_ALLOC_ORDER \
> +{ \
> + /* General registers. */ \
> + 2, 3, 12, 13, 14, 15, 1, 0, 4, 5, 6, 7, 8, 9, 10, 11, \
> + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 30, \
> + /* Extension core registers. */ \
> 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
> - 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, \
> - 27, 28, 29, 30, 31, 63}
> + 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \
> + /* VR regs. */ \
> + 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
> + 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
> + 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, \
> + 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, \
> + 124, 125, 126, 127, \
> + /* DMA registers. */ \
> + 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, \
> + 142, 143, \
> + /* Register not used for general use. */ \
> + 62, FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \
> + SP_REG, ILINK1_REG, RETURN_ADDR_REGNUM, LP_COUNT, CC_REG, PCL_REG \
> +}
> +
> +/* Use different register alloc ordering for Thumb. */
> +#define ADJUST_REG_ALLOC_ORDER arc_adjust_reg_alloc_order ()
> +
> +/* Tell IRA to use the order we define rather than messing it up with its
> + own cost calculations. */
> +#define HONOR_REG_ALLOC_ORDER 1
>
> /* Internal macros to classify a register number as to whether it's a
> general purpose register for compact insns (r0-r3,r12-r15), or
> --
> 2.20.1
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/5] [ARC] Enable code density frame option for elf targets.
2019-03-06 10:20 ` [PATCH 2/5] [ARC] Enable code density frame option for elf targets Claudiu Zissulescu
@ 2019-03-16 11:35 ` Andrew Burgess
0 siblings, 0 replies; 12+ messages in thread
From: Andrew Burgess @ 2019-03-16 11:35 UTC (permalink / raw)
To: Claudiu Zissulescu; +Cc: gcc-patches, fbedard, claziss
* Claudiu Zissulescu <claziss@gmail.com> [2019-03-06 12:20:02 +0200]:
> xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com>
>
> * config/arc/arc.opt (mcode-density-frame): Get the inital value
> from TARGET_CODE_DENSITY_FRAME_DEFAULT.
> * config/arc/elf.h (TARGET_CODE_DENSITY_FRAME_DEFAULT): Define it
> to 1.
> * config/arc/linux.h (TARGET_CODE_DENSITY_FRAME_DEFAULT): Define
> it to 0.
In general this looks fine, but there's a few nits inline....
Thanks,
Andrew
> ---
> gcc/config/arc/arc.c | 5 ++++-
> gcc/config/arc/arc.md | 20 ++++++++++----------
These changes don't appear in the ChangeLog file.
> gcc/config/arc/arc.opt | 2 +-
> gcc/config/arc/elf.h | 4 ++++
> gcc/config/arc/linux.h | 4 ++++
> 5 files changed, 23 insertions(+), 12 deletions(-)
>
> diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
> index 0b18e677735..9e086477027 100644
> --- a/gcc/config/arc/arc.c
> +++ b/gcc/config/arc/arc.c
> @@ -1292,6 +1292,9 @@ arc_override_options (void)
> if (arc_size_opt_level == 3)
> optimize_size = 1;
>
> + if (TARGET_V2 && optimize_size && (ATTRIBUTE_PCS == 2))
> + TARGET_CODE_DENSITY_FRAME = 1;
> +
> if (flag_pic)
> {
> /* If we had SDATA enabled, still don't use GP when pic is
> @@ -3188,7 +3191,7 @@ arc_save_callee_enter (unsigned int gmask,
> reg = gen_rtx_SET (stack_pointer_rtx,
> plus_constant (Pmode,
> stack_pointer_rtx,
> - nregs * UNITS_PER_WORD));
> + -nregs * UNITS_PER_WORD));
> RTX_FRAME_RELATED_P (reg) = 1;
> XVECEXP (insn, 0, indx++) = reg;
> off = nregs * UNITS_PER_WORD;
> diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
> index 54d073107a8..c64a7fdb653 100644
> --- a/gcc/config/arc/arc.md
> +++ b/gcc/config/arc/arc.md
> @@ -6442,7 +6442,7 @@ core_3, archs4x, archs4xd, archs4xd_slow"
> (plus:SI (reg:SI SP_REG)
> (match_operand 1 "immediate_operand" "")))
> (set (mem:SI (plus:SI (reg:SI SP_REG)
> - (match_dup 1)))
> + (match_operand 2 "immediate_operand" "")))
> (reg:SI 13))])]
> "TARGET_CODE_DENSITY"
> {
> @@ -6450,14 +6450,14 @@ core_3, archs4x, archs4xd, archs4xd_slow"
> rtx tmp = XVECEXP (operands[0], 0, len - 1);
> if (MEM_P (XEXP (tmp, 0)))
> {
> - operands[2] = XEXP (tmp, 1);
> - return "enter_s\\t{r13-%2} ; sp=sp-%1";
> + operands[3] = XEXP (tmp, 1);
> + return "enter_s\\t{r13-%3} ; sp=sp+(%1)";
> }
> else
> {
> tmp = XVECEXP (operands[0], 0, len - 3);
> - operands[2] = XEXP (tmp, 1);
> - return "enter_s\\t{r13-%2, fp} ; sp=sp-%1";
> + operands[3] = XEXP (tmp, 1);
> + return "enter_s\\t{r13-%3, fp} ; sp=sp+(%1)";
> }
> }
> [(set_attr "type" "call_no_delay_slot")
> @@ -6469,7 +6469,7 @@ core_3, archs4x, archs4xd, archs4xd_slow"
> (plus:SI (reg:SI SP_REG)
> (match_operand 1 "immediate_operand" "")))
> (set (mem:SI (plus:SI (reg:SI SP_REG)
> - (match_dup 1)))
> + (match_operand 2 "immediate_operand" "")))
> (reg:SI RETURN_ADDR_REGNUM))])]
> "TARGET_CODE_DENSITY"
> {
> @@ -6477,14 +6477,14 @@ core_3, archs4x, archs4xd, archs4xd_slow"
> rtx tmp = XVECEXP (operands[0], 0, len - 1);
> if (MEM_P (XEXP (tmp, 0)))
> {
> - operands[2] = XEXP (tmp, 1);
> - return "enter_s\\t{r13-%2, blink} ; sp=sp-%1";
> + operands[3] = XEXP (tmp, 1);
> + return "enter_s\\t{r13-%3, blink} ; sp=sp+(%1)";
> }
> else
> {
> tmp = XVECEXP (operands[0], 0, len - 3);
> - operands[2] = XEXP (tmp, 1);
> - return "enter_s\\t{r13-%2, fp, blink} ; sp=sp-%1";
> + operands[3] = XEXP (tmp, 1);
> + return "enter_s\\t{r13-%3, fp, blink} ; sp=sp+(%1)";
> }
> }
> [(set_attr "type" "call_no_delay_slot")
> diff --git a/gcc/config/arc/arc.opt b/gcc/config/arc/arc.opt
> index a5271cbbceb..567df30951f 100644
> --- a/gcc/config/arc/arc.opt
> +++ b/gcc/config/arc/arc.opt
> @@ -537,5 +537,5 @@ Target Report Var(TARGET_BRANCH_INDEX) Init(DEFAULT_BRANCH_INDEX)
> Enable use of BI/BIH instructions when available.
>
> mcode-density-frame
> -Target Report Var(TARGET_CODE_DENSITY_FRAME)
> +Target Report Var(TARGET_CODE_DENSITY_FRAME) Init(TARGET_CODE_DENSITY_FRAME_DEFAULT)
> Enable ENTER_S and LEAVE_S opcodes for ARCv2.
> diff --git a/gcc/config/arc/elf.h b/gcc/config/arc/elf.h
> index 8f9bec05606..651741f3342 100644
> --- a/gcc/config/arc/elf.h
> +++ b/gcc/config/arc/elf.h
> @@ -98,3 +98,7 @@ along with GCC; see the file COPYING3. If not see
> fixed_regs[GP_REG] = 0; \
> arc_regno_reg_class[GP_REG] = GENERAL_REGS; \
> }
> +
> +/* Enter/Leave ops are default on for elf targets. */
> +#undef TARGET_CODE_DENSITY_FRAME_DEFAULT
> +#define TARGET_CODE_DENSITY_FRAME_DEFAULT 0
You comment/email-subject says on, your code says off :)
> diff --git a/gcc/config/arc/linux.h b/gcc/config/arc/linux.h
> index 6c8a7b46296..270ca907d87 100644
> --- a/gcc/config/arc/linux.h
> +++ b/gcc/config/arc/linux.h
> @@ -133,3 +133,7 @@ along with GCC; see the file COPYING3. If not see
> fun = gen_rtx_SYMBOL_REF (Pmode, "_mcount"); \
> emit_library_call (fun, LCT_NORMAL, VOIDmode, rt, Pmode); \
> }
> +
> +/* Enter/Leave ops are default off for linux targets. */
> +#undef TARGET_CODE_DENSITY_FRAME_DEFAULT
> +#define TARGET_CODE_DENSITY_FRAME_DEFAULT 0
> --
> 2.20.1
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 3/5] [ARC] Define TARGET_HAVE_SPECULATION_SAFE_VALUE.
2019-03-06 10:20 ` [PATCH 3/5] [ARC] Define TARGET_HAVE_SPECULATION_SAFE_VALUE Claudiu Zissulescu
@ 2019-03-16 11:37 ` Andrew Burgess
0 siblings, 0 replies; 12+ messages in thread
From: Andrew Burgess @ 2019-03-16 11:37 UTC (permalink / raw)
To: Claudiu Zissulescu; +Cc: gcc-patches, fbedard, claziss
* Claudiu Zissulescu <claziss@gmail.com> [2019-03-06 12:20:03 +0200]:
> xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com>
>
> * config/arc/arc.c (TARGET_HAVE_SPECULATION_SAFE_VALUE): Define.
This is fine.
Thanks,
Andrew
> ---
> gcc/config/arc/arc.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
> index 9e086477027..a3a013e90e1 100644
> --- a/gcc/config/arc/arc.c
> +++ b/gcc/config/arc/arc.c
> @@ -11440,6 +11440,9 @@ arc_adjust_reg_alloc_order (void)
> #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
> #define TARGET_ASM_TRAMPOLINE_TEMPLATE arc_asm_trampoline_template
>
> +#undef TARGET_HAVE_SPECULATION_SAFE_VALUE
> +#define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed
> +
> struct gcc_target targetm = TARGET_INITIALIZER;
>
> #include "gt-arc.h"
> --
> 2.20.1
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 4/5] [ARC] Fix tst_movb pattern.
2019-03-06 10:22 ` [PATCH 4/5] [ARC] Fix tst_movb pattern Claudiu Zissulescu
@ 2019-03-16 11:41 ` Andrew Burgess
0 siblings, 0 replies; 12+ messages in thread
From: Andrew Burgess @ 2019-03-16 11:41 UTC (permalink / raw)
To: Claudiu Zissulescu; +Cc: gcc-patches, fbedard, claziss
* Claudiu Zissulescu <claziss@gmail.com> [2019-03-06 12:20:04 +0200]:
> xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com>
>
> * config/arc/arc.md (tst_movb): Fix constraint.
This is fine.
Thanks,
Andrew
> ---
> gcc/config/arc/arc.md | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
> index c64a7fdb653..1e64331f397 100644
> --- a/gcc/config/arc/arc.md
> +++ b/gcc/config/arc/arc.md
> @@ -958,10 +958,10 @@ core_3, archs4x, archs4xd, archs4xd_slow"
> (match_operand 0 "cc_register" "")
> (match_operator 4 "zn_compare_operator"
> [(and:SI
> - (match_operand:SI 1 "register_operand" "%Rcq,Rcq, c, c, c, c,Rrq, 3, c")
> + (match_operand:SI 1 "register_operand" "%Rcq,Rcq, c, c, c, c,Rrq,Rrq, c")
> (match_operand:SI 2 "nonmemory_operand" "Rcq,C0p,cI,C1p,Ccp,Chs,Cbf,Cbf,???Cal"))
> (const_int 0)]))
> - (clobber (match_scratch:SI 3 "=X,X,X,X,X,X,Rrq,Rrq,c"))]
> + (clobber (match_scratch:SI 3 "=X,X,X,X,X,X,Rrq,1,c"))]
> "TARGET_NPS_BITOPS"
> "movb.f.cl %3,%1,%p2,%p2,%s2"
> "TARGET_NPS_BITOPS && reload_completed
> --
> 2.20.1
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 5/5] [ARC] Refactor deprecated macros.
2019-03-06 10:20 ` [PATCH 5/5] [ARC] Refactor deprecated macros Claudiu Zissulescu
@ 2019-03-16 15:06 ` Andrew Burgess
0 siblings, 0 replies; 12+ messages in thread
From: Andrew Burgess @ 2019-03-16 15:06 UTC (permalink / raw)
To: Claudiu Zissulescu; +Cc: gcc-patches, fbedard, claziss
* Claudiu Zissulescu <claziss@gmail.com> [2019-03-06 12:20:05 +0200]:
> xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com>
>
> * config/arc/arc-protos.h (arc_register_move_cost): Remove.
> * config/arc/arc.c (arc_register_move_cost): Re-purpose it to
> implement target hook.
> (arc_memory_move_cost): New function.
> (TARGET_REGISTER_MOVE_COST): Define.
> (TARGET_MEMORY_MOVE_COST): Likewise.
> * config/arc/arc.h (REGISTER_MOVE_COST): Remove.
> (MEMORY_MOVE_COST): Likewise.
This is fine.
Thanks,
Andrew
> ---
> gcc/config/arc/arc-protos.h | 2 --
> gcc/config/arc/arc.c | 26 ++++++++++++++++++++++++--
> gcc/config/arc/arc.h | 11 -----------
> 3 files changed, 24 insertions(+), 15 deletions(-)
>
> diff --git a/gcc/config/arc/arc-protos.h b/gcc/config/arc/arc-protos.h
> index 8f0f197f14a..ac0de6b2874 100644
> --- a/gcc/config/arc/arc-protos.h
> +++ b/gcc/config/arc/arc-protos.h
> @@ -68,8 +68,6 @@ extern bool arc_is_shortcall_p (rtx);
> extern bool valid_brcc_with_delay_p (rtx *);
> extern bool arc_ccfsm_cond_exec_p (void);
> struct secondary_reload_info;
> -extern int arc_register_move_cost (machine_mode, enum reg_class,
> - enum reg_class);
> extern rtx disi_highpart (rtx);
> extern int arc_adjust_insn_length (rtx_insn *, int, bool);
> extern int arc_corereg_hazard (rtx, rtx);
> diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
> index a3a013e90e1..50977704c45 100644
> --- a/gcc/config/arc/arc.c
> +++ b/gcc/config/arc/arc.c
> @@ -8686,9 +8686,11 @@ arc_preserve_reload_p (rtx in)
> && !((INTVAL (XEXP (in, 1)) & 511)));
> }
>
> -int
> +/* Implement TARGET_REGISTER_MOVE_COST. */
> +
> +static int
> arc_register_move_cost (machine_mode,
> - enum reg_class from_class, enum reg_class to_class)
> + reg_class_t from_class, reg_class_t to_class)
> {
> /* Force an attempt to 'mov Dy,Dx' to spill. */
> if ((TARGET_ARC700 || TARGET_EM) && TARGET_DPFP
> @@ -11428,6 +11430,20 @@ arc_adjust_reg_alloc_order (void)
> memcpy (reg_alloc_order, size_alloc_order, sizeof (size_alloc_order));
> }
>
> +/* Implement TARGET_MEMORY_MOVE_COST. */
> +
> +static int
> +arc_memory_move_cost (machine_mode mode,
> + reg_class_t rclass ATTRIBUTE_UNUSED,
> + bool in ATTRIBUTE_UNUSED)
> +{
> + if ((GET_MODE_SIZE (mode) <= UNITS_PER_WORD)
> + || ((GET_MODE_SIZE (mode) <= UNITS_PER_WORD * 2) && TARGET_LL64))
> + return 6;
> +
> + return (2 * GET_MODE_SIZE (mode));
> +}
> +
> #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
> #define TARGET_USE_ANCHORS_FOR_SYMBOL_P arc_use_anchors_for_symbol_p
>
> @@ -11443,6 +11459,12 @@ arc_adjust_reg_alloc_order (void)
> #undef TARGET_HAVE_SPECULATION_SAFE_VALUE
> #define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed
>
> +#undef TARGET_REGISTER_MOVE_COST
> +#define TARGET_REGISTER_MOVE_COST arc_register_move_cost
> +
> +#undef TARGET_MEMORY_MOVE_COST
> +#define TARGET_MEMORY_MOVE_COST arc_memory_move_cost
> +
> struct gcc_target targetm = TARGET_INITIALIZER;
>
> #include "gt-arc.h"
> diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
> index 90420a9d474..46ca2dde413 100644
> --- a/gcc/config/arc/arc.h
> +++ b/gcc/config/arc/arc.h
> @@ -925,17 +925,6 @@ arc_select_cc_mode (OP, X, Y)
>
> /* Costs. */
>
> -/* Compute extra cost of moving data between one register class
> - and another. */
> -#define REGISTER_MOVE_COST(MODE, CLASS, TO_CLASS) \
> - arc_register_move_cost ((MODE), (CLASS), (TO_CLASS))
> -
> -/* Compute the cost of moving data between registers and memory. */
> -/* Memory is 3 times as expensive as registers.
> - ??? Is that the right way to look at it? */
> -#define MEMORY_MOVE_COST(MODE,CLASS,IN) \
> -(GET_MODE_SIZE (MODE) <= UNITS_PER_WORD ? 6 : 12)
> -
> /* The cost of a branch insn. */
> /* ??? What's the right value here? Branches are certainly more
> expensive than reg->reg moves. */
> --
> 2.20.1
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 0/5][ARC] Fix failing tests and use newer macros.
2019-03-06 10:20 [PATCH 0/5][ARC] Fix failing tests and use newer macros Claudiu Zissulescu
` (4 preceding siblings ...)
2019-03-06 10:22 ` [PATCH 4/5] [ARC] Fix tst_movb pattern Claudiu Zissulescu
@ 2019-03-18 9:51 ` Claudiu Zissulescu
5 siblings, 0 replies; 12+ messages in thread
From: Claudiu Zissulescu @ 2019-03-18 9:51 UTC (permalink / raw)
To: gcc-patches; +Cc: Francois Bedard, Andrew Burgess, claziss@gmail.com
Thanks Andrew for your review,
Claudiu
On Wed, Mar 6, 2019 at 12:20 PM Claudiu Zissulescu <claziss@gmail.com> wrote:
>
> Hi,
>
> Please find a set of 5 patches as this:
>
> [ARC] Introduce ADJUST_REG_ALLOC_ORDER.
> This patch just cleans the old way of changing the register allocation order and uses a gcc macro specially made for this task.
>
> [ARC] Enable code density frame option for elf targets.
> The compress instruction for frame are there for a while, but they are not enabled by default when using Os, just do it.
>
> [ARC] Define TARGET_HAVE_SPECULATION_SAFE_VALUE.
> New macro fixes a dejagnu failure.
>
> [ARC] Fix tst_movb pattern.
> Fixes dejagnu failure.
>
> [ARC] Refactor deprecated macros.
> Old macros replaced with their newer equivalent.
>
>
> Thanks,
> Claudiu
>
> gcc/config/arc/arc-protos.h | 3 +-
> gcc/config/arc/arc.c | 101 ++++++++++++++++++------------------
> gcc/config/arc/arc.h | 44 ++++++++++------
> gcc/config/arc/arc.md | 24 ++++-----
> gcc/config/arc/arc.opt | 2 +-
> gcc/config/arc/elf.h | 4 ++
> gcc/config/arc/linux.h | 4 ++
> 7 files changed, 99 insertions(+), 83 deletions(-)
>
> --
> 2.20.1
>
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2019-03-18 9:30 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-03-06 10:20 [PATCH 0/5][ARC] Fix failing tests and use newer macros Claudiu Zissulescu
2019-03-06 10:20 ` [PATCH 1/5] [ARC] Introduce ADJUST_REG_ALLOC_ORDER Claudiu Zissulescu
2019-03-16 11:32 ` Andrew Burgess
2019-03-06 10:20 ` [PATCH 2/5] [ARC] Enable code density frame option for elf targets Claudiu Zissulescu
2019-03-16 11:35 ` Andrew Burgess
2019-03-06 10:20 ` [PATCH 3/5] [ARC] Define TARGET_HAVE_SPECULATION_SAFE_VALUE Claudiu Zissulescu
2019-03-16 11:37 ` Andrew Burgess
2019-03-06 10:20 ` [PATCH 5/5] [ARC] Refactor deprecated macros Claudiu Zissulescu
2019-03-16 15:06 ` Andrew Burgess
2019-03-06 10:22 ` [PATCH 4/5] [ARC] Fix tst_movb pattern Claudiu Zissulescu
2019-03-16 11:41 ` Andrew Burgess
2019-03-18 9:51 ` [PATCH 0/5][ARC] Fix failing tests and use newer macros Claudiu Zissulescu
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