From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [IPv6:2a00:1450:4864:20::62a]) by sourceware.org (Postfix) with ESMTPS id 66029385772B for ; Mon, 30 Oct 2023 13:45:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 66029385772B Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 66029385772B Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::62a ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698673534; cv=none; b=i0c4YFfBqo5YlFJ+AHMv/R1GXFZ11++FhXbrrx5P6mtRoIYlbREP05MIkgdpm3TAUpbMYpsQXqjCIXL0uDZp11hQlZR+B22edgM6yoW3f5HDlXXD6SQJ1fhd5ndFtEyjQkxdGs+x9CmjQ1CKmznlZ3Ik7Pn/NDOwNPekBhqDMEY= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698673534; c=relaxed/simple; bh=6PTDwG2P6jYjLVJ3rOxlKrfjS72Ck1l9GfKz6CLJ1rI=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=YsuU3dpuL+USmFq/r57F9IVYbJAhF72m9RIdizd65EC5UKH04JQHktffAcfcr/lWLce8Wxb7p2SkyrJ74XHdSrjqNaJ2q272jrnnE4pUk5YuW+HY4DWLIsg8N32JUpsQI0A7Bzzn6TAd6NCBGsqWbMBRnpXfgeY33ttLlYFvyC0= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-ej1-x62a.google.com with SMTP id a640c23a62f3a-99de884ad25so687906866b.3 for ; Mon, 30 Oct 2023 06:45:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1698673531; x=1699278331; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=zgjDhMmtvyacyX+Fh8KlJOETabuE4FiMMALODQybliY=; b=I4HelUjeHxCq29kLEqn/pYgvDGzCKKfdnAIwLH27sJIrzfgKo7JV6VEgnJcaVTvMSB oKiY3guIRWjkfVG2Sj7SAKvO2AE2MDk+i5XcDZhef3vnzLEN6cfgHWuKPRPGJTOZDiAm m0MbB2+ByM71UmscBVsxN+0M2IJ4tP6xW/QhzpRO9DJgCAxKmOivFHO8iRDgOvVk8PKB Z+mcS3lvf6FmLFAR4TX9tm7Nits6vj+1qKs9L9ucQiievo7GLmMGRh8pXRiV+TdKNmEi wAOdkqq7/DwHHukcouu6Y8G98052nO3c9GVtqqc9LM2KWAsGiXj3xbxJZwkapaG1eaan 8HpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698673531; x=1699278331; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zgjDhMmtvyacyX+Fh8KlJOETabuE4FiMMALODQybliY=; b=CKhNrt08inYgd1J0m+CMYLW6+DGd5RpZGddTVDWjxJwyITsVO9Z5SHmcHO2TjXDwfX KkSGUhJ89QRmjKeZnfiq9Ey3Y1qBvDSPw/riTxvBpI4fvTdAVaL6ltVRoOuteE7Kk41B RL7fdoXXsvusyG088RBgtCcbvbxG0U5nJ2KBb6MTrZ3UCGHfx7vczNHr4VHPmVfRWYNw Ktr0sdmTJFzl0jOaGhdFg3LIGg5SiQCR/K0F3bj801MObsYoSfSSGDteu/AEZCorpCIM 5zjRC017rIGjCLkkJlhCLfvTpCukhJdYYaT30EQIdC+pFFe6CFkmOfDBkva/mKNXDJL4 5IDQ== X-Gm-Message-State: AOJu0YwZAl52/P6bJLxSjGAo7XRk14LD87ZVUhpG4CC5NFEX8zILMTaU siQDNPozCO8Kd4LKNowNhekTYfilhMktjCuOaojqxiUjFZit8w== X-Google-Smtp-Source: AGHT+IFBqwSNrJWNfasIT7M7QTShaQOjD6ctnqu5n+C0hLN/QgKNKvvKiTop1gVpvrpM3oBdVvgACzOpUbPzgIgNnTc= X-Received: by 2002:a17:907:2d92:b0:9c8:f128:2fdb with SMTP id gt18-20020a1709072d9200b009c8f1282fdbmr8007815ejc.13.1698673530845; Mon, 30 Oct 2023 06:45:30 -0700 (PDT) MIME-Version: 1.0 References: <014601da0a48$a3d6b010$eb841030$@nextmovesoftware.com> In-Reply-To: <014601da0a48$a3d6b010$eb841030$@nextmovesoftware.com> From: Claudiu Zissulescu Ianculescu Date: Mon, 30 Oct 2023 15:45:19 +0200 Message-ID: Subject: Re: [ARC PATCH] Improved ARC rtx_costs/insn_cost for SHIFTs and ROTATEs. To: Roger Sayle Cc: gcc-patches@gcc.gnu.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-3.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Roger, You have a block of 8 spaces that needs to be replaced by tabs: gcc/config/arc/arc.cc:5538:0: if (n < 4) Please fix the above, and proceed with your commit. Thank you, Claudiu On Sun, Oct 29, 2023 at 11:16=E2=80=AFAM Roger Sayle wrote: > > > This patch overhauls the ARC backend's insn_cost target hook, and makes > some related improvements to rtx_costs, BRANCH_COST, etc. The primary > goal is to allow the backend to indicate that shifts and rotates are > slow (discouraged) when the CPU doesn't have a barrel shifter. I should > also acknowledge Richard Sandiford for inspiring the use of set_cost > in this rewrite of arc_insn_cost; this implementation borrows heavily > for the target hooks for AArch64 and ARM. > > The motivating example is derived from PR rtl-optimization/110717. > > struct S { int a : 5; }; > unsigned int foo (struct S *p) { > return p->a; > } > > With a barrel shifter, GCC -O2 generates the reasonable: > > foo: ldb_s r0,[r0] > asl_s r0,r0,27 > j_s.d [blink] > asr_s r0,r0,27 > > What's interesting is that during combine, the middle-end actually > has two shifts by three bits, and a sign-extension from QI to SI. > > Trying 8, 9 -> 11: > 8: r158:SI=3Dr157:QI#0<<0x3 > REG_DEAD r157:QI > 9: r159:SI=3Dsign_extend(r158:SI#0) > REG_DEAD r158:SI > 11: r155:SI=3Dr159:SI>>0x3 > REG_DEAD r159:SI > > Whilst it's reasonable to simplify this to two shifts by 27 bits when > the CPU has a barrel shifter, it's actually a significant pessimization > when these shifts are implemented by loops. This combination can be > prevented if the backend provides accurate-ish estimates for insn_cost. > > > Previously, without a barrel shifter, GCC -O2 -mcpu=3Dem generates: > > foo: ldb_s r0,[r0] > mov lp_count,27 > lp 2f > add r0,r0,r0 > nop > 2: # end single insn loop > mov lp_count,27 > lp 2f > asr r0,r0 > nop > 2: # end single insn loop > j_s [blink] > > which contains two loops and requires about ~113 cycles to execute. > With this patch to rtx_cost/insn_cost, GCC -O2 -mcpu=3Dem generates: > > foo: ldb_s r0,[r0] > mov_s r2,0 ;3 > add3 r0,r2,r0 > sexb_s r0,r0 > asr_s r0,r0 > asr_s r0,r0 > j_s.d [blink] > asr_s r0,r0 > > which requires only ~6 cycles, for the shorter shifts by 3 and sign > extension. > > > Tested with a cross-compiler to arc-linux hosted on x86_64, > with no new (compile-only) regressions from make -k check. > Ok for mainline if this passes Claudiu's nightly testing? > > > 2023-10-29 Roger Sayle > > gcc/ChangeLog > * config/arc/arc.cc (arc_rtx_costs): Improve cost estimates. > Provide reasonable values for SHIFTS and ROTATES by constant > bit counts depending upon TARGET_BARREL_SHIFTER. > (arc_insn_cost): Use insn attributes if the instruction is > recognized. Avoid calling get_attr_length for type "multi", > i.e. define_insn_and_split patterns without explicit type. > Fall-back to set_rtx_cost for single_set and pattern_cost > otherwise. > * config/arc/arc.h (COSTS_N_BYTES): Define helper macro. > (BRANCH_COST): Improve/correct definition. > (LOGICAL_OP_NON_SHORT_CIRCUIT): Preserve previous behavior. > > > Thanks again, > Roger > -- >