From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pg1-x52d.google.com (mail-pg1-x52d.google.com [IPv6:2607:f8b0:4864:20::52d]) by sourceware.org (Postfix) with ESMTPS id BCFFF3858C52 for ; Wed, 24 May 2023 07:18:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org BCFFF3858C52 Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-pg1-x52d.google.com with SMTP id 41be03b00d2f7-53f158ecfe1so53478a12.0 for ; Wed, 24 May 2023 00:18:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1684912712; x=1687504712; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=cPZCG1yHFRwtx1Co0P63tqweVbzQs1bvlxF3JNEboBQ=; b=VRI2aKcCFXFGujhADvJw5zBxCorCMV+btox2oXPnWPsKxUHFniVig9it5y8MdQ+uQF QPImX+VZqmJTuGJlUjaFyptpsmqWsjZw9sISgUa4prxrYWE2uLka+RWhmMgPmpfoTFAh 9XQtveV5ws7S63bcvhCLn7Ez6+HfZnZlPsfEo0qxrOXqBuAW56v+qVTQhF+t92tsiXDO 2JLo4mc4As5lSgQrWrRWWPg6JxA5ukz7eJKT7nETIPafEWTVE/GMS5GOokVCctch9a64 hOhUUKZEHhE8CGslH70Fen9G2q3Tb9mMQwf3nrM2eObJlL97R32AfKZzHdnkZm5o9kVR KWZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684912712; x=1687504712; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cPZCG1yHFRwtx1Co0P63tqweVbzQs1bvlxF3JNEboBQ=; b=gpkvHMgzgQCu+NMsEun0b1XVZGNJFTnS409tDeAOSnI9DIeoxF9WiVKOhpTI3c/X6f R/La/EaRzJorcc6QIJnBSnCvTxLc5S8aeNNiV998PTdJO0CUKuiuCpvbY0dIsxOUZGnn haNX5AjlHXZA3eyO1TolDcai4RhOk6xvRMWExk6Vcqnjc5lYBIt/5GCjDNNljvlI0xhH Nyro+ArMIpNAIpj2dLGd+0Yjgdn7WYhK7NIwOR6iRyVsfhWbnozJDUBImIxP3stcDpH4 vgV7p1yJH3JsrIT+NRSSg68zFCxHwl9rP7iZFaPw8JOzFl1ILeQa4OqKLDyvQqe47qKb c9CQ== X-Gm-Message-State: AC+VfDx+Ab8BhzClvf3lgHBzLe+rHfHWUIc9WiFzYGon806LSKs78B6N EpjJzwn82MDO/VCVWK/CqlaQGpEFRkipmY8ZYGWHsQ== X-Google-Smtp-Source: ACHHUZ42Abp8U7yK+yZblWZIZOh9uzdqNpda+tN/wBXgDc0zYqIvXn2zRnIiAutE5oW35JuMQNm3W0o/AIh36uUcUII= X-Received: by 2002:a17:902:d382:b0:1aa:86a4:37ed with SMTP id e2-20020a170902d38200b001aa86a437edmr17735089pld.55.1684912712493; Wed, 24 May 2023 00:18:32 -0700 (PDT) MIME-Version: 1.0 References: <20230524070329.1163656-1-juzhe.zhong@rivai.ai> In-Reply-To: <20230524070329.1163656-1-juzhe.zhong@rivai.ai> From: Kito Cheng Date: Wed, 24 May 2023 15:18:21 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Add RVV mask logic auto-vectorization To: juzhe.zhong@rivai.ai Cc: gcc-patches@gcc.gnu.org, kito.cheng@gmail.com, palmer@dabbelt.com, palmer@rivosinc.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-9.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_ASCII_DIVIDERS,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Just one comment: define_insn_and_split should be used in this scenario rather than define_insn_and_rewrite since you are not really rewriting. You can commit after updating to define_insn_and_split :) On Wed, May 24, 2023 at 3:04=E2=80=AFPM wrote: > > From: Juzhe-Zhong > > This patch is adding mask logic auto-vectorization. > define the pattern as "define_insn_and_split" to allow > combine PASS easily combine series instructions. > > For example: > combine vmxor.mm + vmnot.m into vmxnor.mm > > Build success and regression PASS > > Ok for trunk ? > > gcc/ChangeLog: > > * config/riscv/autovec.md (3): New pattern. > (one_cmpl2): Ditto. > (*not): Ditto. > (*n): Ditto. > * config/riscv/riscv-v.cc (expand_vec_cmp_float): Change to one_c= mpl. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/autovec/cmp/vcond-4.c: New test. > * gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c: New test. > > --- > gcc/config/riscv/autovec.md | 95 +++++++++++++++++++ > gcc/config/riscv/riscv-v.cc | 7 +- > .../riscv/rvv/autovec/cmp/vcond-4.c | 53 +++++++++++ > .../riscv/rvv/autovec/cmp/vcond_run-4.c | 35 +++++++ > 4 files changed, 187 insertions(+), 3 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-= 4.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_= run-4.c > > diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md > index 4eeeab624a4..cacf27e4e60 100644 > --- a/gcc/config/riscv/autovec.md > +++ b/gcc/config/riscv/autovec.md > @@ -163,6 +163,101 @@ > DONE; > }) > > +;; ---------------------------------------------------------------------= ---- > +;; ---- [BOOL] Binary logical operations > +;; ---------------------------------------------------------------------= ---- > +;; Includes: > +;; - vmand.mm > +;; - vmxor.mm > +;; - vmor.mm > +;; ---------------------------------------------------------------------= ---- > + > +(define_insn_and_rewrite "3" > + [(set (match_operand:VB 0 "register_operand" "=3Dvr") > + (any_bitwise:VB (match_operand:VB 1 "register_operand" " vr") > + (match_operand:VB 2 "register_operand" " vr")))] > + "TARGET_VECTOR" > + "#" > + "&& can_create_pseudo_p ()" > + { > + insn_code icode =3D code_for_pred (, mode); > + riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_BINOP, opera= nds); > + DONE; > + } > + [(set_attr "type" "vmalu") > + (set_attr "mode" "")]) > + > +;; ---------------------------------------------------------------------= ---- > +;; ---- [BOOL] Inverse > +;; ---------------------------------------------------------------------= ---- > +;; Includes: > +;; - vmnot.m > +;; ---------------------------------------------------------------------= ---- > + > +(define_insn_and_rewrite "one_cmpl2" > + [(set (match_operand:VB 0 "register_operand" "=3Dvr") > + (not:VB (match_operand:VB 1 "register_operand" " vr")))] > + "TARGET_VECTOR" > + "#" > + "&& can_create_pseudo_p ()" > + { > + insn_code icode =3D code_for_pred_not (mode); > + riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, operan= ds); > + DONE; > + } > + [(set_attr "type" "vmalu") > + (set_attr "mode" "")]) > + > +;; ---------------------------------------------------------------------= ---- > +;; ---- [BOOL] Binary logical operations (inverted second input) > +;; ---------------------------------------------------------------------= ---- > +;; Includes: > +;; - vmandnot.mm > +;; - vmornot.mm > +;; ---------------------------------------------------------------------= ---- > + > +(define_insn_and_rewrite "*not" > + [(set (match_operand:VB 0 "register_operand" "=3Dvr") > + (bitmanip_bitwise:VB > + (not:VB (match_operand:VB 2 "register_operand" " vr")) > + (match_operand:VB 1 "register_operand" " vr")))] > + "TARGET_VECTOR" > + "#" > + "&& can_create_pseudo_p ()" > + { > + insn_code icode =3D code_for_pred_not (, mode); > + riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_BINOP, opera= nds); > + DONE; > + } > + [(set_attr "type" "vmalu") > + (set_attr "mode" "")]) > + > +;; ---------------------------------------------------------------------= ---- > +;; ---- [BOOL] Binary logical operations (inverted result) > +;; ---------------------------------------------------------------------= ---- > +;; Includes: > +;; - vmnand.mm > +;; - vmnor.mm > +;; - vmxnor.mm > +;; ---------------------------------------------------------------------= ---- > + > +(define_insn_and_rewrite "*n" > + [(set (match_operand:VB 0 "register_operand" "=3Dvr") > + (not:VB > + (any_bitwise:VB > + (match_operand:VB 1 "register_operand" " vr") > + (match_operand:VB 2 "register_operand" " vr"))))] > + "TARGET_VECTOR" > + "#" > + "&& can_create_pseudo_p ()" > + { > + insn_code icode =3D code_for_pred_n (, mode); > + riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_BINOP, opera= nds); > + DONE; > + } > + [(set_attr "type" "vmalu") > + (set_attr "mode" "")]) > + > ;; =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > ;; =3D=3D Comparisons and selects > ;; =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc > index 10de5a19937..f71ad9e46a1 100644 > --- a/gcc/config/riscv/riscv-v.cc > +++ b/gcc/config/riscv/riscv-v.cc > @@ -1550,9 +1550,10 @@ expand_vec_cmp_float (rtx target, rtx_code code, r= tx op0, rtx op1, > emit_move_insn (target, eq0); > return true; > } > - insn_code icode =3D code_for_pred_not (mask_mode); > - rtx ops[] =3D {target, eq0}; > - emit_vlmax_insn (icode, RVV_UNOP, ops); > + > + /* We use one_cmpl2 to make Combine PASS to combine mask instruc= tions > + into: vmand.mm/vmnor.mm/vmnand.mm/vmnor.mm/vmxnor.mm. */ > + emit_insn (gen_rtx_SET (target, gen_rtx_NOT (mask_mode, eq0))); > return false; > } > > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-4.c b/g= cc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-4.c > new file mode 100644 > index 00000000000..435a59c97f2 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-4.c > @@ -0,0 +1,53 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-march=3Drv32gcv -mabi=3Dilp32d --param=3Dri= scv-autovec-preference=3Dscalable" } */ > + > +#include > + > +#define b_and(A, B) ((A) & (B)) > +#define b_orr(A, B) ((A) | (B)) > +#define b_xor(A, B) ((A) ^ (B)) > +#define b_nand(A, B) (!((A) & (B))) > +#define b_nor(A, B) (!((A) | (B))) > +#define b_xnor(A, B) (!(A) ^ (B)) > +#define b_andnot(A, B) ((A) & !(B)) > +#define b_ornot(A, B) ((A) | !(B)) > + > +#define LOOP(TYPE, BINOP) = \ > + void __attribute__ ((noinline, noclone)) = \ > + test_##TYPE##_##BINOP (TYPE *restrict dest, TYPE *restrict src, = \ > + TYPE *restrict a, TYPE *restrict b, TYPE *restri= ct c, \ > + TYPE *restrict d, TYPE fallback, int count) = \ > + { = \ > + for (int i =3D 0; i < count; ++i) = \ > + { = \ > + TYPE srcv =3D src[i]; = \ > + dest[i] =3D (BINOP (__builtin_isunordered (a[i], b[i]), = \ > + __builtin_isunordered (c[i], d[i])) = \ > + ? srcv = \ > + : fallback); = \ > + } = \ > + } > + > +#define TEST_BINOP(T, BINOP) = \ > + T (float, BINOP) = \ > + T (double, BINOP) > + > +#define TEST_ALL(T) = \ > + TEST_BINOP (T, b_and) = \ > + TEST_BINOP (T, b_orr) = \ > + TEST_BINOP (T, b_xor) = \ > + TEST_BINOP (T, b_nand) = \ > + TEST_BINOP (T, b_nor) = \ > + TEST_BINOP (T, b_xnor) = \ > + TEST_BINOP (T, b_andnot) = \ > + TEST_BINOP (T, b_ornot) > + > +TEST_ALL (LOOP) > + > +/* { dg-final { scan-assembler-times {\tvmand\.mm} 2 } } */ > +/* { dg-final { scan-assembler-times {\tvmor\.mm} 2 } } */ > +/* { dg-final { scan-assembler-times {\tvmxor\.mm} 2 } } */ > +/* { dg-final { scan-assembler-times {\tvmnot\.m} 4 } } */ > +/* { dg-final { scan-assembler-times {\tvmxnor\.mm} 2 } } */ > +/* { dg-final { scan-assembler-times {\tvmandn\.mm} 4 } } */ > +/* { dg-final { scan-assembler-times {\tvmorn\.mm} 4 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c= b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c > new file mode 100644 > index 00000000000..6c45c274c33 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c > @@ -0,0 +1,35 @@ > +/* { dg-do run { target { riscv_vector } } } */ > +/* { dg-additional-options "--param=3Driscv-autovec-preference=3Dscalabl= e" } */ > + > +#include "vcond-4.c" > + > +#define N 401 > + > +#define RUN_LOOP(TYPE, BINOP) \ > + { \ > + TYPE dest[N], src[N], a[N], b[N], c[N], d[N]; \ > + for (int i =3D 0; i < N; ++i) = \ > + { = \ > + src[i] =3D i * i; = \ > + a[i] =3D i % 5 < 3 ? __builtin_nan("") : i; = \ > + b[i] =3D i % 7 < 4 ? __builtin_nan("") : i; = \ > + c[i] =3D i % 9 < 5 ? __builtin_nan("") : i; = \ > + d[i] =3D i % 11 < 6 ? __builtin_nan("") : i; = \ > + asm volatile ("" ::: "memory"); \ > + } = \ > + test_##TYPE##_##BINOP (dest, src, a, b, c, d, 100, N); \ > + for (int i =3D 0; i < N; ++i) = \ > + { = \ > + int res =3D BINOP (__builtin_isunordered (a[i], b[i]), = \ > + __builtin_isunordered (c[i], d[i])); \ > + if (dest[i] !=3D (res ? src[i] : 100.0)) = \ > + __builtin_abort (); \ > + } = \ > + } > + > +int __attribute__ ((optimize (1))) > +main (void) > +{ > + TEST_ALL (RUN_LOOP) > + return 0; > +} > -- > 2.36.3 >