From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lj1-x22a.google.com (mail-lj1-x22a.google.com [IPv6:2a00:1450:4864:20::22a]) by sourceware.org (Postfix) with ESMTPS id C92CE3858039 for ; Mon, 18 Sep 2023 08:01:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C92CE3858039 Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-lj1-x22a.google.com with SMTP id 38308e7fff4ca-2bffe2840adso16418241fa.2 for ; Mon, 18 Sep 2023 01:01:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1695024083; x=1695628883; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=Ts+/5r7sS+EVQ7HxnNCOR5KkDXEUpbZVkhbBV1vOp/M=; b=kbWma5HlFxqc7Z8VeEWYMHrVU6s4hUOuAQxhNVTAQv8GoluOfEqeGAcVGkf9pK7d10 /jQjTep6zRcBcGZltU+RIKccNE4S7dXhvbY3bEJg189qg2qFX9L7XphYWzerlwXScmRh xuMhEWEbI+WYsAn0xuNvJHq4u2e8V4HzkoLUS6Su+adn3/OQCkmiRMMJO8qrH5N90dhp GoEnGs8v9W80+AbzGU2iarr8+tirBtQzn5PdFbAHdb5KC7ceCyLIGL8v7rAR6a1jBq7B VMpOkrWeI/MuGvUQaLl/nYb1lNo5pDnezQKr28i7EBNgxlCcUmqGOwPTFHRt5TRFx/vE q7+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695024083; x=1695628883; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ts+/5r7sS+EVQ7HxnNCOR5KkDXEUpbZVkhbBV1vOp/M=; b=Je/gKdaWTO6zchoU/hfgEdiBLlUIXZcFTs5ZeOVDK8KMOQgnzZPOF7nC9GBeoFpLwF MtkknladkPcdtN19gfXI8rwAnJCHjLx3H8P0eCulb85k/xKA8hiaXOgaJiKtiEplj4IB tkIYpmYNVEuwS04bLJth9cSNKIo+R6FmirzeE3HJxoSe22zhYvPQ0sSV2bos8xjieUlZ JY41pV+xsAwTOqR2R+RBtxwC3i6NWBsGBd9Nu/RrEBg/N9ThFXdQ+aLG9qOSui72F+VN h3oywb6Lzb118WcNaACD+m5Fu8D9h309Y9bJF6NqEwuhC6aVlvSLGimV1z3H0hQrpSfa mkVA== X-Gm-Message-State: AOJu0Yyko6H3VheW/XwFsXNgYkKM5zNT7FyK6Ou59jcX3DixdyEO6p0s dQvMddIW1hfmbZKlgqeJxKL1mL4L+N2zfLmtbIxUTA== X-Google-Smtp-Source: AGHT+IG9luhL60TACp9pXfez209FAf3VTYa3g5glYK9xbUhy4Joz6FDiGTus0CBWEKA8eGWYt7jEHARZxTgIuPMSWrk= X-Received: by 2002:a2e:9c02:0:b0:2bc:bb01:bfe6 with SMTP id s2-20020a2e9c02000000b002bcbb01bfe6mr7568374lji.21.1695024083018; Mon, 18 Sep 2023 01:01:23 -0700 (PDT) MIME-Version: 1.0 References: <20230918070713.3569601-1-juzhe.zhong@rivai.ai> In-Reply-To: <20230918070713.3569601-1-juzhe.zhong@rivai.ai> From: Kito Cheng Date: Mon, 18 Sep 2023 16:01:11 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Remove autovec-vls.md file and clean up VLS move modes[NFC] To: Juzhe-Zhong Cc: gcc-patches@gcc.gnu.org, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_ASCII_DIVIDERS,KAM_SHORT,MEDICAL_SUBJECT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: LGTM :) On Mon, Sep 18, 2023 at 3:07=E2=80=AFPM Juzhe-Zhong = wrote: > > We have largely supportted VLS modes. Only move patterns of VLS modes are > different from VLS patterns. The rest of them are the same. > > We always extend the current VLA patterns with VLSmodes: > > VI --> V_VLSI > VF --> V_VLSF > > It makes no sense to have a separate file holding a very few VLS patterns > that can not be extended from the current VLA patterns. > > So remove autovec-vls.md > > gcc/ChangeLog: > > * config/riscv/vector.md (mov): New pattern. > (*mov_mem_to_mem): Ditto. > (*mov): Ditto. > (@mov_lra): Ditto. > (*mov_lra): Ditto. > (*mov_vls): Ditto. > (movmisalign): Ditto. > (@vec_duplicate): Ditto. > * config/riscv/autovec-vls.md: Removed. > > --- > gcc/config/riscv/autovec-vls.md | 196 -------------------------------- > gcc/config/riscv/vector.md | 172 +++++++++++++++++++++++++++- > 2 files changed, 170 insertions(+), 198 deletions(-) > delete mode 100644 gcc/config/riscv/autovec-vls.md > > diff --git a/gcc/config/riscv/autovec-vls.md b/gcc/config/riscv/autovec-v= ls.md > deleted file mode 100644 > index 3488f452e5d..00000000000 > --- a/gcc/config/riscv/autovec-vls.md > +++ /dev/null > @@ -1,196 +0,0 @@ > -;; Machine description for VLS of RVV auto-vectorization. > -;; Copyright (C) 2023 Free Software Foundation, Inc. > -;; Contributed by Juzhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies= Ltd. > - > -;; This file is part of GCC. > - > -;; GCC is free software; you can redistribute it and/or modify > -;; it under the terms of the GNU General Public License as published by > -;; the Free Software Foundation; either version 3, or (at your option) > -;; any later version. > - > -;; GCC is distributed in the hope that it will be useful, > -;; but WITHOUT ANY WARRANTY; without even the implied warranty of > -;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > -;; GNU General Public License for more details. > - > -;; You should have received a copy of the GNU General Public License > -;; along with GCC; see the file COPYING3. If not see > -;; . > - > -;; We define VLS modes as 'define_insn_and_split' with normal > -;; RTX_CODE operation, so we can gain benefits from Combine optimization= s. > - > -;; ----------------------------------------------------------------- > -;; ---- Moves Operations > -;; ----------------------------------------------------------------- > - > -(define_expand "mov" > - [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand") > - (match_operand:VLS_AVL_IMM 1 "general_operand"))] > - "TARGET_VECTOR" > -{ > - if (riscv_vector::legitimize_move (operands[0], operands[1])) > - DONE; > -}) > - > -(define_insn_and_split "*mov_mem_to_mem" > - [(set (match_operand:VLS_AVL_IMM 0 "memory_operand") > - (match_operand:VLS_AVL_IMM 1 "memory_operand"))] > - "TARGET_VECTOR && can_create_pseudo_p ()" > - "#" > - "&& 1" > - [(const_int 0)] > - { > - if (GET_MODE_BITSIZE (mode).to_constant () <=3D MAX_BITS_PER_W= ORD) > - { > - /* Opitmize the following case: > - > - typedef int8_t v2qi __attribute__ ((vector_size (2))); > - v2qi v =3D *(v2qi*)in; > - *(v2qi*)out =3D v; > - > - We prefer scalar load/store instead of vle.v/vse.v when > - the VLS modes size is smaller scalar mode. */ > - machine_mode mode; > - unsigned size =3D GET_MODE_BITSIZE (mode).to_constant (); > - if (FLOAT_MODE_P (mode)) > - mode =3D mode_for_size (size, MODE_FLOAT, 0).require (); > - else > - mode =3D mode_for_size (size, MODE_INT, 0).require (); > - emit_move_insn (gen_lowpart (mode, operands[0]), > - gen_lowpart (mode, operands[1])); > - } > - else > - { > - operands[1] =3D force_reg (mode, operands[1]); > - emit_move_insn (operands[0], operands[1]); > - } > - DONE; > - } > - [(set_attr "type" "vmov")] > -) > - > -(define_insn_and_split "*mov" > - [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand" "=3Dvr, m, vr"= ) > - (match_operand:VLS_AVL_IMM 1 "reg_or_mem_operand" " m,vr, vr"))] > - "TARGET_VECTOR > - && (register_operand (operands[0], mode) > - || register_operand (operands[1], mode))" > - "@ > - # > - # > - vmv%m1r.v\t%0,%1" > - "&& reload_completed > - && (!register_operand (operands[0], mode) > - || !register_operand (operands[1], mode))" > - [(const_int 0)] > - { > - bool ok_p =3D riscv_vector::legitimize_move (operands[0], operands[1= ]); > - gcc_assert (ok_p); > - DONE; > - } > - [(set_attr "type" "vmov")] > -) > - > -(define_expand "mov" > - [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand") > - (match_operand:VLS_AVL_REG 1 "general_operand"))] > - "TARGET_VECTOR" > -{ > - bool ok_p =3D riscv_vector::legitimize_move (operands[0], operands[1])= ; > - gcc_assert (ok_p); > - DONE; > -}) > - > -(define_expand "@mov_lra" > - [(parallel > - [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand") > - (match_operand:VLS_AVL_REG 1 "reg_or_mem_operand")) > - (clobber (match_scratch:P 2))])] > - "TARGET_VECTOR && (lra_in_progress || reload_completed)" > -{}) > - > -(define_insn_and_split "*mov_lra" > - [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand" "=3Dvr, m,vr") > - (match_operand:VLS_AVL_REG 1 "reg_or_mem_operand" " m,vr,vr")) > - (clobber (match_scratch:P 2 "=3D&r,&r,X"))] > - "TARGET_VECTOR && (lra_in_progress || reload_completed) > - && (register_operand (operands[0], mode) > - || register_operand (operands[1], mode))" > - "#" > - "&& reload_completed" > - [(const_int 0)] > -{ > - if (REG_P (operands[0]) && REG_P (operands[1])) > - emit_insn (gen_rtx_SET (operands[0], operands[1])); > - else > - { > - emit_move_insn (operands[2], gen_int_mode (GET_MODE_NUNITS (mode), > - Pmode)); > - unsigned insn_flags > - =3D GET_MODE_CLASS (mode) =3D=3D MODE_VECTOR_B= OOL > - ? riscv_vector::UNAR= Y_MASK_OP > - : riscv_vector::UNAR= Y_OP; > - riscv_vector::emit_nonvlmax_insn (code_for_pred_mov (mode), > - insn_flags, operands, operands[2]= ); > - } > - DONE; > -} > - [(set_attr "type" "vmov")] > -) > - > -(define_insn "*mov_vls" > - [(set (match_operand:VLS 0 "register_operand" "=3Dvr") > - (match_operand:VLS 1 "register_operand" " vr"))] > - "TARGET_VECTOR" > - "vmv%m1r.v\t%0,%1" > - [(set_attr "type" "vmov") > - (set_attr "mode" "")]) > - > -(define_insn "*mov_vls" > - [(set (match_operand:VLSB 0 "register_operand" "=3Dvr") > - (match_operand:VLSB 1 "register_operand" " vr"))] > - "TARGET_VECTOR" > - "vmv1r.v\t%0,%1" > - [(set_attr "type" "vmov") > - (set_attr "mode" "")]) > - > -(define_expand "movmisalign" > - [(set (match_operand:VLS 0 "nonimmediate_operand") > - (match_operand:VLS 1 "general_operand"))] > - "TARGET_VECTOR" > - { > - /* To support misalign data movement, we should use > - minimum element alignment load/store. */ > - unsigned int size =3D GET_MODE_SIZE (GET_MODE_INNER (mode)); > - poly_int64 nunits =3D GET_MODE_NUNITS (mode) * size; > - machine_mode mode =3D riscv_vector::get_vector_mode (QImode, nunits)= .require (); > - operands[0] =3D gen_lowpart (mode, operands[0]); > - operands[1] =3D gen_lowpart (mode, operands[1]); > - if (MEM_P (operands[0]) && !register_operand (operands[1], mode)) > - operands[1] =3D force_reg (mode, operands[1]); > - riscv_vector::emit_vlmax_insn (code_for_pred_mov (mode), riscv_vecto= r::UNARY_OP, operands); > - DONE; > - } > -) > - > -;; ----------------------------------------------------------------- > -;; ---- Duplicate Operations > -;; ----------------------------------------------------------------- > - > -(define_insn_and_split "@vec_duplicate" > - [(set (match_operand:VLS 0 "register_operand") > - (vec_duplicate:VLS > - (match_operand: 1 "reg_or_int_operand")))] > - "TARGET_VECTOR && can_create_pseudo_p ()" > - "#" > - "&& 1" > - [(const_int 0)] > - { > - riscv_vector::emit_vlmax_insn (code_for_pred_broadcast (mode), > - riscv_vector::UNARY_OP, operands); > - DONE; > - } > - [(set_attr "type" "vector")] > -) > diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md > index 939e992cad1..40512e8d864 100644 > --- a/gcc/config/riscv/vector.md > +++ b/gcc/config/riscv/vector.md > @@ -25,7 +25,6 @@ > ;; - Intrinsics (https://github.com/riscv/rvv-intrinsic-doc) > ;; - Auto-vectorization (autovec.md) > ;; - Optimization (autovec-opt.md) > -;; - VLS patterns (autovec-vls.md) > > (include "vector-iterators.md") > > @@ -1210,6 +1209,160 @@ > [(set_attr "type" "vmov,vlde,vste") > (set_attr "mode" "")]) > > +;; ----------------------------------------------------------------- > +;; ---- VLS Moves Operations > +;; ----------------------------------------------------------------- > + > +(define_expand "mov" > + [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand") > + (match_operand:VLS_AVL_IMM 1 "general_operand"))] > + "TARGET_VECTOR" > +{ > + if (riscv_vector::legitimize_move (operands[0], operands[1])) > + DONE; > +}) > + > +(define_insn_and_split "*mov_mem_to_mem" > + [(set (match_operand:VLS_AVL_IMM 0 "memory_operand") > + (match_operand:VLS_AVL_IMM 1 "memory_operand"))] > + "TARGET_VECTOR && can_create_pseudo_p ()" > + "#" > + "&& 1" > + [(const_int 0)] > + { > + if (GET_MODE_BITSIZE (mode).to_constant () <=3D MAX_BITS_PER_W= ORD) > + { > + /* Opitmize the following case: > + > + typedef int8_t v2qi __attribute__ ((vector_size (2))); > + v2qi v =3D *(v2qi*)in; > + *(v2qi*)out =3D v; > + > + We prefer scalar load/store instead of vle.v/vse.v when > + the VLS modes size is smaller scalar mode. */ > + machine_mode mode; > + unsigned size =3D GET_MODE_BITSIZE (mode).to_constant (); > + if (FLOAT_MODE_P (mode)) > + mode =3D mode_for_size (size, MODE_FLOAT, 0).require (); > + else > + mode =3D mode_for_size (size, MODE_INT, 0).require (); > + emit_move_insn (gen_lowpart (mode, operands[0]), > + gen_lowpart (mode, operands[1])); > + } > + else > + { > + operands[1] =3D force_reg (mode, operands[1]); > + emit_move_insn (operands[0], operands[1]); > + } > + DONE; > + } > + [(set_attr "type" "vmov")] > +) > + > +(define_insn_and_split "*mov" > + [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand" "=3Dvr, m, vr"= ) > + (match_operand:VLS_AVL_IMM 1 "reg_or_mem_operand" " m,vr, vr"))] > + "TARGET_VECTOR > + && (register_operand (operands[0], mode) > + || register_operand (operands[1], mode))" > + "@ > + # > + # > + vmv%m1r.v\t%0,%1" > + "&& reload_completed > + && (!register_operand (operands[0], mode) > + || !register_operand (operands[1], mode))" > + [(const_int 0)] > + { > + bool ok_p =3D riscv_vector::legitimize_move (operands[0], operands[1= ]); > + gcc_assert (ok_p); > + DONE; > + } > + [(set_attr "type" "vmov")] > +) > + > +(define_expand "mov" > + [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand") > + (match_operand:VLS_AVL_REG 1 "general_operand"))] > + "TARGET_VECTOR" > +{ > + bool ok_p =3D riscv_vector::legitimize_move (operands[0], operands[1])= ; > + gcc_assert (ok_p); > + DONE; > +}) > + > +(define_expand "@mov_lra" > + [(parallel > + [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand") > + (match_operand:VLS_AVL_REG 1 "reg_or_mem_operand")) > + (clobber (match_scratch:P 2))])] > + "TARGET_VECTOR && (lra_in_progress || reload_completed)" > +{}) > + > +(define_insn_and_split "*mov_lra" > + [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand" "=3Dvr, m,vr") > + (match_operand:VLS_AVL_REG 1 "reg_or_mem_operand" " m,vr,vr")) > + (clobber (match_scratch:P 2 "=3D&r,&r,X"))] > + "TARGET_VECTOR && (lra_in_progress || reload_completed) > + && (register_operand (operands[0], mode) > + || register_operand (operands[1], mode))" > + "#" > + "&& reload_completed" > + [(const_int 0)] > +{ > + if (REG_P (operands[0]) && REG_P (operands[1])) > + emit_insn (gen_rtx_SET (operands[0], operands[1])); > + else > + { > + emit_move_insn (operands[2], gen_int_mode (GET_MODE_NUNITS (mode), > + Pmode)); > + unsigned insn_flags > + =3D GET_MODE_CLASS (mode) =3D=3D MODE_VECTOR_B= OOL > + ? riscv_vector::UNAR= Y_MASK_OP > + : riscv_vector::UNAR= Y_OP; > + riscv_vector::emit_nonvlmax_insn (code_for_pred_mov (mode), > + insn_flags, operands, operands[2]= ); > + } > + DONE; > +} > + [(set_attr "type" "vmov")] > +) > + > +(define_insn "*mov_vls" > + [(set (match_operand:VLS 0 "register_operand" "=3Dvr") > + (match_operand:VLS 1 "register_operand" " vr"))] > + "TARGET_VECTOR" > + "vmv%m1r.v\t%0,%1" > + [(set_attr "type" "vmov") > + (set_attr "mode" "")]) > + > +(define_insn "*mov_vls" > + [(set (match_operand:VLSB 0 "register_operand" "=3Dvr") > + (match_operand:VLSB 1 "register_operand" " vr"))] > + "TARGET_VECTOR" > + "vmv1r.v\t%0,%1" > + [(set_attr "type" "vmov") > + (set_attr "mode" "")]) > + > +(define_expand "movmisalign" > + [(set (match_operand:VLS 0 "nonimmediate_operand") > + (match_operand:VLS 1 "general_operand"))] > + "TARGET_VECTOR" > + { > + /* To support misalign data movement, we should use > + minimum element alignment load/store. */ > + unsigned int size =3D GET_MODE_SIZE (GET_MODE_INNER (mode)); > + poly_int64 nunits =3D GET_MODE_NUNITS (mode) * size; > + machine_mode mode =3D riscv_vector::get_vector_mode (QImode, nunits)= .require (); > + operands[0] =3D gen_lowpart (mode, operands[0]); > + operands[1] =3D gen_lowpart (mode, operands[1]); > + if (MEM_P (operands[0]) && !register_operand (operands[1], mode)) > + operands[1] =3D force_reg (mode, operands[1]); > + riscv_vector::emit_vlmax_insn (code_for_pred_mov (mode), riscv_vecto= r::UNARY_OP, operands); > + DONE; > + } > +) > + > ;; ----------------------------------------------------------------- > ;; ---- Duplicate Operations > ;; ----------------------------------------------------------------- > @@ -1230,6 +1383,22 @@ > } > ) > > +(define_insn_and_split "@vec_duplicate" > + [(set (match_operand:VLS 0 "register_operand") > + (vec_duplicate:VLS > + (match_operand: 1 "reg_or_int_operand")))] > + "TARGET_VECTOR && can_create_pseudo_p ()" > + "#" > + "&& 1" > + [(const_int 0)] > + { > + riscv_vector::emit_vlmax_insn (code_for_pred_broadcast (mode), > + riscv_vector::UNARY_OP, operands); > + DONE; > + } > + [(set_attr "type" "vector")] > +) > + > ;; ----------------------------------------------------------------- > ;; ---- 6. Configuration-Setting Instructions > ;; ----------------------------------------------------------------- > @@ -8540,4 +8709,3 @@ > > (include "autovec.md") > (include "autovec-opt.md") > -(include "autovec-vls.md") > -- > 2.36.3 >