From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by sourceware.org (Postfix) with ESMTPS id DDE03385734E for ; Mon, 15 May 2023 13:44:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DDE03385734E Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-1aad6f2be8eso118056455ad.3 for ; Mon, 15 May 2023 06:44:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1684158281; x=1686750281; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=UJLPo+EL9FQ2Lo3vp8j+Imix+BpYXhouYmdiA/5F7is=; b=GN3zIs8RdVJPoHVjLv/uFpVsEoOwvjFVy9c1F9A9K3iKSegeJ/2AWyZzITmnviW8o1 L7UjjIfNgub2/fDXBEQfXe4tkOBdBZWDlKidLBFZjukyYXUeEnCFVVeR/fsR6VPhkZMJ pbxwIYkIJn3voRQacQP1y7R/0NM2Ook+nmyTms0cdfEhTw4qywEDoN7LvbTN3X8e8jKw X9mi7QWJtKb7zvtoeP1SWcsq7HU9D9Tlzt+t18iPMVroZWwZjyt/YlD1rwtWLyYK0JEY N2rd9DPpZJdD1FbaRdwzQn4n/QuOnQ0rY0ONugbxacp0SNmGe7D/a8GTx13WC+liEMn3 xZqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684158281; x=1686750281; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=UJLPo+EL9FQ2Lo3vp8j+Imix+BpYXhouYmdiA/5F7is=; b=SfIyIxkH1/5V4/vxBo/LZX3w1FoEAAuZOlSS00st8cmFscc40XI7VItxS1enXJuGov 0XiUcHw+gBJM0bXOOTwASS5Nro5m9uzyjIxlLxSZvOs/Ti90suQYySDNYs1nuEz+NLvP tJfHkjrQW8p5RLnPMPR8660A9S4JsAOVH8njLaYiCO+NOGSCBvUixz1iViAMG8KH17QW HxCSiKQOesPkQs2oRDvjxXeDIHdcUuehdN6TQop2U13nu472/56LEqDfQioJDHHTmXGQ RBdw0iqNxgZjThAlbjEeHoYhg4d/GtHPejQFwIMurcejD2XrxKAzqUjcO9md1IOJIAKJ AAaw== X-Gm-Message-State: AC+VfDzhNZfusJxrmP7uQA62UuQZZe5e2VsGhPWacVem7pkaDA6oZLPX 6b15EBJ7FBHoPEOh1CDhZ7qt560XFRgtZWprwOQVKg== X-Google-Smtp-Source: ACHHUZ4AVrhkR2/+mq8+dPDgLTzxlmNGuls+zYDrFfwvL9r1yOmsV3LTj8vpsAepcEIfKHB8C+E6rj/bddUPXmLVwbw= X-Received: by 2002:a17:903:d4:b0:1ad:be0c:267c with SMTP id x20-20020a17090300d400b001adbe0c267cmr15406915plc.57.1684158280743; Mon, 15 May 2023 06:44:40 -0700 (PDT) MIME-Version: 1.0 References: <20230515114932.244397-1-juzhe.zhong@rivai.ai> In-Reply-To: <20230515114932.244397-1-juzhe.zhong@rivai.ai> From: Kito Cheng Date: Mon, 15 May 2023 21:44:29 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Add rounding mode operand for floating point instructions To: juzhe.zhong@rivai.ai Cc: gcc-patches@gcc.gnu.org, jeffreyalaw@gmail.com, kito.cheng@gmail.com, palmer@dabbelt.com, palmer@rivosinc.com, rdapp.gcc@gmail.com Content-Type: multipart/alternative; boundary="00000000000011dd5d05fbbba8fb" X-Spam-Status: No, score=-8.5 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,HTML_MESSAGE,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --00000000000011dd5d05fbbba8fb Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable LGTM =E6=96=BC 2023=E5=B9=B45=E6=9C=8815=E6=97=A5 =E9=80= =B1=E4=B8=80=EF=BC=8C19:50=E5=AF=AB=E9=81=93=EF=BC=9A > From: Juzhe-Zhong > > This patch is adding rounding mode operand and FRM_REGNUM dependency > into floating-point instructions. > > The floating-point instructions we added FRM and rounding mode operand: > 1. vfadd/vfsub > 2. vfwadd/vfwsub > 3. vfmul > 4. vfdiv > 5. vfwmul > 6. vfwmacc/vfwnmacc/vfwmsac/vfwnmsac > 7. vfsqrt7/vfrec7 > 8. floating-point conversions. > 9. floating-point reductions. > > The floating-point instructions we did NOT add FRM and rounding mode > operand: > 1. vfsqrt/vfneg > 2. vfmin/vfmax > 3. comparisons > 4. vfclass > 5. vfsgnj/vfsgnjn/vfsgnjx > 6. vfmerge > 7. vfmv.v.f > > TODO: floating-point ternary: FRM and rounding mode operand should be > added but > they are not added in this patch since it will exceed the number of > operands can > be handled in optabs.cc. Will add it the next patch. > > gcc/ChangeLog: > > * config/riscv/riscv-protos.h (enum frm_field_enum): New enum. > * config/riscv/riscv-vector-builtins.cc > (function_expander::use_widen_ternop_insn): Add default rounding mode. > * config/riscv/riscv.cc (riscv_hard_regno_nregs): Add FRM_REGNUM. > (riscv_hard_regno_mode_ok): Ditto. > (riscv_conditional_register_usage): Ditto. > * config/riscv/riscv.h (DWARF_FRAME_REGNUM): Ditto. > (FRM_REG_P): Ditto. > (RISCV_DWARF_FRM): Ditto. > * config/riscv/riscv.md: Ditto. > * config/riscv/vector-iterators.md: split smax/smin and plus/mult > since smax/smin doesn't need FRM. > * config/riscv/vector.md (@pred__scalar): Splitted > pattern. > (@pred_): Ditto. > > --- > gcc/config/riscv/riscv-protos.h | 10 ++ > gcc/config/riscv/riscv-vector-builtins.cc | 7 + > gcc/config/riscv/riscv.cc | 7 +- > gcc/config/riscv/riscv.h | 7 +- > gcc/config/riscv/riscv.md | 1 + > gcc/config/riscv/vector-iterators.md | 6 +- > gcc/config/riscv/vector.md | 171 ++++++++++++++++++---- > 7 files changed, 171 insertions(+), 38 deletions(-) > > diff --git a/gcc/config/riscv/riscv-protos.h > b/gcc/config/riscv/riscv-protos.h > index 835bb802fc6..12634d0ac1a 100644 > --- a/gcc/config/riscv/riscv-protos.h > +++ b/gcc/config/riscv/riscv-protos.h > @@ -231,6 +231,16 @@ enum vxrm_field_enum > VXRM_RDN, > VXRM_ROD > }; > +/* Rounding mode bitfield for floating point FRM. */ > +enum frm_field_enum > +{ > + FRM_RNE =3D 0b000, > + FRM_RTZ =3D 0b001, > + FRM_RDN =3D 0b010, > + FRM_RUP =3D 0b011, > + FRM_RMM =3D 0b100, > + DYN =3D 0b111 > +}; > } > > /* We classify builtin types into two classes: > diff --git a/gcc/config/riscv/riscv-vector-builtins.cc > b/gcc/config/riscv/riscv-vector-builtins.cc > index 1de075fb90d..f10f38f6425 100644 > --- a/gcc/config/riscv/riscv-vector-builtins.cc > +++ b/gcc/config/riscv/riscv-vector-builtins.cc > @@ -3482,6 +3482,13 @@ function_expander::use_widen_ternop_insn (insn_code > icode) > add_input_operand (Pmode, get_tail_policy_for_pred (pred)); > add_input_operand (Pmode, get_mask_policy_for_pred (pred)); > add_input_operand (Pmode, get_avl_type_rtx (avl_type::NONVLMAX)); > + > + /* TODO: Currently, we don't support intrinsic that is modeling > rounding mode. > + We add default rounding mode for the intrinsics that didn't model > rounding > + mode yet. */ > + if (opno !=3D insn_data[icode].n_generator_args) > + add_input_operand (Pmode, const0_rtx); > + > return generate_insn (icode); > } > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index b52e613c629..de5b87b1a87 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -6082,7 +6082,8 @@ riscv_hard_regno_nregs (unsigned int regno, > machine_mode mode) > > /* mode for VL or VTYPE are just a marker, not holding value, > so it always consume one register. */ > - if (VTYPE_REG_P (regno) || VL_REG_P (regno) || VXRM_REG_P (regno)) > + if (VTYPE_REG_P (regno) || VL_REG_P (regno) || VXRM_REG_P (regno) > + || FRM_REG_P (regno)) > return 1; > > /* Assume every valid non-vector mode fits in one vector register. */ > @@ -6150,7 +6151,8 @@ riscv_hard_regno_mode_ok (unsigned int regno, > machine_mode mode) > if (lmul !=3D 1) > return ((regno % lmul) =3D=3D 0); > } > - else if (VTYPE_REG_P (regno) || VL_REG_P (regno) || VXRM_REG_P (regno)) > + else if (VTYPE_REG_P (regno) || VL_REG_P (regno) || VXRM_REG_P (regno) > + || FRM_REG_P (regno)) > return true; > else > return false; > @@ -6587,6 +6589,7 @@ riscv_conditional_register_usage (void) > fixed_regs[VTYPE_REGNUM] =3D call_used_regs[VTYPE_REGNUM] =3D 1; > fixed_regs[VL_REGNUM] =3D call_used_regs[VL_REGNUM] =3D 1; > fixed_regs[VXRM_REGNUM] =3D call_used_regs[VXRM_REGNUM] =3D 1; > + fixed_regs[FRM_REGNUM] =3D call_used_regs[FRM_REGNUM] =3D 1; > } > } > > diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h > index f74b70de562..f55bd6112a8 100644 > --- a/gcc/config/riscv/riscv.h > +++ b/gcc/config/riscv/riscv.h > @@ -121,8 +121,9 @@ ASM_MISA_SPEC > > /* The mapping from gcc register number to DWARF 2 CFA column number. */ > #define DWARF_FRAME_REGNUM(REGNO) > \ > - (VXRM_REG_P (REGNO) ? RISCV_DWARF_VXRM > \ > - : VL_REG_P (REGNO) ? RISCV_DWARF_VL > \ > + (FRM_REG_P (REGNO) ? RISCV_DWARF_FRM > \ > + : VXRM_REG_P (REGNO) ? RISCV_DWARF_VXRM > \ > + : VL_REG_P (REGNO) ? RISCV_DWARF_VL > \ > : VTYPE_REG_P (REGNO) > \ > ? RISCV_DWARF_VTYPE > \ > : (GP_REG_P (REGNO) || FP_REG_P (REGNO) || V_REG_P (REGNO) > \ > @@ -374,6 +375,7 @@ ASM_MISA_SPEC > #define VL_REG_P(REGNO) ((REGNO) =3D=3D VL_REGNUM) > #define VTYPE_REG_P(REGNO) ((REGNO) =3D=3D VTYPE_REGNUM) > #define VXRM_REG_P(REGNO) ((REGNO) =3D=3D VXRM_REGNUM) > +#define FRM_REG_P(REGNO) ((REGNO) =3D=3D FRM_REGNUM) > > /* True when REGNO is in SIBCALL_REGS set. */ > #define SIBCALL_REG_P(REGNO) \ > @@ -392,6 +394,7 @@ ASM_MISA_SPEC > #define FRAME_POINTER_REGNUM 65 > > /* Define Dwarf for RVV. */ > +#define RISCV_DWARF_FRM (4096 + 0x003) > #define RISCV_DWARF_VXRM (4096 + 0x00a) > #define RISCV_DWARF_VL (4096 + 0xc20) > #define RISCV_DWARF_VTYPE (4096 + 0xc21) > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md > index c5cf3af9868..91808d6bd2a 100644 > --- a/gcc/config/riscv/riscv.md > +++ b/gcc/config/riscv/riscv.md > @@ -136,6 +136,7 @@ > (VL_REGNUM 66) > (VTYPE_REGNUM 67) > (VXRM_REGNUM 68) > + (FRM_REGNUM 69) > ]) > > (include "predicates.md") > diff --git a/gcc/config/riscv/vector-iterators.md > b/gcc/config/riscv/vector-iterators.md > index a282861335d..ac87ac3d114 100644 > --- a/gcc/config/riscv/vector-iterators.md > +++ b/gcc/config/riscv/vector-iterators.md > @@ -1436,8 +1436,10 @@ > > (define_code_iterator and_ior [and ior]) > > -(define_code_iterator any_float_binop [plus mult smax smin minus div]) > -(define_code_iterator commutative_float_binop [plus mult smax smin]) > +(define_code_iterator any_float_binop [plus mult minus div]) > +(define_code_iterator any_float_binop_nofrm [smax smin]) > +(define_code_iterator commutative_float_binop [plus mult]) > +(define_code_iterator commutative_float_binop_nofrm [smax smin]) > (define_code_iterator non_commutative_float_binop [minus div]) > (define_code_iterator any_float_unop [neg abs sqrt]) > > diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md > index e0aeeea57a4..0929d19d5ec 100644 > --- a/gcc/config/riscv/vector.md > +++ b/gcc/config/riscv/vector.md > @@ -5722,8 +5722,10 @@ > (match_operand 6 "const_int_operand" " i, i, i, i= ") > (match_operand 7 "const_int_operand" " i, i, i, i= ") > (match_operand 8 "const_int_operand" " i, i, i, i= ") > + (match_operand 9 "const_int_operand" " i, i, i, i= ") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > (any_float_binop:VF > (match_operand:VF 3 "register_operand" " vr, vr, vr, vr= ") > (match_operand:VF 4 "register_operand" " vr, vr, vr, > vr")) > @@ -5733,7 +5735,7 @@ > [(set_attr "type" "") > (set_attr "mode" "")]) > > -(define_insn "@pred__scalar" > +(define_insn "@pred_" > [(set (match_operand:VF 0 "register_operand" "=3Dvd, vd, vr, > vr") > (if_then_else:VF > (unspec: > @@ -5744,6 +5746,28 @@ > (match_operand 8 "const_int_operand" " i, i, i, i= ") > (reg:SI VL_REGNUM) > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (any_float_binop_nofrm:VF > + (match_operand:VF 3 "register_operand" " vr, vr, vr, vr= ") > + (match_operand:VF 4 "register_operand" " vr, vr, vr, > vr")) > + (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, > 0")))] > + "TARGET_VECTOR" > + "vf.vv\t%0,%3,%4%p1" > + [(set_attr "type" "") > + (set_attr "mode" "")]) > + > +(define_insn "@pred__scalar" > + [(set (match_operand:VF 0 "register_operand" "=3Dvd, vd, vr, > vr") > + (if_then_else:VF > + (unspec: > + [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1= ") > + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK= ") > + (match_operand 6 "const_int_operand" " i, i, i, i= ") > + (match_operand 7 "const_int_operand" " i, i, i, i= ") > + (match_operand 8 "const_int_operand" " i, i, i, i= ") > + (match_operand 9 "const_int_operand" " i, i, i, i= ") > + (reg:SI VL_REGNUM) > + (reg:SI VTYPE_REGNUM) > + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > (commutative_float_binop:VF > (vec_duplicate:VF > (match_operand: 4 "register_operand" " f, f, f, > f")) > @@ -5765,6 +5789,29 @@ > (match_operand 8 "const_int_operand" " i, i, i, i= ") > (reg:SI VL_REGNUM) > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (commutative_float_binop_nofrm:VF > + (vec_duplicate:VF > + (match_operand: 4 "register_operand" " f, f, f, > f")) > + (match_operand:VF 3 "register_operand" " vr, vr, vr, > vr")) > + (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, > 0")))] > + "TARGET_VECTOR" > + "vf.vf\t%0,%3,%4%p1" > + [(set_attr "type" "") > + (set_attr "mode" "")]) > + > +(define_insn "@pred__scalar" > + [(set (match_operand:VF 0 "register_operand" "=3Dvd, vd, vr, > vr") > + (if_then_else:VF > + (unspec: > + [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1= ") > + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK= ") > + (match_operand 6 "const_int_operand" " i, i, i, i= ") > + (match_operand 7 "const_int_operand" " i, i, i, i= ") > + (match_operand 8 "const_int_operand" " i, i, i, i= ") > + (match_operand 9 "const_int_operand" " i, i, i, i= ") > + (reg:SI VL_REGNUM) > + (reg:SI VTYPE_REGNUM) > + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > (non_commutative_float_binop:VF > (match_operand:VF 3 "register_operand" " vr, vr, vr, vr= ") > (vec_duplicate:VF > @@ -5784,8 +5831,10 @@ > (match_operand 6 "const_int_operand" " i, i, i, i= ") > (match_operand 7 "const_int_operand" " i, i, i, i= ") > (match_operand 8 "const_int_operand" " i, i, i, i= ") > + (match_operand 9 "const_int_operand" " i, i, i, i= ") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > (non_commutative_float_binop:VF > (vec_duplicate:VF > (match_operand: 4 "register_operand" " f, f, f, > f")) > @@ -6379,8 +6428,10 @@ > (match_operand 5 "const_int_operand" " i, i, i, i= ") > (match_operand 6 "const_int_operand" " i, i, i, i= ") > (match_operand 7 "const_int_operand" " i, i, i, i= ") > + (match_operand 8 "const_int_operand" " i, i, i, i= ") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > (unspec:VF > [(match_operand:VF 3 "register_operand" " vr, vr, vr, > vr")] VFMISC) > (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, > 0")))] > @@ -6426,8 +6477,10 @@ > (match_operand 6 "const_int_operand" " > i, i") > (match_operand 7 "const_int_operand" " > i, i") > (match_operand 8 "const_int_operand" " > i, i") > + (match_operand 9 "const_int_operand" " > i, i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > (any_widen_binop:VWEXTF > (float_extend:VWEXTF > (match_operand: 3 "register_operand" " > vr, vr")) > @@ -6448,8 +6501,10 @@ > (match_operand 6 "const_int_operand" " > i, i") > (match_operand 7 "const_int_operand" " > i, i") > (match_operand 8 "const_int_operand" " > i, i") > + (match_operand 9 "const_int_operand" " > i, i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > (any_widen_binop:VWEXTF > (float_extend:VWEXTF > (match_operand: 3 "register_operand" " > vr, vr")) > @@ -6471,8 +6526,10 @@ > (match_operand 6 "const_int_operand" " > i, i") > (match_operand 7 "const_int_operand" " > i, i") > (match_operand 8 "const_int_operand" " > i, i") > + (match_operand 9 "const_int_operand" " > i, i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > (plus_minus:VWEXTF > (match_operand:VWEXTF 3 "register_operand" " > vr, vr") > (float_extend:VWEXTF > @@ -6492,8 +6549,10 @@ > (match_operand 6 "const_int_operand" " > i, i") > (match_operand 7 "const_int_operand" " > i, i") > (match_operand 8 "const_int_operand" " > i, i") > + (match_operand 9 "const_int_operand" " > i, i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > (plus_minus:VWEXTF > (match_operand:VWEXTF 3 "register_operand" " > vr, vr") > (float_extend:VWEXTF > @@ -6521,8 +6580,10 @@ > (match_operand 6 "const_int_operand" " > i") > (match_operand 7 "const_int_operand" " > i") > (match_operand 8 "const_int_operand" " > i") > + (match_operand 9 "const_int_operand" " > i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > (plus_minus:VWEXTF > (mult:VWEXTF > (float_extend:VWEXTF > @@ -6545,8 +6606,10 @@ > (match_operand 6 "const_int_operand" " > i") > (match_operand 7 "const_int_operand" " > i") > (match_operand 8 "const_int_operand" " > i") > + (match_operand 9 "const_int_operand" " > i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > (plus_minus:VWEXTF > (mult:VWEXTF > (float_extend:VWEXTF > @@ -6570,8 +6633,10 @@ > (match_operand 6 "const_int_operand" " > i") > (match_operand 7 "const_int_operand" " > i") > (match_operand 8 "const_int_operand" " > i") > + (match_operand 9 "const_int_operand" " > i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > (plus_minus:VWEXTF > (neg:VWEXTF > (mult:VWEXTF > @@ -6595,8 +6660,10 @@ > (match_operand 6 "const_int_operand" " > i") > (match_operand 7 "const_int_operand" " > i") > (match_operand 8 "const_int_operand" " > i") > + (match_operand 9 "const_int_operand" " > i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > (plus_minus:VWEXTF > (neg:VWEXTF > (mult:VWEXTF > @@ -6910,8 +6977,10 @@ > (match_operand 5 "const_int_operand" " i, i, > i, i") > (match_operand 6 "const_int_operand" " i, i, > i, i") > (match_operand 7 "const_int_operand" " i, i, > i, i") > + (match_operand 8 "const_int_operand" " i, i, > i, i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > (unspec: > [(match_operand:VF 3 "register_operand" " vr, vr, vr, > vr")] VFCVTS) > (match_operand: 2 "vector_merge_operand" " vu, 0, > vu, 0")))] > @@ -6929,8 +6998,10 @@ > (match_operand 5 "const_int_operand" " i, i, > i, i") > (match_operand 6 "const_int_operand" " i, i, > i, i") > (match_operand 7 "const_int_operand" " i, i, > i, i") > + (match_operand 8 "const_int_operand" " i, i, > i, i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > (any_fix: > (match_operand:VF 3 "register_operand" " vr, vr, vr, > vr")) > (match_operand: 2 "vector_merge_operand" " vu, 0, > vu, 0")))] > @@ -6948,8 +7019,10 @@ > (match_operand 5 "const_int_operand" " i, i, i, > i") > (match_operand 6 "const_int_operand" " i, i, i, > i") > (match_operand 7 "const_int_operand" " i, i, i, > i") > + (match_operand 8 "const_int_operand" " i, i, i, > i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > (any_float:VF > (match_operand: 3 "register_operand" " vr, vr, vr, > vr")) > (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, > 0")))] > @@ -6974,8 +7047,10 @@ > (match_operand 5 "const_int_operand" " i, > i") > (match_operand 6 "const_int_operand" " i, > i") > (match_operand 7 "const_int_operand" " i, > i") > + (match_operand 8 "const_int_operand" " i, > i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > (unspec:VWCONVERTI > [(match_operand: 3 "register_operand" " vr, > vr")] VFCVTS) > (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, > 0")))] > @@ -6993,8 +7068,10 @@ > (match_operand 5 "const_int_operand" " i, i= ") > (match_operand 6 "const_int_operand" " i, i= ") > (match_operand 7 "const_int_operand" " i, i= ") > + (match_operand 8 "const_int_operand" " i, i= ") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > (any_fix:VWCONVERTI > (match_operand: 3 "register_operand" " vr, > vr")) > (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, > 0")))] > @@ -7012,8 +7089,10 @@ > (match_operand 5 "const_int_operand" " i, i= ") > (match_operand 6 "const_int_operand" " i, i= ") > (match_operand 7 "const_int_operand" " i, i= ") > + (match_operand 8 "const_int_operand" " i, i= ") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > (any_float:VF > (match_operand: 3 "register_operand" " vr, > vr")) > (match_operand:VF 2 "vector_merge_operand" " vu, > 0")))] > @@ -7031,8 +7110,10 @@ > (match_operand 5 "const_int_operand" " i, > i") > (match_operand 6 "const_int_operand" " i, > i") > (match_operand 7 "const_int_operand" " i, > i") > + (match_operand 8 "const_int_operand" " i, > i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > (float_extend:VWEXTF > (match_operand: 3 "register_operand" " vr, > vr")) > (match_operand:VWEXTF 2 "vector_merge_operand" " vu, > 0")))] > @@ -7057,8 +7138,10 @@ > (match_operand 5 "const_int_operand" " i, i, > i, i, i, i") > (match_operand 6 "const_int_operand" " i, i, > i, i, i, i") > (match_operand 7 "const_int_operand" " i, i, > i, i, i, i") > + (match_operand 8 "const_int_operand" " i, i, > i, i, i, i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > (unspec: > [(match_operand:VF 3 "register_operand" " 0, 0, > 0, 0, vr, vr")] VFCVTS) > (match_operand: 2 "vector_merge_operand" " vu, 0, > vu, 0, vu, 0")))] > @@ -7076,8 +7159,10 @@ > (match_operand 5 "const_int_operand" " i, i, > i, i, i, i") > (match_operand 6 "const_int_operand" " i, i, > i, i, i, i") > (match_operand 7 "const_int_operand" " i, i, > i, i, i, i") > + (match_operand 8 "const_int_operand" " i, i, > i, i, i, i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > (any_fix: > (match_operand:VF 3 "register_operand" " 0, 0, > 0, 0, vr, vr")) > (match_operand: 2 "vector_merge_operand" " vu, 0, > vu, 0, vu, 0")))] > @@ -7095,8 +7180,10 @@ > (match_operand 5 "const_int_operand" " i, i, > i, i, i, i") > (match_operand 6 "const_int_operand" " i, i, > i, i, i, i") > (match_operand 7 "const_int_operand" " i, i, > i, i, i, i") > + (match_operand 8 "const_int_operand" " i, i, > i, i, i, i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > (any_float: > (match_operand:VWCONVERTI 3 "register_operand" " 0, 0, > 0, 0, vr, vr")) > (match_operand: 2 "vector_merge_operand" " vu, 0, > vu, 0, vu, 0")))] > @@ -7114,8 +7201,10 @@ > (match_operand 5 "const_int_operand" " i, > i, i, i, i, i") > (match_operand 6 "const_int_operand" " i, > i, i, i, i, i") > (match_operand 7 "const_int_operand" " i, > i, i, i, i, i") > + (match_operand 8 "const_int_operand" " i, > i, i, i, i, i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > (float_truncate: > (match_operand:VWEXTF 3 "register_operand" " 0, > 0, 0, 0, vr, vr")) > (match_operand: 2 "vector_merge_operand" " vu, > 0, vu, 0, vu, 0")))] > @@ -7133,8 +7222,10 @@ > (match_operand 5 "const_int_operand" " i, > i, i, i, i, i") > (match_operand 6 "const_int_operand" " i, > i, i, i, i, i") > (match_operand 7 "const_int_operand" " i, > i, i, i, i, i") > + (match_operand 8 "const_int_operand" " i, > i, i, i, i, i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > (unspec: > [(float_truncate: > (match_operand:VWEXTF 3 "register_operand" " 0, > 0, 0, 0, vr, vr"))] UNSPEC_ROD) > @@ -7289,8 +7380,10 @@ > (match_operand 5 "vector_length_operand" " rK, > rK") > (match_operand 6 "const_int_operand" " i, > i") > (match_operand 7 "const_int_operand" " i, > i") > + (match_operand 8 "const_int_operand" " i, > i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > (any_freduc:VF > (vec_duplicate:VF > (vec_select: > @@ -7311,8 +7404,10 @@ > (match_operand 5 "vector_length_operand" " > rK, rK") > (match_operand 6 "const_int_operand" " > i, i") > (match_operand 7 "const_int_operand" " > i, i") > + (match_operand 8 "const_int_operand" " > i, i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > (any_freduc:VF_ZVE64 > (vec_duplicate:VF_ZVE64 > (vec_select: > @@ -7333,8 +7428,10 @@ > (match_operand 5 "vector_length_operand" " rK, > rK, rK, rK") > (match_operand 6 "const_int_operand" " i, > i, i, i") > (match_operand 7 "const_int_operand" " i, > i, i, i") > + (match_operand 8 "const_int_operand" " i, > i, i, i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > (any_freduc:VF_ZVE32 > (vec_duplicate:VF_ZVE32 > (vec_select: > @@ -7356,8 +7453,10 @@ > (match_operand 5 "vector_length_operand" " rK, > rK") > (match_operand 6 "const_int_operand" " i, > i") > (match_operand 7 "const_int_operand" " i, > i") > + (match_operand 8 "const_int_operand" " i, > i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > (plus:VF > (vec_duplicate:VF > (vec_select: > @@ -7379,8 +7478,10 @@ > (match_operand 5 "vector_length_operand" " > rK, rK") > (match_operand 6 "const_int_operand" " > i, i") > (match_operand 7 "const_int_operand" " > i, i") > + (match_operand 8 "const_int_operand" " > i, i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > (plus:VF_ZVE64 > (vec_duplicate:VF_ZVE64 > (vec_select: > @@ -7402,8 +7503,10 @@ > (match_operand 5 "vector_length_operand" " > rK, rK, rK, rK") > (match_operand 6 "const_int_operand" " > i, i, i, i") > (match_operand 7 "const_int_operand" " > i, i, i, i") > + (match_operand 8 "const_int_operand" " > i, i, i, i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > (plus:VF_ZVE32 > (vec_duplicate:VF_ZVE32 > (vec_select: > @@ -7425,8 +7528,10 @@ > (match_operand 5 "vector_length_operand" " rK, > rK") > (match_operand 6 "const_int_operand" " i, > i") > (match_operand 7 "const_int_operand" " i, > i") > + (match_operand 8 "const_int_operand" " i, > i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > (match_operand:VWF 3 "register_operand" " vr, > vr") > (match_operand: 4 "register_operand" " vr, > vr") > (match_operand: 2 "vector_merge_operand" " vu, > 0")] UNSPEC_WREDUC_SUM)] ORDER))] > @@ -7444,8 +7549,10 @@ > (match_operand 5 "vector_length_operand" " rK, > rK") > (match_operand 6 "const_int_operand" " i, > i") > (match_operand 7 "const_int_operand" " i, > i") > + (match_operand 8 "const_int_operand" " i, > i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM) > + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > (match_operand:VWF_ZVE64 3 "register_operand" " > vr, vr") > (match_operand: 4 "register_operand" " > vr, vr") > (match_operand: 2 "vector_merge_operand" " > vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))] > -- > 2.36.1 > > --00000000000011dd5d05fbbba8fb--