From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by sourceware.org (Postfix) with ESMTPS id 67AA83858C60 for ; Fri, 28 Apr 2023 06:35:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 67AA83858C60 Authentication-Results: sourceware.org; dmarc=pass (p=quarantine dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-lf1-x134.google.com with SMTP id 2adb3069b0e04-4f00d41df22so8102130e87.1 for ; Thu, 27 Apr 2023 23:35:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1682663722; x=1685255722; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=qpM9IcbOzL6jUQuDSSA/Ain3KcS5FaTkR2U9Wx3BhGU=; b=hxsLI9u+NO7Vs4h310ZxTTIyi2m7S4pPqZ+MSDUqQWHTXJDBUM1LN9g+etaqIadwzD 1DB7dT0W1rS9W63kYuRWMLMOfgAA8UA1jciHudv6Bs1uSnMsMOzMi1ySFGi5yUhmPhau P0EZ9+cZo88h0jX/UJzN+gL2fTLKQYIZft3UutUElHd6cOCLGPqPmGHv+x56IiEZBqDB OH7rpODNPY7If45BTi6IrOncXNtUgjwufAn0Vq7+D/3xh+2y7e6NmmKmAuMVm7BhauvC bSXG8HaE8WVv4TEeaUVpZthbHGqp3JiAD6J+EkmV6gRcmgfwFLJMbayI+sYW7cQqBqXb Ke9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682663722; x=1685255722; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qpM9IcbOzL6jUQuDSSA/Ain3KcS5FaTkR2U9Wx3BhGU=; b=UxZYiB/YAYDPZbDxbqySRusA1Sg4wFnr/uwfupA0Bq2K8m/4eMEcrbzqbMimdaDopW 1tkVqieYae7Enekts/9/SqjjFjIUklVfQshuzBSwu5J/HfOtZMjj12MVb8MS5lnWT05+ 3zOZiaseMybOuPlyOZc3KwTcwJP1YkmvGLzgK6VC9LFeBb4SeuoHfAqexqbeOVhBz7Q0 gcQwflztacakcRfgTylncXXW7R0gXO3HpxEqAYez6DvpDqeKsW0uv9YNQKvqS2R0DSau YA4W5PSKORAfQarT92HWF0YW1nEFP4l0TpRpFfWD3WVejmtPWBU7sj+sWocFPybYlrLj zjfQ== X-Gm-Message-State: AC+VfDwQLoRjReVziLAIGLjz42GhkyHuRVIUhhUr/JCx/pUcI519F9qc +H2yDorR3LMpG8NqM3+ogZzNxeoeutZnpyXUL37thw== X-Google-Smtp-Source: ACHHUZ5bxXxAAX/k+Q6HcIWgMtcfbXgXhnyJohmjzul80FpPgjzylGbrog8hbLFQSECSa68fhUWLyBbZxmoJjRIPvcw= X-Received: by 2002:a05:6512:a84:b0:4ef:840a:ba71 with SMTP id m4-20020a0565120a8400b004ef840aba71mr2479663lfu.12.1682663721706; Thu, 27 Apr 2023 23:35:21 -0700 (PDT) MIME-Version: 1.0 References: <20230427143005.1781966-1-pan2.li@intel.com> In-Reply-To: From: Kito Cheng Date: Fri, 28 Apr 2023 14:35:10 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to VMCLR To: "Li, Pan2" Cc: "gcc-patches@gcc.gnu.org" , "juzhe.zhong@rivai.ai" , "Wang, Yanzhang" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-3.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: > The defined predicate of vector_move_operand composes of (non-imm || (con= st vector && (reload_completed ? constraint_vi (op) : constraint_wc0(op))). I may not quit understand why we group them together and named as vector_mo= ve. I forgot the detail reason about that, but vaguely remember that is for optimization, maybe need Ju-Zhe back and tell us the reason :P On Fri, Apr 28, 2023 at 10:06=E2=80=AFAM Li, Pan2 wrote= : > > Thanks Kito for the better approach. It works well with the prepared test= cases but I may have one question about the semantics of the vector_move_o= perand. > > The defined predicate of vector_move_operand composes of (non-imm || (con= st vector && (reload_completed ? constraint_vi (op) : constraint_wc0(op))). > I may not quit understand why we group them together and named as vector_= move. > > Another difference is that it will act on combine pass which is more gene= ric than the PATCH v1 (which acts on split2 pass). > > Pan > > -----Original Message----- > From: Kito Cheng > Sent: Thursday, April 27, 2023 11:00 PM > To: Li, Pan2 > Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; Wang, Yanzhang > Subject: Re: [PATCH] RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to V= MCLR > > > Could you try something like this? that should be more generic: > > > > (define_split > > [(set (match_operand:VB 0 "register_operand") > > (if_then_else:VB > > (unspec:VB > > [(match_operand:VB 1 "vector_all_trues_mask_operand") > > (match_operand 4 "vector_length_operand") > > (match_operand 5 "const_int_operand") > > (match_operand 6 "const_int_operand") > > (reg:SI VL_REGNUM) > > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > > (match_operand:VB 3 "vector_move_operand") > > (match_operand:VB 2 "vector_undef_operand")))] > > "TARGET_VECTOR && reload_completed" > > Remove the reload_completed should work well, but you might need more tes= t, I didn't run full test on this change :P > > > [(const_int 0)] > > { > > emit_insn (gen_pred_mov (mode, operands[0], CONST1_RTX (= mode), > > RVV_VUNDEF (mode), CONST0_RTX (= mode), > > operands[4], operands[5])); > > DONE; > > } > > )