From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pg1-x534.google.com (mail-pg1-x534.google.com [IPv6:2607:f8b0:4864:20::534]) by sourceware.org (Postfix) with ESMTPS id 9A1ED387089F for ; Thu, 11 May 2023 14:15:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 9A1ED387089F Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-pg1-x534.google.com with SMTP id 41be03b00d2f7-53063897412so1559975a12.0 for ; Thu, 11 May 2023 07:15:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1683814521; x=1686406521; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=mo73/RKNBaQLuBh1TNbc6+u2f59FZb4NA5k7Fhl2Za0=; b=G0djDktXl5V87tQR/GQoOj4aHb5hg2kSCCwG/q7SuVorLhUMlxIgiWDZTI/XxkEXEj xXB9CeIplLSqJCtAybLTibd7CLbCEjEEahPD7m0U3qzWosFhH1Uf6uxX5bhBcKMXFd6Y avtXf8KC2YYfOHk37wWR0d75t+oeRXI8mjLa7T1GKP/NnV42ZaYr90aYIqYMriLldquo 0sFQw6aYODB/5DF//uWpSpS80TIZYJEi7GcCSNvcpmBaOdsvNqj0jZDVksa+979qmHnr 1XxBYkyEAn/5ybq3P4zRXfbMxYgq4XXe4rRxtq5cyXLbj3/taxAkuirhkoJfqspFbAdV K0Gg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683814521; x=1686406521; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mo73/RKNBaQLuBh1TNbc6+u2f59FZb4NA5k7Fhl2Za0=; b=dww167anzXqSohwrLgNjbziOS3pj+4ofIbqpKpcqoGKM/vuo8BXvvgAKvpELA3Mk3N xgOAQhnG9dw6Gf+e5NtJq/uJ9uGKUcg9tn1thMe4Hk5GsmTFOH7vLol/6Y3rUR94wsl0 y0rmLazIFt8Rm8cpF1hJRTvSUwC4IIpfHXKELx61MBqW+StQ/V26g7DFn3A3t6nzd9Ch 5RSOGnZ9EnXkHcukdeYLwXs3DwVAktOlfnp9FZEifdZvR7sJrpmyj11anRKroSiIH/kZ Fzqy0zrd/+0/e52NO9FS/RSiNWt1rCH/jUUiqnCXZTB82GXz1Z/BhGznOyStcAZB9/n8 p62Q== X-Gm-Message-State: AC+VfDxvhOd0bM/JvJ642YD7vYAqCRWAE0qa0tTQW78jDhPHfxpkzC+f l43txFCx1RB/XBji47PmFeK6gdVIw7jyV7ymsPFEXg== X-Google-Smtp-Source: ACHHUZ4jMOIyWTkeaHXehbCnUKzHp+Qml+Y5wum8vd53+FgnM2gE+tjAc+C/H3W1Xx9c8vGyg3fJXcvxj90fgGUZ4nU= X-Received: by 2002:a17:902:b18a:b0:1a2:98b1:1ee3 with SMTP id s10-20020a170902b18a00b001a298b11ee3mr20723072plr.12.1683814521233; Thu, 11 May 2023 07:15:21 -0700 (PDT) MIME-Version: 1.0 References: <46ca12b2-8ac6-030e-92dc-6b71ab2d4ee8@gmail.com> <4B555E0D49C3178B+2023050413074589268520@rivai.ai> <6B74F0215DD1EAD6+2023050708091558978410@rivai.ai> <3bd0d367-8ea4-3446-abe6-a7c7a5065248@gmail.com> In-Reply-To: <3bd0d367-8ea4-3446-abe6-a7c7a5065248@gmail.com> From: Kito Cheng Date: Thu, 11 May 2023 22:15:10 +0800 Message-ID: Subject: Re: [PATCH v2] RISC-V: Allow vector constants in riscv_const_insns. To: Robin Dapp Cc: =?UTF-8?B?6ZKf5bGF5ZOy?= , Jeff Law , gcc-patches , "kito.cheng" , palmer , Michael Collison Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: LGTM, thanks :) On Thu, May 11, 2023 at 8:47=E2=80=AFPM Robin Dapp wr= ote: > > > OK, you can go ahead commit patch. I am gonna send another patch to > > fix this. > I agree that we should handle more constants but I'd still rather go > ahead now and fix things later. The patch is more about the test > rather than the actual change anyway. > > Jeff already ack'ed v1, maybe waiting for Kito's OK to push still. > > (Minor) changes from v1: > - Rebase vs Juzhe's patch > - Change test format to match binops. > > > This patch adds various vector constants to riscv_const_insns in order > for them to be properly recognized as immediate operands. This then > allows to emit vmv.v.i instructions via autovectorization. > > gcc/ChangeLog: > > * config/riscv/riscv.cc (riscv_const_insns): Add permissible > vector constants. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c: New test. > * gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c: New test. > * gcc.target/riscv/rvv/autovec/vmv-imm-template.h: New test. > * gcc.target/riscv/rvv/autovec/vmv-imm-run.c: New test. > --- > gcc/config/riscv/riscv.cc | 7 +++ > .../riscv/rvv/autovec/vmv-imm-run.c | 57 +++++++++++++++++++ > .../riscv/rvv/autovec/vmv-imm-rv32.c | 6 ++ > .../riscv/rvv/autovec/vmv-imm-rv64.c | 6 ++ > .../riscv/rvv/autovec/vmv-imm-template.h | 54 ++++++++++++++++++ > 5 files changed, 130 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-ru= n.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv= 32.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv= 64.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-te= mplate.h > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index 8f032250b0f..de578b5b899 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -1291,6 +1291,13 @@ riscv_const_insns (rtx x) > return 1; > } > } > + /* Constants from -16 to 15 can be loaded with vmv.v.i. > + The Wc0, Wc1 constraints are already covered by the > + vi constraint so we do not need to check them here > + separately. */ > + else if (TARGET_VECTOR && satisfies_constraint_vi (x)) > + return 1; > + > /* TODO: We may support more const vector in the future. */ > return x =3D=3D CONST0_RTX (GET_MODE (x)) ? 1 : 0; > } > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c b/g= cc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c > new file mode 100644 > index 00000000000..309a296b686 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c > @@ -0,0 +1,57 @@ > +/* { dg-do run { target { riscv_vector } } } */ > +/* { dg-additional-options "-std=3Dc99 -fno-vect-cost-model --param=3Dri= scv-autovec-preference=3Dscalable -fno-builtin" } */ > + > +#include "vmv-imm-template.h" > + > +#include > +#include > + > +#define SZ 512 > + > +#define TEST_POS(TYPE,VAL) \ > + TYPE a##TYPE##VAL[SZ]; \ > + vmv_##VAL (a##TYPE##VAL, SZ); \ > + for (int i =3D 0; i < SZ; i++) \ > + assert (a##TYPE##VAL[i] =3D=3D VAL); > + > +#define TEST_NEG(TYPE,VAL) \ > + TYPE am##TYPE##VAL[SZ]; \ > + vmv_m##VAL (am##TYPE##VAL, SZ); \ > + for (int i =3D 0; i < SZ; i++) \ > + assert (am##TYPE##VAL[i] =3D=3D -VAL); > + > +int main () > +{ > + TEST_NEG(int8_t, 16) > + TEST_NEG(int8_t, 15) > + TEST_NEG(int8_t, 14) > + TEST_NEG(int8_t, 13) > + TEST_NEG(int16_t, 12) > + TEST_NEG(int16_t, 11) > + TEST_NEG(int16_t, 10) > + TEST_NEG(int16_t, 9) > + TEST_NEG(int32_t, 8) > + TEST_NEG(int32_t, 7) > + TEST_NEG(int32_t, 6) > + TEST_NEG(int32_t, 5) > + TEST_NEG(int64_t, 4) > + TEST_NEG(int64_t, 3) > + TEST_NEG(int64_t, 2) > + TEST_NEG(int64_t, 1) > + TEST_POS(uint8_t, 0) > + TEST_POS(uint8_t, 1) > + TEST_POS(uint8_t, 2) > + TEST_POS(uint8_t, 3) > + TEST_POS(uint16_t, 4) > + TEST_POS(uint16_t, 5) > + TEST_POS(uint16_t, 6) > + TEST_POS(uint16_t, 7) > + TEST_POS(uint32_t, 8) > + TEST_POS(uint32_t, 9) > + TEST_POS(uint32_t, 10) > + TEST_POS(uint32_t, 11) > + TEST_POS(uint64_t, 12) > + TEST_POS(uint64_t, 13) > + TEST_POS(uint64_t, 14) > + TEST_POS(uint64_t, 15) > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c b/= gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c > new file mode 100644 > index 00000000000..c419256cd45 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c > @@ -0,0 +1,6 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-std=3Dc99 -march=3Drv32gcv -mabi=3Dilp32d -= fno-vect-cost-model --param=3Driscv-autovec-preference=3Dscalable -fno-buil= tin" } */ > + > +#include "vmv-imm-template.h" > + > +/* { dg-final { scan-assembler-times "vmv.v.i" 32 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c b/= gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c > new file mode 100644 > index 00000000000..520321e1c73 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c > @@ -0,0 +1,6 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-std=3Dc99 -march=3Drv64gcv -fno-vect-cost-m= odel --param=3Driscv-autovec-preference=3Dscalable -fno-builtin" } */ > + > +#include "vmv-imm-template.h" > + > +/* { dg-final { scan-assembler-times "vmv.v.i" 32 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-template.= h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-template.h > new file mode 100644 > index 00000000000..93ba5204c2e > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-template.h > @@ -0,0 +1,54 @@ > +#include > +#include > + > +#define VMV_POS(TYPE,VAL) \ > + __attribute__ ((noipa)) \ > + void vmv_##VAL (TYPE dst[], int n) \ > + { \ > + for (int i =3D 0; i < n; i++) \ > + dst[i] =3D VAL; \ > + } > + > +#define VMV_NEG(TYPE,VAL) \ > + __attribute__ ((noipa)) \ > + void vmv_m##VAL (TYPE dst[], int n) \ > + { \ > + for (int i =3D 0; i < n; i++) \ > + dst[i] =3D -VAL; \ > + } > + > +#define TEST_ALL() \ > +VMV_NEG(int8_t,16) \ > +VMV_NEG(int8_t,15) \ > +VMV_NEG(int8_t,14) \ > +VMV_NEG(int8_t,13) \ > +VMV_NEG(int16_t,12) \ > +VMV_NEG(int16_t,11) \ > +VMV_NEG(int16_t,10) \ > +VMV_NEG(int16_t,9) \ > +VMV_NEG(int32_t,8) \ > +VMV_NEG(int32_t,7) \ > +VMV_NEG(int32_t,6) \ > +VMV_NEG(int32_t,5) \ > +VMV_NEG(int64_t,4) \ > +VMV_NEG(int64_t,3) \ > +VMV_NEG(int64_t,2) \ > +VMV_NEG(int64_t,1) \ > +VMV_POS(uint8_t,0) \ > +VMV_POS(uint8_t,1) \ > +VMV_POS(uint8_t,2) \ > +VMV_POS(uint8_t,3) \ > +VMV_POS(uint16_t,4) \ > +VMV_POS(uint16_t,5) \ > +VMV_POS(uint16_t,6) \ > +VMV_POS(uint16_t,7) \ > +VMV_POS(uint32_t,8) \ > +VMV_POS(uint32_t,9) \ > +VMV_POS(uint32_t,10) \ > +VMV_POS(uint32_t,11) \ > +VMV_POS(uint64_t,12) \ > +VMV_POS(uint64_t,13) \ > +VMV_POS(uint64_t,14) \ > +VMV_POS(uint64_t,15) > + > +TEST_ALL() > -- > 2.40.0